Engineering 43
FETs-3
(Field Effect Transistors)
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Learning Goals
 Understand the Basic Physics of
MOSFET Operation
 Describe the Regions of Operation of a
MOSFET
 Use the Graphical LOAD-LINE method
to analyze the operation of basic
MOSFET Amplifiers
 Determine the Bias-Point (Q-Point) for
MOSFET circuits
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Learning Goals
 Analyze the I/O relationship for
small-signal Amplifiers
 Determine the OutPut for Various
CMOS Logic Gates
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
“Common” – What does it mean?
 “Common” is an electronics term that
usually means a digital-GROUND of
Some Sort.
 Recall that in the small Signal Case that
VDC Sources are effectively SHORTS
to the Small-Signal “Common”, or GND
Connection
• Example: A “common-source” MOSFET
amp has the source connected to smallsignal GND somehow
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Refined Small Signal Model
 The KCL Equation for the model
that accounts for the
id  g m v gs
upward iD Slope in SAT
 The Graphical Representation
vds

rd

vds

Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Common Source Amplifier
 A typical “CS” Amp Circuit
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Common Source Amplifier
 Analyze,
Qualitatively the CS
Amp Circuit
 C1 and C2 are
“Coupling”
capacitors
• C1 couples the input
to the MOSFET gate
• C2 couple the Output
to the Load, RL
 Recall for Caps
• SHORTS to fast AC
• OPENS to DC
Engineering-43: Engineering Circuit Analysis
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 CS connects the
FET SourceConnection to GND
(or Common)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Common Source Amplifier
 Analyze,
Qualitatively the CS
Amp Circuit
 Resistors R1, R2, RD,
and RS form the
Bias Network
Engineering-43: Engineering Circuit Analysis
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 The Bias Network is
designed to set the
Q-Point to allow a
large swing in the
output signal, vo, as
a result of large input
Voltage (vin = vgs)
Changes.
• The FET MUST
Remain in
SATURATION during
the entire Swing
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CS-Amp Small Signal Model
 Recall the Small Signal FET Model from
Last time
 Note that Caps & DC-Srcs are Shorts
 Yields the small signal Model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
LargeSmall Signal Model
→ Short
To AC
Signals
𝐺𝑁𝐷
𝐺𝑁𝐷
𝐷
𝐺
𝑆
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CS-Amp Voltage Gain
 Use these
equivalent
Resistances to
 By Parallel Resistors
simplify the small
R1 R2
signal Ckt
RG 
R1  R2
 Also define vin and
1
1
1
1
vo for the equivalent
 

RL rd RD RL
circuit
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CS-Amp Voltage Gain
iin
io

vin


v gs

g m v gs
 By V-Divider on Left
Loop v  vt  RG
 Thus by Ohm
 On Right (OutPut)
Loop io   g m v gs
 Thus Av:
in
R  RG
Engineering-43: Engineering Circuit Analysis
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
vo

vo  RL io  RL  g m vgs 
 Also vin  vgs
vo  RL g m v gs
Av 

  RL g m
vin
v gs Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CS-Amp input Resistance
iin

vin

 Recall R = ∆V/∆I
 For the Common
Source Amp
vin RG iin
Rin 

 RG
iin
iin
Engineering-43: Engineering Circuit Analysis
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io

v gs

g m v gs

vo

 From RG  R1 R2
R1  R2
Before
 Thus Rin
R1 R2
Rin  RG 
R1  R2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CS Amp OutPut Resistance
 To find the OUTput
Resistance
• Set v(t) = 0
– i.e.; it becomes a
SHORT
• Disconnect Load RL
• Find R Looking into
the RL terminals
 This Produces the
Ro circuit
Engineering-43: Engineering Circuit Analysis
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 Since vgs = 0 V, then
gmvgs = 0 amps
• i.e.; the dependent
current source is OPEN
 Thus can Find Ro by
Parallel combination
rd RD
Ro 
rd  RD
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Check by Thévenin: 𝑹𝒐 = 𝒗𝒐𝒄 𝒊𝒔𝒄
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Check by Thévenin: 𝑹𝒐 = 𝒗𝒐𝒄 𝒊𝒔𝒄
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
 Notes on SF Ckt
• R is the internal
(Thévenin)
resistance of the
input source
• C1 and C2 are Coupling Capacitors
– They are SHORTS to the Small Signal
• R1, R2, and RS form the Bias (Q-Pt)
Network
• In Small-Signal vd connected to GND
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
SF Large Signal Model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
SF Large Signal Model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
 Note that in this case the DRAIN is
connected to DC-Source VDD; a SHORT
to the Small Signal.
 Then the Small Signal Model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
SF Small Signal Model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
 Again, Equivalent
Resistances
R1 R2
RG 
R1  R2
1
1
1
1
 

RL rd RD RL
 Then the Equivalent
Model
 Note that in this
Circuit the Drain is
at the Bottom
(GND’d), and
Source is at the Top
Engineering-43: Engineering Circuit Analysis
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RL
RG
 By Ohm on the Rt
vo  io RL  g m vgs RL
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
RL
RG
 Note that the
• Source is at the vo Voltage
• Gate is at the vin Voltage as iin =0
 Then by KVL on
a clever Loop
Engineering-43: Engineering Circuit Analysis
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 vo  vgs  vin  0 or
vin  vgs  vo
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
 But v  i R  g v R
o
o L
m gs L
recall
 Substitute out vo in
the previous Eqn
vin  vgs  vo or
vin  vgs  g m vgs RL
 Then the Voltage
Gain (amplification)
g m vgs RL
vo
Av 

vin vgs  g m vgs RL
Engineering-43: Engineering Circuit Analysis
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RL
RG
 Factor out vgs
v gs  g m RL 
Av 
v gs 1  g m RL 
 Cancelling vgs Find
in the Small Signal
Case:
g m RL
Av 
1  g m RL
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
 The Input
Resistance
vin
R1 R2
 RG 
iin
R1  R2
RL
RG
 The probed Circuit
 For Ro
• Set v(t) = 0
– i.e.; Short it
• Remove RL
• Apply a Voltage
PROBE to SD
Connections
Engineering-43: Engineering Circuit Analysis
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 Then Ro =vx/ix
• Note that vin = 0 (no
Pwr Src) → Gterminal is at GND
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Source Follower Circuit
 And vs fixed at vx so
vgs  vg  vs  0  vx
or vgs  vx
 Now KCL at TopRight node (in = out)
vx vx
g m v gs  ix  
rd RS
 Subbing out vgs
vx vx
g m  vx   ix  
rd RS
Engineering-43: Engineering Circuit Analysis
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 Collecting Terms
vx vx
ix  
 g m vx or
rd RS
1 1

ix  vx  
 g m 
 rd RS

 Then Ro =vx/ix
vx
Ro   1
ix
1 1

 
 g m 
 rd RS

Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Recall from Chp7 Logic Gates
NOT (inverter)
NAND (all high = low, else high) NOR (any high = low, else high)
Input = 1 Output = 0
Input = 0 Output = 1
Input 1
Input 2
Output
Input 1
Input 2
Output
0
0
1
0
0
1
0
1
1
0
1
0
1
0
1
1
0
0
1
1
0
1
1
0
 Truth Tables Describe the I/O behavior
of Logic Gates, but NOT how they are
constructed
 Most Modern Logic gates are built
from collections of MOSFETS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Alternative Symbols for MOSFETs
 nMOSFETs
• “ON”: when VGS
POSITIVE
Engineering-43: Engineering Circuit Analysis
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 pMOSFETs
• “ON”: when VGS
NEGATIVE
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Alternative Symbol Meaning
 The Arrow shows the direction of
Current flow in SOURCE Connection
nFET
pFET
• In an nFET current flows: Drain→Source
– Current flows OUT of the source when FET On
• In a pFET current flows: Source→Drain
– Current flows Into the Source when FET On
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS  What is it?
 “CMOS” it the technology used in
Digital Integrated Circuits such as
MicroProcessors. The Meaning




C ≡ Complementary ← The key
M ≡ Metal
O ≡ Oxide
S ≡ Silicon
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Complementary Logic
 In Perfect Complementary Logic circuits
every nFET (or pFET) has it’s opposite,
or complementary pFET (or nFET)
 Example:
CMOS
Inverter
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Switch Model for CMOS Logic Ckts
 The INPUT to CMOS Logic Circuits is
assumed to be DIGITAL; that is the
Input is one of
• Hi (usually VDD)
OR
Lo (usually GND)
 Example: CMOS Inverter
(a)
Input is
Lo;
Output
is Hi
Engineering-43: Engineering Circuit Analysis
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(a)
Input is
Hi:
Output
is Lo
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS Inverter Summarized
 Note that SOURCE and
BODY are “tied Together”
• This is very typical for
Enhancement Mode MOSFETS
 A third Alternative seen in
Logic Ckt Analysis is the
“Invert BUBBLE” on the pFET
Engineering-43: Engineering Circuit Analysis
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nFET
pFET
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Invert-Bubble Inverter Circuit
 Using the
Inversion-Bubble
facilitates drawing
and analysis of
CMOS Logic
Circuits.
 The “Bubble”
Version of the
Inverter ckt
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS Voltage Levels for 1 & 0
 As discussed previously a “digital” 1 or
0 is represented by a RANGE (analog)
of Voltage Levels. For typical CMOS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS NAND Gate
 NAND: All Hi → Lo, else Hi
 


Basic Circuit
Engineering-43: Engineering Circuit Analysis
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A-Hi & B-Lo
Vout Connected
to VDD
BOTH A & B Hi
Vout Connected
to GND
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS NAND “Switch” Analysis
 Drawing the FETs as switches can
Speed and/or Clarify the output analysis
 

Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS NAND “Bubble” Analysis
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS NOR Gate
 NOR: Any Hi → Lo, else Hi


Basic Circuit
Engineering-43: Engineering Circuit Analysis
40
A-Hi & B-Lo
Vout Connected
to GND
 
BOTH A & B Lo
Vout Connected
to VDD
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS NOR Switch Analysis
 NOR: Any Hi → Lo, else Hi
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
WhiteBoard Work
 Determine the TRUTH Table for the
CMOS Logic Gate Below
A
L
L
H
H
Engineering-43: Engineering Circuit Analysis
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B
L
H
L
H
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Out
All Done for Today
Typical
CMOS gate
I/O Curve
 CMOS Inverter
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Engineering 43
Appendix
Other CMOS Gates
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
44
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
DC Srcs  SHORTS in Small-Signal
 In the small-signal equivalent circuit DC
voltage-sources are represented by
SHORT CIRUITS; since their voltage is
CONSTANT, the exhibit ZERO
INCREMENTAL, or SIGNAL, voltage
 Alternative Statement: Since a DC
Voltage source has an ac component of
current, but NO ac VOLTAGE, the DC
Voltage Source is equivalent to a
SHORT circuit for ac signals
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Ways to Make 1’s & 0’s
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
3-Input NAND
Ref: 2010-005. Wakerly - Chapter_03 - logic gates_VERYGood.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
CMOS Buffer (Unity Gain)
 Inverters in SERIES
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
AND Gate
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
AND-OR-INVERT gate
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
AND-OR-INVERT gate SYMBOL
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
OR-AND-INVERT gate
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
OR-AND-INVERT gate SYMBOL
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
HC CMOS Logic-Family Noise Lvls
 Noise levels
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx