Part 8: Virtual Memory
Virtual vs. Physical Address Space
 Each process has its own virtual address space, which
may be larger than the physical address space (namely
size of RAM).
 The concept of a virtual address space that is bound to a
separate physical address space is central to proper
memory management

Virtual address – generated by the CPU; also referred to
as logical address

Physical address – address seen by the memory unit
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Memory-Management Unit (MMU)
 Hardware device that maps virtual to physical address
 In MMU scheme, the value in the relocation register is added
to every address generated by a user process at the time it
is sent to memory
 The user program deals with virtual addresses; it never sees
the real physical addresses
 CPU generates virtual addresses
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The Memory Management Unit
Page
Table
Virtual
Address
Page Table
Register
Physical
Address
CPU
Data Bus
Address Bus
Memory
Cache
Memory
Management
Unit (MMU)
Translation LookAside Buffer (TLB)
RAM
I/O
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Paging
 Physical address space of a process can be
noncontiguous; process is allocated physical memory
whenever the latter is available
 Divide physical memory into fixed-sized blocks called
frames (size is power of 2, between 512 bytes and
8,192 bytes)
 Divide logical memory into blocks of same size called
pages
 Keep track of all free frames
 To run a program of size n pages, need to find n free
frames and load program
 Set up a page table to translate logical to physical
addresses
 Internal fragmentation
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Paging
 The Virtual Memory System will keep in memory the pages
that are currently in use.

It will leave in disk the memory that is not in use.
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Address Translation Scheme
 Virtual address generated by CPU is divided into:

Page number (p) – used as an index into a page table
which contains base address of each page in physical
memory

Page offset (d) – combined with base address to define
the physical memory address that is sent to the memory
unit
page number (p) page offset (d)
m-n
n
For given logical address space 2m and page size 2n
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Paging Hardware
MMU
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Paging Model of Logical and Physical Memory
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Paging Example
32-byte memory and 4-byte pages
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Free Frames
Before allocation
After allocation
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Implementation of Page Table
 Page table is kept in main memory
 Page-table base register (PTBR) points to the page
table
 Page-table length register (PRLR) indicates size of
the page table
 In this scheme every data/instruction access requires
two memory accesses. One for the page table and
one for the data/instruction.
 The two memory access problem can be solved by the
use of a special fast-lookup hardware cache called
associative memory or translation look-aside
buffers (TLBs)
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TLB via Associative Memory
 Associative memory – parallel search
Page #
Frame #
What are the differences between the page table and the
TLB?
Address translation (p, d)

If p matches a page # in TLB, get frame # from the same entry
in TLB

Otherwise get frame # from page table in memory
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Paging Hardware With TLB
MMU
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Issues
 What TLB entry to be replaced?


Random
Pseudo Least Recently Used (LRU)
 What happens on a context switch?


Process tag: change TLB registers and process register
No process tag: Invalidate/flush the entire TLB
 What happens when changing a page table entry?


Change the entry in memory
Update the TLB entry
15
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Memory Protection
 Memory protection implemented by associating protection bit with
each frame
 Valid-invalid bit attached to each entry in the page table:

“valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page

“invalid” indicates that the page is not in the process’ logical address
space
 Other memory protection bit

Non-executable (NX)

NX is not enough for code injection prevention. See video at
http://friends.cs.purdue.edu/dokuwiki/doku.php?id=code_injection
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Valid (v) or Invalid (i) Bit In A Page Table
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Hierarchical Page Tables
 Break up the logical address space into multiple page tables
 A simple technique is a two-level page table
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Two-Level Page-Table Scheme
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Two-Level Paging Example



A virtual address (on 32-bit machine with 1K page size) is divided into:

a page number consisting of 22 bits

a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:

a 12-bit page number

a 10-bit page offset
Thus, a virtual address is partitioned as follows:
page number
pi
12
page offset
p2
d
10
10
where pi is an index into the outer page table, and p2 is the displacement
within the page of the outer page table
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Address-Translation Scheme
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Demand Paging
 Bring a page into memory only when it is needed

Less I/O needed

Less memory needed

Faster response

More users
 Page is needed  reference to it

invalid reference  abort

not-in-memory  bring to memory
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Page Table When Some Pages Are Not in Main Memory
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Page Fault
 If there is a reference to a page, first reference to that page will
trap to operating system:
page fault (interrupt raised by MMU)
1. Operating system to decide:
Invalid reference  abort
 Just not in memory

2. Get empty frame
3. Swap page into frame
4. Reset tables
Set validation bit = v
1. Restart the instruction that caused the page fault
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Steps in Handling a Page Fault
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Performance of Demand Paging
 Page Fault Rate 0  p  1.0

if p = 0 no page faults

if p = 1, every reference is a fault
 Effective Access Time (EAT)
EAT = (1 – p) x memory access
+ p (page fault overhead
+ swap page out (why?)
+ swap page in
+ restart overhead
)
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Demand Paging Example
 Memory access time = 200 nanoseconds
 Average page-fault service time = 8 milliseconds
 EAT = (1 – p) x 200 + p (8 milliseconds)
= (1 – p) x 200 + p x 8,000,000
 If one access out of 1,000 causes a page fault, then
EAT = 8.2 microseconds.
This is a slowdown by a factor of 40!!
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What happens if there is no free frame?
 Page replacement – find some page in memory, but not really
in use, swap it out

algorithm

performance – want an algorithm which will result in minimum
number of page faults
 Same page may be brought into memory several times
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Page Replacement
 Prevent over-allocation of memory by modifying page-fault
service routine to include page replacement
 Use modify (dirty) bit to reduce overhead of page transfers –
only modified pages are written to disk
 Page replacement helps realizing separation between virtual
memory and physical memory – large virtual memory can be
provided on a smaller physical memory
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Need For Page Replacement
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Basic Page Replacement
1. Find the location of the desired page on disk
2. Find a free frame:
- If there is a free frame, use it
- If there is no free frame, use a page replacement
algorithm to select a victim frame
3. Bring the desired page into the (newly) free frame; update
the page and frame tables
4. Restart the process
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Page Replacement
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Page Replacement Algorithms
 Want lowest page-fault rate
 Evaluate algorithm by running it on a particular string of
memory references (reference string) and computing the
number of page faults on that string
 In all our examples, the reference string is
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
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Graph of Page Faults Versus The Number of Frames
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First-In-First-Out (FIFO) Algorithm

Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

3 frames (3 pages can be in memory at a time per process)


1
1
4
5
2
2
1
3
3
3
2
4
1
1
5
4
2
2
1
5
3
3
2
4
4
3
9 page faults
4 frames
10 page faults
Belady’s Anomaly: more frames  more page faults
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FIFO Illustrating Belady’s Anomaly
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FIFO Page Replacement
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Optimal Algorithm
 Replace page that will not be used for longest period of time
 4 frames example
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1
4
2
6 page faults
3
4
5
 How do you know this?
 Used for measuring how well your algorithm performs
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Optimal Page Replacement
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Least Recently Used (LRU) Algorithm
 Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1
1
1
1
5
2
2
2
2
2
3
5
5
4
4
4
4
3
3
3
 Timestamp implementation

Every page entry has a timestamp; every time page is
referenced through this entry, copy the clock into the
timestamp

When a page needs to be replaced, look at the timestamps to
determine which one to evict
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LRU Page Replacement
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LRU Algorithm (Cont.)
 Stack implementation – keep a stack of page numbers in a
double link form:


Page referenced:

move it to the top

requires 6 pointers to be changed
No search for replacement
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Use Of A Stack to Record The Most Recent Page References
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LRU Approximation Algorithms
 Reference bit

With each page associate a bit, initially = 0

When page is referenced bit set to 1

Replace the one which is 0 (if one exists)

We do not know the order, however
 Second chance

Need reference bit

Clock replacement

If page to be replaced (in clock order) has reference bit = 1
then:

set reference bit 0

leave page in memory

replace next page (in clock order), subject to same rules
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Second-Chance (clock) Page-Replacement Algorithm
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Counting Algorithms
 Keep a counter of the number of references that have
been made to each page
 LFU Algorithm: replaces page with smallest count
 MFU Algorithm: based on the argument that the page
with the smallest count was probably just brought in
and has yet to be used
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Exercise Question
 The operating system implements approximate page
replacement algorithms using the reference bit and the 11
history bits (as “history recorder”) in each page table entry.
At regular intervals (say, every 100 milliseconds), a timer
interrupt transfers control to the OS. The OS shifts the
reference bit for each page into the high-order bit of its 11-bit
history recorder, shifting the other bits right by 1 bit and
discarding the low-order bit. Describe how to leverage this
mechanism to approximate

(a) LRU page replacement algorithm,

(b) LFU (least frequently used) page replacement
algorithm.
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Thrashing
 If a process does not have “enough” pages, the page-fault
rate is very high. This leads to:

low CPU utilization

operating system thinks that it needs to increase the degree of
multiprogramming

another process added to the system
 Thrashing  a process is busy swapping pages in and out
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Thrashing (Cont.)
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Demand Paging and Thrashing
 Why does demand paging work?
Locality model

Process migrates from one locality to another

Localities may overlap
 Why does thrashing occur?
 size of locality > total memory size
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Locality In A Memory-Reference Pattern
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Working-Set Model
   working-set window  a fixed number of memory
accesses
Example: 10,000 instruction
 WSSi (working set of Process Pi) =
total number of pages referenced in the most recent  (varies
in time)

if  too small will not encompass entire locality

if  too large will encompass several localities

if  =   will encompass entire program
 D =  WSSi  total demand frames
 if D > m  Thrashing
 Policy if D > m, then suspend one of the processes
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Working-set model
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Keeping Track of the Working Set
 Approximate with interval timer + a reference bit
 Example:  = 10,000

Timer interrupts after every 5000 time units

Keep in memory 2 bits for each page

Whenever a timer interrupts copy and set the values of all reference
bits to 0

If one of the bits in memory = 1  page in working set
 Why is this not completely accurate?
 Improvement = 10 bits and interrupt every 1000 time units
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