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5871
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狀態 NC093FJU00428040
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輔仁大學
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電子工程學系
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學號 492506288
研究
生 林漢文
(中)
研究
生 Han-Wen Lin
(英)
論文
名稱 具階層多餘之嵌入式記憶體內建自我修復方法
(中)
論文
An Efficient Built-In Self-Repair Scheme for Embedded Memories with
名稱
Hierarchical Redundancy
(英)
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指導
教授 呂學坤
(中)
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教授 Shyue-Kung Lu
(英)
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學年 93
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字 具階層多餘
(中)
關鍵
字 Embedded Memories with Hierarchical Redundancy
(英)
在現今 system-on-a-chip 的市場上，嵌入式記憶體在系統晶片裡通常佔有
摘要 絕大部分的面積。因此，嵌入式記憶體的良率勢必決定了系統晶片的良
率。所以，在設計和製造過程中如何提高嵌入式記憶體的可靠度和良率
(中)
變成一個重要的研究議題。在這篇論文中，我們提出了一個具階層多餘
之嵌入式記憶體內建自我修復方法。這個自我修復方法的電路包含了自
我測試和自我多餘分析兩大部分。在多餘修復資源方面，我們使用了記
憶體 Word Write Mask 的特性把多餘字、多餘列和多餘行整合在同一塊記
憶體上。此外，再把多餘列和多餘行用虛擬的方式分成多餘列區塊和多
餘行組區塊。因此，在修復過程中所使用的多餘資源是以區塊為單位而
非整行或整列。另外，我們還發展了一套計算修復效能的模擬程式。這
一個模擬程式可以幫助設計者規劃所需的多餘修復資源以達到可接受的
修復率。最後的實驗結果顯示對一個 16K ? 32 SRAM 的晶片，我們提出
的修復方法可以有較低的額外硬體(1.83%)。
In today’s system-on-a-chip era, embedded memories usually occupy a
significant portion of the system chip area. Therefore, the yield of these memory
cores will dominate the SOC chip yield. How to improve the reliability and the
yield of embedded memories is an important issue for designer and fabrication. A
Built-In Self-Repair (BISR) scheme with hierarchical redundancy architecture for
embedded memories will be presented in this thesis. Our BISR circuit consists of a
摘要 built-in self-test (BIST) module and a built-in redundancy-analysis (BIRA)
module. Spare words, spare rows, and spare columns are added into the memory
cores as redundancy by using the feature of Word Write Mask. The spare rows and
(英)
spare columns of the memory are virtually divided into spare row blocks and spare
column group blocks. The address reconfiguration is performed at row block or
column block level instead of the traditional row or column level. Moreover, a
simulator is also developed for evaluating repair efficiency of redundancy analysis
algorithms. This simulator can help designer to reach an acceptable repair rate with
a specific redundancy configuration. Experimental results show that we can obtain
a high repair rate with low area overhead (1.83%) of the BISR circuit for a 16K ?
32 SRAM chip.
Contents Page Abstract (in Chinese) ????????????????????? i
Abstract ??????????????????????????? ii
Acknowledgement ??????????????????????? iii
Contents ??????????????????????????? iv List of Tables ????????????????????????
vi List of Figures ???????????????????????? vii 1
Introduction ??????????????????????? 1 1.1 Motivation and
Background ???????????????? 1 1.2 Organization ?????????????????????? 4 2
論文
Review of BIST, BISD, and BISR Techniques for Embedded Memories? 5 2.1
Fault Models & Test Algorithms?????????????? 5 2.2 Built-In Self目次 Test ??????????????????? 9 2.3 Built-In Self-Diagnosis ????????????????? 11 2.4
Built-In Self-Repair & Built-In Redundancy Analysis ????? 12 3 A BISR Scheme
of Embedded Memories with Hierarchical Redundancy? 16 3.1 Proposed BISR
Scheme ????????????????? 16 3.1.1 Proposed Redundancy Organization ?????????
16 3.1.2 Extended ESP Algorithm ?????????????? 19 3.1.3 BISR Architecture and
Procedure??????????? 28 3.2 BIST and BIRA Circuit Implementation ????????? 29
3.2.1 BIST Circuit ??????????????????? 29 3.2.2 BIRA Circuit ??????????????????
31 4 A Simulator for Evaluating Efficiency of Redundancy Analysis Algorithm 35
4.1 Simulation Flow and Graphic User Interface????????? 35 4.2 Input
Specifications??????????????????? 37 4.3 Fault Injection ??????????????????? 39
4.4 Evaluation of Repair Rate ??????????????? 41 4.5 Area
Overhead ??????????????????? 42 4.5.1 Memory Model ???????????????? 42 4.5.2
BIST Area Model ??????????????? 43 4.5.3 BIRA Area Model ??????????????? 45
5 Experimental Results ??????????????????? 47 5.1 A Practical
Example ???????????????? 47 5.2 Repair Rate Analysis ???????????????? 49 5.3
Yield Analysis ??????????????????? 55 6 Conclusions and Future
Works ????????????????? 57 6.1 Conclusions ????????????????????? 57 6.2
Future Works ????????????????????? 57 References ???????????????????????? 58
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