Senior Design Projects
National Radio Astronomy Observatory
Richard Prestage, John Ford, Mark Whitehead
Randy McCullough, Jason Ray, Tim Weadon
At 100 m, the GBT is the largest fully steerable telescope
in the world.
305 ft
485 ft
2.3 acre collecting
area
Characteristics of the GBT
Large Collecting Area
Sensitive to Low Surface Brightness
Sky Coverage & Tracking (>85%)
Angular Resolution
Frequency Coverage
Radio Quiet Zone
Unblocked Aperture
state-of-art receivers & detectors
modern control software
flexible scheduling
The Advantage of Unblocked Optics
Dynamic Range
Near sidelobes reduced by a factor >10 from conventional antennas
Gain & Sensitivity
The 100 meter diameter GBT performs better than a 120 meter conventional antenna
Reduced Interference
A telescope for cosmology
The origin and destiny of the Universe
Studying black holes and
extreme environments to
determine the fate and
age of the Universe
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A telescope for cosmology
The origin and destiny of the Universe
Measuring SunyaevZel'dovich effect to
determine the size and
scale of galactic origins
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A telescope for fundamental physics
The fastest pulsars test
our understanding of
matter at the most
extreme densities
Timing of pulsars gives the
most stringent tests of
theories of gravity
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Kramer et al 2006 Science
A Telescope Designed to be Enhanced
We have an ongoing development program to ensure the
GBT remains a vibrant, cutting-edge instrument for years to
come
All development is done in conjunction with college &
university groups around the country
A Telescope Designed to be Enhanced
Digital signal processing
Pushing the state of the art
in bandwidth and resolution
Green Bank FPGA lab building
digital signal processing hardware
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A Telescope Designed to be Enhanced
Software Engineering
Advancing astronomical software
through technologies, visualization,
and high performance computing
Upcoming data rate of >10Pb/day;
Take advantage of web-based technologies
e.g. GWT, AJAX, JAVA, Genshi
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NRAO / WVU Senior Design Projects
• We are keen to start a number of NRAO / WVU Senior Design
Projects.
• Students would be co-supervised by a WVU faculty member and an
NRAO staff member.
• We have a range of projects available; we will highlight four here.
• One project will involve computer science and development only.
• Three projects are more cross-disciplinary within electronic
engineering.
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The Projects
• A new Engineering Graphical User Interface for the GBT.
• Design and implementation of a new “artificial pulsar”
instrument test fixture.
• Design of a series of daughterboards for the standard
GBT microcontroller
• GBT Active surface control system upgrade.
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WVU Senior Capstone Project –
New Engineering Graphical User Interface
Mark Whitehead
Green Bank Software Development Division
CLEO
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CLEO 12-18 GHz Dual Feed Receiver
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CLEO Future
CLEO is a great application!
It is also 15 YO Tcl/Tk application and needs to be maintained by SDD which
already maintains a large base of C++ and Python code. Either SDD learns Tcl or
we port...
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CLEO Future
CLEO relies on an interface to the rest of the system which has grown increasingly
difficult to maintain – we would like to remove that dependency.
The rest of the system has been recently modified to use ‘data streaming’
technology and we would like to explore upgrading CLEO to use that.
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WVU Senior Capstone Project
We propose porting CLEO to C++/Python as a Senior Capstone project.
This is a software engineering project and is best suited for CS students who may
be interested in pursuing professional software development.
We recommend managing the project using an Agile Methodology (viz., Scrum)
with weekly iterations. Pivotal Tracker would be used to manage stories and track
velocity.
The GB SDD Division Head will be the “Scrum Master” and responsible for overall
management.
The original developer, an NRAO Astronomer with a successful track record and
genuine interest in working with students, would be the “Product Owner” and
responsible for feature and usability requirements.
The GB SDD would specify the technology requirements (e.g. programming
language, high-level architecture).
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WVU Senior Capstone Project
The student team would be responsible for design, implementation, testing and
documentation of the Device Explorer application.
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WVU Senior Capstone Project
This effort may involve modifications to the core monitor and control system or
the development of re-usable CLEO infrastructure libraries. Information describing
the core monitor and control system will be provided by GB SDD.
The primary result of this effort should include a working Device Explorer
application with useful documentation. If Device Explorer is delivered before the
end of the allotted time, work on the next highest priority CLEO application to port
could begin.
It is also desirable to produce a short paper, suitable for submission to the SPIE
Astronomical Telescopes and Instrumentation conference, summarizing the overall
concept, specific software issues encountered during development and results.
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WVU Senior Capstone Project –
Artificial Pulsar Test Fixture
Randy McCullough
Head of GBT Digital Electronics Groups
Wideband Artificial Pulsar
• The GBT operates extremely sophisticated digital backends to
support pulsar search and pulsar timing projects.
• Custom instrumentation designed in-house and in
collaboration with university partners using the “CASPER”
DSP toolset.
• Telescope time is extremely precious, so we need to test
offline as far as possible.
• Need a test fixture which closely approximates the natural
characteristics of an actual pulsar.
• In particular, the pulse period (in msec range) and pulse
dispersion through the interstellar medium.
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Pulsar Frequency versus pulse phase
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Project Description
• It’s currently envisioned that this design will be based upon a suitably
chosen PIC uController made by Microchip and programmed in C (or
other suitable uController); used in conjunction with a number of RF
components such as wide band noise sources, digitally controlled band
pass filters, summing amplifiers, attenuators, etc.
• Candidate(s) are expected to fully define the target functionalities and
performance parameters by conducting initial research through internet
searches, consultations with pulsar astronomers, discussions with RF and
digital engineers, etc.
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Development of draft Operator’s Manual
A basic description of the Wideband Artificial Pulsar Instrument
Target specifications
Theory of operation with block diagram(s)
Proposed schematics and/or wiring diagrams
Basic outline of proposed software design
Proposed packaging arrangement including operator controls, connectors,
etc.
• List of operator-adjustable parameters along with their adjustment ranges,
etc.
• Preliminary Bill of Materials
• Also: a proposed project schedule, estimated manpower requirements,
and estimated parts costs.
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Preliminary Design Review
• Project team members will present the documents referred to above to a
panel of reviewers comprised of pulsar astronomers, RF and digital
engineers, etc.
• The outcome of this PDR will be a set of revisions to be made to the draft
Operator’s Manual, a revised schedule, along with revised estimates of
manpower requirements and parts costs.
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Design and Construction
• At this point, the team will begin work in conjunction with RF and digital
engineers, lab technicians, and pulsar astronomers to carry out the design,
development, construction, programming, testing, and documentation of
the Wideband Artificial Pulsar Instrument.
• Design, engineering, and testing tools which may be utilized throughout
this project include:
– Autodesk Inventor (packaging and mechanical design)
– Eagle PCB (schematic capture and Printed Circuit Board Layout)
– Microwave Office (RF/Microwave design, modelling, etc.)
– Vector Network Analyzer
– Portable Spectrum Analyzer
– Portable Digital Oscilloscope
– Digital Multimeter
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Successful Completion
• The final step in completion of this project will be a technical seminar
lasting between 15 and 30 minutes to be given before a general audience
during which a summary of the project will be offered through the use of
PowerPoint slides or similar presentation tool(s).
• Project performance metrics will include: achievement of desired
specifications, adherence to projected schedule(s), resource containment
including manpower utilized and overall final parts costs, quality and userfriendliness of documentation, etc.
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WVU Senior Capstone Project –
Daughterboards for standard GBT µC
Tim Weadon
Green Bank Telescope Digital Engineer
GBT microcontroller upgrades
• The NRAO has designed a small computer card with Ethernet, I2C, SPI,
and 3.3 volt logic I/O capabilities.
• The computer is a Netburner MOD 5270 with a Motorola ColdFire 5271
uProcessor.
• The NRAO computer is a “Motherboard” that has a Xilinx Spartan 3AN
FPGA which allows the designer to interface the ColdFire to a wide range
of “Daughterboard” designs.
• The NRAO-Green Bank Servo group needs various daughterboard designs
to upgrade various subsystems on the Green Bank telescope.
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Required Expertize
• •Real-Time Software Design, Integration and Testing
• •Hardware design
• •Printed Circuit Board Schematic Capture (Using EAGLE Graphical Layout
Editor).
• •Interfacing to standard industry hardware interfaces (SPI, I2C, ColdFire
5271 Busses)
• •XILINX FPGA programming (Interfacing a Spartan 3AN with the
ColdFire 5271 and daughterboard peripheral chips).
• •Conforming to an NRAO design specification protocol between the
FPGA and the ColdFire 5271 and the external daughterboard bus.
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Technical Details
• It is assumed that various daughterboards will stack on the
motherboard through a 50 pin connector. Each daughterboard provides
one or more of the functions listed below:
– Interface to various Magnetostrictive linear transducers. (A
minimum of 6 per board)
– Provide an A/D with a minimum of 16 input channels with at least
16 bit resolution.
– Provide a D/A with a minimum of 8 channels with at least 12 bit
resolution.
– Provide a Synchro/Resolver-to-Digital Converter with at least 12
bit resolution.
• Each design shall be compatible with the NRAO design requirements
such that multiple daughterboards will be able to be mounted on one
motherboard and function simultaneously. Each board will be able to
be read from/written to every millisecond and provide the required
resolution.
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Team Responsibilities
• Each project team will be responsible for hardware, software (C++) and
firmware (VHDL) designs and will deliver an end product that meets the
project requirements. In particular each team will:
– Given the appropriate documents and background information, will
write a requirements document and get it approved by the NRAO
before proceeding to the next stage of the project.
– Choose the components, design the circuits, oversee the production of
the PCB and other necessary hardware.
– Write a software design document for the system and application code
on the MOD 5270 uProcessor.
– Write a firmware design for the Xilinx FPGA VHDL firmware.
– Write the necessary Interface documents (detailing the communication
on or between the MOD 5270, FPGA, and all busses used.)
– Write a test plan, with procedures, and demonstrate the final product to
the customer. (NRAO or Advisor)
– Provide a bill of materials, in spreadsheet form.
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Motherboard
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Example Daughterboard
RS-485 (Position Encoder Interface) Card
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WVU Senior Capstone Project –
Active Surface Controller Upgrade
Jason Ray
Green Bank Telescope Digital Engineer
GBT Active Surface
• The GBT is so large that the shape of the primary reflector changes over
elevation, mainly due to gravity.
• To correct this problem, the GBT has an active surface comprised of 2209
actuator assemblies, which can adjust the 2004 surface panels as needed to
bring the surface back to the required parabolic shape.
• The hardware components for this system were originally procured
starting in early 1992, now making them over 20 years old, and at this
point obsolete.
• Given the importance of the active surface for high frequency observing,
the control system should be upgraded with modern hardware, software,
and communications protocols.
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Existing Hardware
• The current system is based on three MV167 VME computers, with
custom VME IIOP (Intelligent Input Output Processor) boards, which
communicate with the H-Drive modules and LVDT modules.
• The H-Drive modules allow for bidirectional on/off control of 16 actuators
each. The LVDT modules are analog input modules that can monitor 16
LVDT position sensors each.
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Existing Hardware
• The actuator assembly consists of a small DC motor for movement up or
down, and an LVDT for position sensing.
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Upgrade Project
• The scope of this project will be to design and develop an upgraded and
modernized control system for the GBT Active Surface. Tasks will include:
– Planning the project
– Gathering and defining the requirements
– Designing the hardware and software
– Participating in a design review
– Writing the software
– Testing and documentation of the finished device
• The VME computers and IO cards shall be replaced by a modern computer
running Linux Redhat 64.
• The proprietary IIOP interface, for communicating between the computer
and the control modules, shall be replaced by a standard, ethernet based
interface (i.e., telnet).
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Upgrade Project
• The H-Drive and LVDT modules shall be replaced by microcontroller
based modules that will provide control/monitor for 16 actuators each.
• The current H-Drive modules only allow for simple “on/off” control of the
motors. It is desirable for the new motor control module (not necessarily
based on the H-bridge device) to have a higher quality control mechanism,
such as pulse width modulation (PWM).
• The new control system hardware, software, and communications
protocols shall all have wide commercial acceptance in order to stave off
obsolescence for as long as possible. The hardware components shall be
highly reliable and readily available from standard parts suppliers.
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Deliverables
The deliverables from this project include:
• Project plan and schedule
• Hardware design of the control modules
• Software and firmware designs for the control modules
• Control system design
• Prototype system to demonstrate the control of 16 actuators.
• Presentation of results including a demonstration of hardware
• Complete documentation of the system, including:
– Drawings
– Schematics
– PCB layout and fabrication files
– Source code for all software and firmware
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