ELI Research and Engineering,
Inc.
Presents
Do not copy or reproduce without permission of ELI R&E Inc.
Certifiable IS Performance
using
TOTAL I S
Total Object--Total Assembly Line
Information Services
Do not copy or reproduce without permission of ELI R&E Inc.
A Fundamental,
not
incremental
change in computer based
Information Technology
Architectures
Do not copy or reproduce without permission of ELI R&E Inc.
We examine TOTAL IS an
architecture which is totally new to
Information Processing, but which has
been used by manufacturing since the
beginning of the industrial revolution,
to produce
o Certifiable quality products
at
o High rates and low cost.
Which can be and often is
totally mechanized
With
A new Data Processor Architecture
Fully Automated
Using ALL Hardware control
ALL Hardware processes (“programs”)
Mechanized processes
NO Software
Do not copy or reproduce without permission of ELI R&E Inc.
Manufacturing Process
materials
PROCESS
Parts
Parts
Vendor parts
PROCESS
Vendor parts
PROCESS
PROCESS
PROCESS
PROCESS
Process operate concurrently,
Output at stepping rate of
assembly line
ASSEMBLE
Product
TOTAL
Because ALTOPS Uses Engineering disciplines
of: Specification, Testing to Specs.
Permits Electronic Processing and Assembly
lines of 100,000 or more Processing Modules
simply connected.
(in different locations if desired) - - o Running at nanosecond rates,
o Concurrently on any number and mix
of jobs.
o Is Essentially Impenerable
Do not copy or reproduce without permission of ELI R&E Inc.
Producing
Certifiably Correct Results
at rates of
100,000 to 1,000,000 per second.
Do not copy or reproduce without permission of ELI R&E Inc.
System can be built NOW of “Off The Shelf” components:
is Essentially Impenetrable
Key functions are in autonomous hardware
to insure
Account and Audit control
JOB
MANAGER
PROCESSOR
ARRAY
SYSTEM
MANAGER
INFORMATION
MANAGER
PARSING SYSTEM MANAGEMENT
SYSTEM ACCESS CONTROL
SYSTEM SECURITY CONTROL
CRYPTOGRAPHIC CONTROL
CERTIFY/ADD PROCEDURE
CERTIFY/ADD DATA/INFORMATION
LOG SYSTEM STATUS
LOG SYSTEM USE
LOG SYSTEM AUDITS
STORAGE SYSTEM ACCESS
PROCESSOR
RESOURCE MANAGER
The Processor Resource Manager Reads the Job Flow Chart:
o Assigns physical Process Nodes to Flow Chart Nodes
-Interconnects Processors
o Sends Information Manager:
-Data class ID’s
-Date-time instances
o Sends Information Manager:
-Port ID’s of Physical I/O Ports
o Monitors operations:
-Replaces failed units
Information Manager
The Information Manager:
o Never erases or writes over. Old files are archived
o Has separate, independent hardware for:
-System Records
-System Processes
-System Resources
-User Data/Information
o Reads Job data requirements:
- Queues up data
- Puts data on Bus to Process Ports as needed
Not to
scale
24”
Populated
columns
Plane has 440 chips
748 Function units
Performance potential
~1 teraOP
Board has 110 Chips
24”
Short Stack,
18 Planes
Performance Pot. 18 teraOps
30”
System
Processor
Assembly
Line
24”
ALTOPS
O-T-S
Prototype
TOTAL
ALTOPS (“Off-The-Shelf”)
Stack 3
Design Study
Stack
1
Disks
Stack 4
3,600
Stack
giga2
byte
5’
6’
6’
Machine has107,712 Function Units.
Sustained performance potential 140 teraOps/sec.
Final result rate for 100,000 instruction
commercial job, ~90,000/second
TOTAL
Some Performance Estimates of
O-T-S ALTOPS (10 teraOp)
o Matrix operation, conventional method,
(assume 10,000 of chips are pipelined
multipliers):
For a 10,000x10,000x1000 model:
Single plane, 10 to 20 ms.
Total model, 10 to 20 sec.
TOTAL
Second Generation, (Wafer Scale integration)
ALTOPS (3.5 PetaOps)
o Matrix multiplication, conventional method,
(assume 20,000 of chips are pipelined
multipliers): For a 10,000x10,000x1000
model: Single plane, 1 to 2 ms.
Total model, 1 to 2 sec.
o Note that due to the simple interconnections
of the ALTOPS architecture, “Wafer Scale”
integration is feasible.
Design study
Stack of 12” Wafers
72 Wafers Each
Total150,000
processors
ALTOPS Next
Generation
(Design Study)
Disk Stack
Disk Stack
System
System
System
System
ALTOP
Scientific Machine
~1 petaFlOps
Sustained.
3’
ALTOPS
ALTOPS
ALTOPS
Commercial
Machine
~2 petaOps
Sustained.
5’
Optical communication among
Wafers, stacks and disks
(Patent # 5,742,823 )
Prepared by ELI R&E, Inc.
BENEFITS OF TOTAL
Efficiency for Business
o Automated accounts and audits of all I.S.
activity.
o Complete model of business Information
System in I. S. Specifications enables:
o Rapid, accurate evaluation of system
changes.
o Rapid, accurate modeling of complex data
and large models.
BENEFITS OF TOTAL
Highest Protection
o Maximum Security and Privacy of Data,
No “Virus”, “Bombs”, “Denial of Service”
o System User cannot invade or discover
Intellectual Property of job being used.
o Job design owner cannot invade data
of User.
o System Owner cannot invade or discover
Intellectual Property of job design or data.
BENEFITS OF TOTAL
Efficiency for Business
o I. S. responsiveness. New applications
running in hours or a few weeks.
(Now. average time to develop new
applications about 60 months. (Ref.1))
o Results rates 100-1000 times faster
on most jobs.
o Assured continuous operation, even during
major system updates.
o More efficient, responsive control of
business processes
BENEFITS OF TOTAL
Reduces I. S. Cost
o Replaces Programming staff with a few
experts in the business or industry. Typical
saving of 80% of I. S. design cost.
(Ref. 1,4)
o Saving on average new application, (coded
locally) about $10,000,000 (Ref. 1)
o Lower cost for system, cooling, less space.
BACKGROUND
HOW IT CAME TO BE
Note: Many of the following are copies of
working documents
NOT polished presentation
TODAY’S SOFTWARE IS
UNPROVEABLE
(Reference 3.)
In the early 1970’s Edwards, (IBM
Research, Kendall and Lamb (IBM
Corp. I.S.) were trying to find a way
to make software predictable and
reliable.
Hardware can be made:
to meet specifications of Performance,
Reliability, Accuracy,
With reusable, tested components.
Hardware can be produced on high
speed assembly lines using large # of
process stations some geographically
separated.
Why can’t software?
SAGE
(Semi-Automatic Ground Environment)
Computer for first computerized air
defense system.
The IBM contract included specs. for
Performance, Reliability, Accuracy,
With firm delivery date and penalties
The IBM contract was signed 1952
In 1952 there were no:
o Computer grade components
o On-Line Real Time computer systems
o Multiprocessors
o Multiprogrammed systems
o Systems driven by unskilled operators
using graphic displays.
Working prototype was delivered 12/54
Factoring Information
Background
• Early “Tabulating machines” used by Banks
and Industry proved that:
• Any class of problem can be solved on a
• few different types of machines,
• simply connected.
• Any number of machines could work
together on any problem.
• These were electro-mechanical machines
• Running typically at 150 functions/minute.
Background
• In the early days of electronic
computers:
• The technology was so expensive only one
processor could be afforded.
• All jobs were necessarily run on this single
processor.
• A single computer time-shared system/job
control and the problem calculation.
Background
o “Compilers”, “Job monitors”, then
“Operating Systems” were invented.
o “WINDOWS” and other current
operating systems are direct derivatives.
All time share a single processor
o Today’s microprocessor architectures
are direct descendants of the early
machines.
Background
o Typical general purpose processors still
use one very fast central processing unit
(smaller than your finger nail).
o Virus and other invasions of the
System are made possible by
time-sharing
System Control and Applications
on a single processor.
Background
o Operating Systems and most programs
are so complex that verification
is not practicable (Ref. 3)
Basic code of Windows comprises
over 10,000,000 lines of code.
o A new 10,000 line program averages
about 750 “high severity” defects.
when delivered. (Ref. 1)
o A C++ programmer spends 80% of
effort removing “bugs”
Average # Defects
Delivered
80,000
5,000
250
New
Applications
Debug,
Enhance
Ave.
10,000
Max.
100,000
Ave.
1,000,000
Program Size (lines of code)
(after T. Capers Jones 2000)
Max.
10,000,000
Average HIGH-SEVERITY Defects
Delivered
~ 12,000
New
Applications
~ 750
~ 40
Debug,
Enhance
Ave.
10,000
Max. Ave.
100,000
1,000,000
Program Size (lines of code)
(after T. Capers Jones 2000)
Max.
10,000,000
Background
o “Cache misses” when the CPU must
access disks for information greatly
reduce the performance of conventional
systems.
o A cache miss rate of 0.1% reduces the
effective performance of a 1 gigaHertz
processor to slightly over 0.2 megaHertz.
o The TOTAL architecture virtually
eliminates cache misses giving efficient
performance.
Background
o A single processor computing system
spends between 70% and 80% of its time
in the operating system. The ALTOPS
processor in a TOTAL system
mechanizes the operating system functions
in separate, dedicated hardware running
concurrently. Thus time is not lost to
the operating system functions.
TOTAL
as in hardware manufacturing
requires all system Components:
o Processor and System control
o Materials (data), assemblies (information)
o Products (reports, screens, messages)
to have Specifications and Accounts that can
Be Verified to conform to Specification,
including: Function, Reliability and Accuracy .
TOTAL
Enabling: (As in hardware manufacture)
o Reusable, interchangeable data,
applications and application components.
o Any number of processor nodes of any
size or location to cooperate in producing
any information product or class of
information product.
o Assembly Line production, giving a
result rate dependent only on the
stepping rate of the line, not length.
o Results 100,000’s to millions per second.
TOTAL
Enabling: (As in hardware manufacture)
o Hardware based automation of the
system operation,
o Hardware process nodes with function
adjusted by parameters if desired,
o User applications composed of linked
sets of standard, tested hardware
modules. No “software”
o System Security No “virus”,
penetrations, “denial of service”
TOTAL
Emabling: (As in hardware manufacture)
o Prefetching of data Virtually eliminating
disk delay.
o Self repair in microseconds. (Tool failure
on a factory floor is immediately detected,
replaced and the process resumes.)
o Hardware automated Accounting and
Audit of all System Contents, Use,
Actions and Configuration.
TOTAL
All User interaction is via interactive screens.
Users’ View
o Information request: User selects from
menu: Class Identification and Instance
(viz., date time group).
o Response in milliseconds
o Run a Job: User selects Job I.D. from
menu, fills in instances of data inputs,
enters parameters if needed.
o Response in milliseconds
TOTAL
CIO View
o Authorize new user: Fill in standard screen,
Assigns security authorization for
department/information class, job class, . . .
o Authorize entry of new Application:
Verifies job design against spec., adds I.D.,
Assigns security authorizations.
o Authorize entry of new data item:
Verifies correct specification, class I.D.,
Assigns security authorizations.
TOTAL
CIO View
o Request and review System Accounts and
Audit records.
o Modify System/System Function:
Order new Function Units from Vendor, or
Contact Vendor representative to enter new
function code into System Unit ROMs
o Authorize entry of new Security Check Sum
o Establish and maintain the Classification
Structure for the Data, Information,
and Applications networks.
o Specify Enterprise Information System
structure and performance requirements.
TOTAL
Application Designer View
o Create Specification of Application Output
o Create Specification of Data/Information
Element inputs, with reliability and accuracy
requirement statements.
o Specify algorithm or process to implement
application, in normal business terms.
o Graphically select and connect
Function Modules (note) and existing
Total Object Tools “TOTS”(existing
Application Components) to construct the
application process.
TOTAL
Application Designer View
o Run the Application prototype on a
separate Test Facility to confirm result
is to Specification.
o Obtain authorization from C.I.O. to
enter the application into the System.
ALTOPS
Second Generation, (Wafer Scale integration)
ALTOPS (3.5 PetaOps)
o Davis (Ref. 2) Referring to CERN experience
and subsequent publications points out that
conventional Massively Parallel machines
tend to operate at about 10% rated peak rate
due to fitting the algorithm to the Single
Instruction stream, Multiple Device (SIMD)
architecture.
Massively Concurrent Machines (ALTOPS)
overcome this problem and operate at high
efficiency on any class of problem.
(Note)
Hardware Function Modules include:
o Standard arithmetic and logic functions
capable of assembly into any algorithm.
o Applications or Application components
specific to various classes of business
or enterprise.
o Standard accounting and audit functions.
References include but are not limited to
1. “Software Assessments, Benchmarks and
Best Practices” Jones, Capers, Addison
Wesley, 2000
2. “Highly Efficient, High Performance
Architectures”, Davis, Dr. Edward,
Chair, Computer Science, N.C. State,
Proposal to National Science Foundation,
1996