Computer Organization
and Architecture
Cache Memory
Chapter 4
Characteristics of Computer Memory
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Location
Capacity
Unit of transfer
Access method
Performance
Physical type
Physical
characteristics
• Organization
Location
• CPU
— Registers, Control Memory
— Cache – L1, L2, …
• Internal
— Main memory (RAM), consists of DRAMs
• External
— Secondary memory – hard disks
— Removable media – ZIP, CD-ROM, Tape
Capacity
• Word size
—The natural unit of organization
—Length = # bits to store a number OR = instruction
length
—But there are exceptions (CRAY, VAX etc.)
—Common word lengths: 8, 16, 32, 64 bits
• Addressable units are typically words
—But most machines allow individual bytes to be
addressed
—N = 2A, where N = size of address space A = address
length (in bits)
—On disks the addressable units are blocks or clusters
Unit of Transfer
• Internal
—#of bits read or written to/from main memory at a time
—Determined by data bus width
—May be different from word or addressable unit
• External
—Usually a block which is much larger than a word
Access Methods
• Sequential
—Start at the beginning and read through in order
—Access time depends on location of data and previous
location
—e.g. tape
• Direct
—Individual blocks have unique address
—Access is by jumping to block plus sequential search
—Access time depends on location and previous
location, but much faster than sequential access
—e.g. disk
Access Methods
• Random
—Individual addresses identify locations exactly
—Access time is independent of location or previous
access
—e.g. internal (main) memory RAM, some caches
• Associative
—Data is located by a comparison with contents of a
portion of the store
—Access time is independent of location or previous
access
—e.g. many cache systems
Performance
• Access time (TA)
—Time between presenting the address and getting the
valid data
• Memory Cycle time
—Time may be required for the memory to “recover”
before next access
—Cycle time = recovery time + access time
• Transfer Rate (R = bits / second)
—Rate at which data can be moved
N
• Sequential memory performance: T  T 
N
A
R
N = # of bits, TN = time for N bits
TA = average access time
Physical Types
• Semiconductor
— RAM (DRAM or SRAM)
• Magnetic
—Disk & Tape
• Optical
—CD & DVD
• Others
—Bubble
—Hologram
Physical Characteristics
• Decay
—E.g. magnetic memory can decay - by the effect of
radiation sources, closeness of magnetic media,
surface wear off
• Volatility
—Volatile memory: without power, memory is erased
– Magnetic memory is volatile, semiconductor can be volatile
or non-volatile
• Erasable
—Non-erasable memory cannot be altered
—E.g. ROM = Read-Only Memory
• Power consumption
Organization
• Physical arrangement of bits into words
• Not always obvious
• E.g. can be interleaved
Memory Hierarchy – multiple levels
• Slower access
• Less frequent
access
• Lower cost
• Bigger capacity
Levels of Memory Hierarchy
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Registers
L1 Cache
L2 Cache
Main memory
Disk cache
Disk
Optical storage
Tape
— The higher the level, the “closer” the memory is to
the CPU – the faster the access is to it
Locality of Reference
• During the course of the execution of a
program, memory references tend to cluster
• E.g. loops:
—Same instructions are used repeatedly - body of loop;
subroutine/function called
—Data tends to be an array or table - typically stored
at consecutive locations
• Consequently: storing related (clustered) data in
faster accessible memory improves performance
• Store related (clustered) data “closer” to the
CPU
Cache
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Small amount of fast memory
Purpose is to exploit Locality of Reference
Contains copies of portions of main memory
Sits between normal main memory and CPU
May be located on CPU chip or module
Cache operation - overview
• CPU requests a word (contents of a memory
location)
• Check cache for this word
• If present (= cache hit), get from cache (fast)
• If not present (= cache miss), read a block from
main memory, that contains this word, to cache
• Simultaneously, deliver word to CPU
• Cache includes tags to identify which block of
main memory is in each cache slot
Cache Read Operation
Cache Design
M = 2n / K blocks in RAM
C << M
blocks in cache
Typical Cache Organization
Cache Characteristics
• Size
• Mapping Function
—Direct
—Associative
—Set associative
• Replacement Algorithm
—LRU, FIFO, LFU, Random
• Write Policy
—Write through, write back, write once
• Block/Line Size
• Number of Caches
Size does matter
• Cost
—Larger cache is more expensive
• Speed
—Larger cache is faster
—But only up to a point
—Beyond which access slows down
—Because checking cache for data takes more time
Mapping Function Example Parameters
RAM size = 16 MBytes (224 bytes)
—Byte-addressable machine (1 word = 1 byte)
—RAM consists of 222 (4 M) 4 byte (word) blocks
• 24 bit address
— 224=16M
• Cache size =64 Kbytes (216 bytes)
• Cache block size = 4 bytes
—cache consists of m =214 (16k) lines of 4 byte lines
Direct Mapping
• Each block of main memory maps to only one
cache line
—i.e. if a block is in cache, it must be in one specific
place
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Address is in two parts
Least Significant w bits identify unique word
Most Significant s bits specify one memory block
The MSBs are split into a cache line field r and a
tag of s-r (most significant)
• Mapping Function: i = j mod m
where
i = cache line, j = block number
m =number of lines in cache
Direct Mapping Cache Line Table
Cache line
Main Memory blocks held
• 0
• 1
0, m, 2m, 3m, … ,2s-m
1,m+1, 2m+1, …, 2s-m+1
• m-1
m-1, 2m-1,3m-1, …, 2s-1
Note: m = 2r = 214 is the number of lines in cache
s = 22 is the block identifier
2s = 222 blocks in RAM
Direct Mapping
Address Structure
Tag s-r
8
Line or Slot r
Word w
14
2
• 24 bit address
• w = 2 bit word identifier (4 byte/word block), also called offset
• s = 22 bit block identifier
— 8 bit tag (=22-14) : distinguishes blocks that map to same cache line
— 2s-r = 28 = 64 blocks map to the same line
— r =14 bit slot# or line#: identifies cache line a particular block maps to
— m =214 lines in cache
• No two blocks in the same line have the same Tag field
• Check contents of cache by finding Line and checking Tag
Direct Mapping Cache Organization
Direct Mapping Example
Direct Mapping Summary
• Address length = (s + w) bits
• Number of addressable units = 2s+w words or
bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w =
2s
• Number of lines in cache = m = 2r
• Size of tag = (s – r) bits
• Block j maps to line i = j mod m
Direct Mapping pros & cons
• Simple
• Inexpensive
• Fixed location for given block
—A given block always maps to the same line in cache
—If a program accesses 2 blocks that map to the same
line repeatedly, cache misses are very high
—This is called thrashing
Associative Mapping
• A main memory block can load into any line of
cache
• The line is determined by a replacement
algorithm
• Memory address is interpreted as tag and word
• Tag uniquely identifies block of memory
• Every line’s tag is examined for a match
—This is done in parallel for all tags
—Requires complex circuitry
• Cache searching gets expensive
Associative Mapping
Address Structure
Word
2 bit
Tag 22 bit
• 22 bit tag stored with each 32 bit block of data
• Compare tag field with tag entry in cache to check
for hit
• Least significant 2 bits of address identify which 16
bit word is required from 32 bit data block (offset)
• e.g.
—Address
—FFFFFC
Tag
FFFFFC
Data
24682468
Cache line
3FFF
Associative Mapping Example
Fully Associative Cache Organization
Associative Mapping Summary
• Address length = (s + w) bits
• Number of addressable units = 2s+w words or
bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w =
2s
• Number of lines in cache = any
—determined by cache size, not address length
• Size of tag = s bits
• A block can map to any line, determined by a
replacement algorithm
Set Associative Mapping
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Combination of direct and associative mapping
Cache is divided into a number of sets
Each set contains a number of lines
Use direct (mod) mapping to identify a set,
replacement algorithm within the set
• Thus a block maps to any line in a given set
—e.g. Block B can be in any line of set i
• E.g. 2 lines per set
—Called 2-way associative mapping
—A given block can be in one of 2 lines in a particular
set
Set Associative Mapping
Address Structure
Tag: 9 bit
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Word
2 bit
Set: 13 bit
Use set field to determine cache set to look in
Compare tag field to see if there is a hit
Word (offset) identifies word/byte within block
e.g.
—Address
—1FF 7FFC
—001 7FFC
Tag
1FF
001
Data
12345678
11223344
Set number
1FFF
1FFF
k-Way Set Associative Cache
Organization
Two Way Set Associative Mapping
Example
Set Associative Mapping Summary
• Address length = (s + w) bits
• Number of addressable units = 2s+w words or
bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = kv = k * 2d
• Size of tag = (s – d) bits
• Block j maps to set i = j mod v
Replacement Algorithms:
Associative & Set Associative Mapping
• Hardware implemented algorithms (for speed)
• Least Recently used (LRU)
—replace the block that has not had a hit the longest time
• First in first out (FIFO)
—replace block that has been in cache longest
• Least frequently used (LFU)
—replace block which has had fewest hits
• Random
—isn’t significantly inferior
Write Policy
• Need to insure coherence of cache and main
memory
• Must not overwrite a cache block with a main
memory block unless main memory is up to
date
• Main memory might be out of date for a number
of reasons
—Multiple CPUs may have individual caches
—I/O may address main memory directly
• Cache blocks may also be made invalid
—E.g. by I/O writes to main memory
Write through
• All writes go to main memory as well as cache
• Multiple CPUs can monitor main memory traffic
to keep local (to CPU) cache up to date
• Lots of traffic
• Slows down writes
Write back
• Minimize memory writes
• Updates initially made in cache only
• UPDATE bit for a cache slot is set when update
occurs
—Portions of MM are invalid
• If block is to be replaced, write to main memory
only if update bit is set
• I/O must access main memory through cache
—Due to invalid MM contents
• Note: 15% of memory references are writes
Cache Coherence
•With multiple caches: a write policy insures only
consistency between one cache and main memory
•Other caches can still be out of sync
—If the same block is present in multiple caches, a write
invalidates not only main memory but the other caches,
too
•Cache coherence: all caches are in sync (and
the main memory, as well)
—Bus watching with write through
—Hardware synch
—Non-cacheable memory: shared memory not cached
Line Size
• Larger line (block) sizes and therefore fewer
lines can be used
—Beneficial because hit ratio is increased
—But only up to a point
—Too large line size will replace useful existing cache
content with less useful (farther words in large block)
—Probability of needing data in cache becomes less
than probability of needing data not in cache
—This will reduce hit ratio
• There is no “universal optimum”
—Depends on program characteristics
—8 to 32 byte block size seems to work well in most
situations
Unified vs. Split Cache
• Unified cache: data and instructions are cached
in the same cache
• Split cache: separate caches for data and
instructions
• Advantages of unified cache
—Balances possible imbalance between amount of data
and instructions in a program
—Only one cache needs to be manufactured
• Advantage of split cache
—Eliminates contention between INS fetch and execute
units
—Supports pipelining and speculative execution
Pentium 4 Cache
• 80386 – no on-chip cache
• 80486 – 8k cache using 16 byte lines and four way set
associative organization
• Pentium (all versions) – two on-chip L1 caches
— Data & instructions
• Pentium 4 – 2 L1 caches (on-chip)
— one instruction cache and one data cache
— 8k bytes
— 64 byte lines
— four way set associative
• L2 cache – off-chip
— Feeding both L1 caches
— 256k
— 128 byte lines
— 8 way set associative
Pentium 4 Diagram (Simplified)
Pentium 4 Core Processor
• Fetch/Decode Unit
— Fetches instructions from L2 cache
— Decode into micro-ops
— Store micro-ops in L1 cache
• Out of order execution logic
— Schedules micro-ops
— Based on data dependence and resources
— May speculatively execute
• Execution units
— Execute micro-ops
— Data from L1 cache
— Results in registers
• Memory subsystem
— L2 cache and systems bus
Pentium 4 Design Reasoning
• Decodes instructions into RISC like micro-ops before L1
cache
• Micro-ops fixed length
— Superscalar pipelining and scheduling
• Pentium instructions are long and complex
• Performance improved by separating decoding from
scheduling & pipelining
— (More later – ch14)
• Data cache is write back
— Can be configured to write through
• L1 cache controlled by 2 bits in register
— CD = cache disable
— NW = not write through
— 2 instructions to invalidate (flush) cache and write back, then
invalidate
Power PC Cache Organization
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601 – single 32kb 8 way set associative
603 – 16kb (2 x 8kb) two way set associative
604 – 32kb
610 – 64kb
G3 & G4
—64kb L1 cache
– 8 way set associative
—256k, 512k or 1M L2 cache
– two way set associative
PowerPC G4
Comparison of Cache Sizes