EC2042
EMBEDDED AND REAL TIME SYSTEMS
MCQ
1. The embedded software is also called as …………………………
Ans : firmware
2. A ……………………. System is a computing device that does a specific job.
Ans : embedded
3. Embedded systems in which some specific work has to be done in a specific time is called as
………………… systems.
Ans :realtime
4. The embedded system architechture can represented as a ……………………… architechture.
Ans : layered
5. The growing importance of embedded systems can be gauged by the availability of
………………….
Ans : processors
6. …………….. and FPGA pave the way for reducing the component of an embedded system.
Ans : PLD
7. General purpose registers constitute the processors ………………. Memory.
Ans : internal
8. Stack pointer points the …………….. in the memory.
Ans : stack
9. Data bus which carries data between processor and otherb devices are …………directional.
Ans :uni
10. The most widely used architechture in embedded systems is ………………………
Ans von Neumann
11. The ……………….. architechture consists of two memory blocks.
Ans : Harvard
12. ……………….. is a signal to the processor that some important event has occurred.
Ans : interrupt
13. Interrupts has to be processed immediately is called as ………………….. interrupt.
Ans : non-maskable
14. RISC is characterized by its limited nmber of ………………………..
Ans : instructions.
15. The two types of memory are …………….. memory and …………….. memory.
Ans :data,program
16. Firmware is stored in ……………………….., in the embedded system.
Ans : ROM
17. ………………… is used to reset the processor automatically if it does not receive a signal
periodically from processor.
Ans : watchdog timer
18. The processor identifies the peripheral by using a signal called as ………………………..
Ans :chipselect
19. The real time information is converted into electrical signals by ……………………..
Ans : sensors
20. The ……………… of a signal is the highest significant frequency component present in a signal.
Ans : bandwidth
21. The analog signals can be digitalized by sampling and ………………………..
Ans : quantization.
22. Serial Peripheral Interface is developed by ………………………..
Ans : Motorola
23. The processor generates the clock and the peripheral uses the clock to ………………….. its
acquisition of the dasta.
Ans : synchronize
24. SPI is a ………… ……………….. protocol.
Ans : master slave
25. ……………….. manages the task to achieve the desired performance of embedded system.
Ans : kernel
36.. Identify which of these are real-time applications scenarios:
An on-line bus ticketing system
Printing of annual report of a company’s annual report
Reconciling a day’s transactions in an account book of a small company
An aircrafts’ yaw control system
37.. Identify the category of the following real-time systems as “hard, soft or firm”
An on-line celebrity cricket bat auction
A patient monitoring system in an ICU
A library book reservation system
A bank’s credit card defaulters notice generation program
38.. Which of the following describes the RTOS design philiosophy best
Maximize the throughput of the system
Maximize the processor utilization
Minimizing the response time
Response within certain stipulated time period
39. Which of the following are commercially claimed RTOSs
Linux
Windows CE
Mindows NT
Vx works
Sun Solaris
40. Scheduling of tasks is a very important consideration in RTOS. Which of the following best described
the scheduling policy design:
The scheduler must follow a pre-emptive policy
The scheduler must not use pre-emptive policy option
The scheduler must not only use pre-emptive policy options with the priority considerations.
The scheduler must not use pre-emptive policy option, but must employ priority
consideration.
41. Keeping a task’s schedulability in mind, which way a task may be scheduled:
a. The task has a predetermined time after which it may be scheduled.
b. The task has a predetermined time before which it may be scheduled
c. The task has a predetermined time interval during which it must be scheduled any time.
d. The task start has a worst case delay estimate before which it must be scheduled.
42. Describe which of these scheduling policies is most suited for controlling a set of periodic tasks.
a. FCFS
b. Least laxity first
c. Earliest dead line first
d. Rate monotonic policy schedule
43. Which of the following strategy is employed for overcoming the priority inversion problem?
e. Abandon the notion of priorities altogether
f. Have only two priority levels
g. Allow for temporarily raising the priority of lower level priority process
h. Use pre-emptive policies strictly based on priorities
44. Is it true that, in general, in an embedded system the application tasks have higher priority than system
tasks?
i. Yes
j. No
45. Where are the device drivers located in RTOSs with a microkernel:
k. In the kernel space
l. In the user space
m. In separately allocated space which is neither kernel space nor user space.
46. 8051 series of micro controllers are made by which of the following companies?
a) Atmel
b) Philips
c) none of the mentioned
d) both of the mentioned
Answer: d
Explanation: Atmel series AT89C2051 and Philips family P89C51RD2 are the two most common micro
controllers of 8051 family.
47. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Answer: b
Explanation: It has 128 bytes of RAM in it.
48. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.
49. When 8051 wakes up then 0×00 is loaded to which register?
a) DPTR
b) SP
c) PC
d) PSW
Answer: c
Explanation: When a program wakes up, then 0×00 is loaded to the program counter register because at
this place the first op code is burnt.
50. When the micro controller executes some arithmetic operations, then the flag bits of which register are
affected?
a) PSW
b) SP
c) DPTR
d) PC
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity,
register bank select bits etc which are affected during such operations.
51. How is the status of the carry, auxiliary carry and parity flag affected if write instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set
to 1. In the result, the number of 1′s present are even so parity flag is set to zero.
52. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and
RS0=0 which are fourth and third bit of the register respectively.
53. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) none of the mentioned
d) both of the mentioned
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push of
element.
54.On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
55. How many bytes of bit addressable memory is present in 8051 based micro controllers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c
Explanation: 8051 micro controllers have 16 bytes of bit addressable memory.
56.In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____.
a) 000BH, a high to low transition on pin INT1
b) 001BH, a low to high transition on pin INT1
c) 0013H, a high to low transition on pin INT1
d) 0023H, a low to high transition on pin INT1
57.Serial port vector address is of _______. And causes an interrupt when ________. a) 0013H, either
TI or RI flag is set
b) 0023H, either TI or RI flag is reset c) 0013H, either
TI or RI flag is reset d) 0023H, either TI or RI flag is
set
58.In serial communication modes, mode 1 the Baud rate =
a) BR=2SMOD/32 * (Timer 0 over flow rate)
b) BR=2SMOD/16 * (Timer 1 over flow rate)
c) BR=2SMOD/16 * (Timer 0 over flow rate)
d) BR=2SMOD/32 * (Timer 1 over flow rate)
59.In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor communication and
is of ____ bit address.
a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH
60 Interfacing LCD with 89C51 _____ data lines are used along with the _____ signals.
a) 6, RS, RW b) 5, RW, EN c) 8, RS, EN, RW d) 9, RS, EN, RW
61 Resolution of ADC is defined as
a) 1/ (2N – 1) b) 2N-1 c) 1/ (2N-1)
d) 2N-1
62 In microcontroller and LCD interface which line will instruct the LCD that
microcontroller is sending data?
a) DB0 b) RW c) EN d) RS
63 Which bit of TMOD will exactly configure timer / counter as a timer or counter.
i) TMOD.6 of C/T for timer 1
ii) TMOD.6 of C/T for timer 0
iii) TMOD.2 of C/T for timer 0
iv) TMOD.2 of C/T for timer 1
a) i, ii b) ii, iv c) i, iii d) iii, iv
Key:
7.1 C 7.2 D 7.3 D 7.4 C 7.5 C 7.6 C 7.7 C 7.8 C
64.µC/OS-II RTOS (i) uses self-host development approach (ii) uses host-target development approach.
µC/OS-II is (iii) a select focus RTOS for microcontroller applications (iv) a general purpose OS with real
time functions. µC/OS-II (v) portable (vi) user programmable (vii) ROMable, (viii) scalable, (ix)
preemptive,
real time (xi) multitasking kernel.
i, iii, v and ix (b) ii, v, vii to xi (c) iii, viii to x (d) iv, v and vii to xi
65µC/OS-II RTOS has the (i) building blocks (software components) (ii) USB device and USB host (iii)
flesh memory loader (iv) memory file system (v) GUI platform (vi) probe tool for real time monitoring
(vii) TCP/IP (viii) CAN (viii) Modbus (ix) Linux driver modules.
(a) i and vi (b) all except xii (c) all except ii and vii (d) all except iii and iv
66.µC/OS-II RTOS has the (i) mailbox functions with limit on number of messages per mailbox (ii) queue
functions with limit on number of messages per mailbox (iii) mailbox functions with one message pointer
per mailbox (iv) queue functions with limit on number of message pointers per mailbox (v) OS scheduler
lock and unlock functions
(a) iii and iv (b) i, ii and v
(c) i and ii
(d) iii, iv and v
67.8.8µC/OS-II interrupt handling mechanism is (a) direct Call to an ISR by an interrupting source and
ISR sending an ISR enter message to RTOS (b) RTOS first interrupting on an interrupt, then RTOS
calling the corresponding ISR (c) RTOS first interrupting on interrupt, then RTOS calling the
corresponding ISR, the ISR sending messages to priority queue of interrupt service thread(s), which runs
by preempting the task (d) RTOS first interrupting on interrupt, then RTOS
calling the waiting ISR for the event corresponding the ISR, the ISR then sending messages to
priority queue of interrupt service thread(s), which runs by preempting the task.
68.µC/OS-II provides for lock and unlock functions are used for (i) handling ISRs (ii) critical section
in a task (iii) preventing interrupts (iv) preventing preemption by all other tasks (v) fast action
compared to use of mutex for exclusive access to system resources by a task or thread (vi) handing OS
functions (v) event functions.
(a) ii, iv and v (b) all (c) all except iv and vi (d) ii, iii and iv
69.µC/OS-II provides for (i) mutex (ii) semaphore, which can be used as mutex by initializing it as 1 (iii)
semaphore, which can be used as mutex by initializing it as 0 for (iv) handling ISRs (v) critical section in a
task (vi) preventing interrupts (vii) preventing preemption by all other tasks (viii) preventing preemption by
other tasks, which share the same resource as the task taking the mutex (ix) handing OS functions (x) event
functions.
(a) ii, iv and v (b) iii to x (c) ii, v and viii (d) ii, iii and iv
70.µC/OS-II task scheduling mechanism is (a) cooperative as well as preemptive (b) cyclic only (c)
preemptive only (d) preemptive as well as time slicing round robin.
71.If the statements #define OS_MAX_TASKS 24 and #define OS_LOWEST_PRIO 23 are used in
µC/OS-II when the user tasks, OS functions low priority tasks and OS functions high priority tasks have
the priorities between
(a) 8 and 23, 4 and 7, and 0 and 3 (b) 4 and 19, 20 and 23, and 0 and 3 (c) 0 and 15, 19 and 23, and
16 and 19 (d) 8 and 15, 16 and 23, and 0 and 7, respectively.
72.µC/OS-II functions provides for the task states (i) created and active (ii) running
(iii) suspended (iv) resumed (running) after suspension (v) delayed for number of system clock ticks
up to 216 (vi) delayed for defined hour, minute, second and millisecond (vii) resume (run) delayed
task. (viii) created and activate separately (ix) inactivated and deleted separately (x) delayed for
number of system clock ticks up to 232 (xi) delayed for defined hour, minute and second (xii)
suspended and deleted if not resumed within specified time interval (xiii) deleted and inactive.
(a) i to vii and xiii (b) all (c) ii, vii to xi (d) i, ii, iii and iv
73.µC/OS-II provides the IPC functions (i) create (ii) connect (iii) post (iv) insert (v) post front (vi) pend
(vii) delete (message) (viii) listen (ix) accept (x) flush (xi) query (xii) close (xiii) delete (queue) for using
message queue.
(a) i, iii, v, vi, ix, x, xi and xiii (b) ii, iv, vii, and x (c) all except ii (d) all except viii and ix
74.VxWorks RTOS (i) uses self-host development approach (ii) uses host-target development approach.
µC/OS-II is (iii) a select focus RTOS for microcontroller applications (iv) a general purpose OS with real
time functions. VxWorks supports (v) two concurrent OSes on a single processor layer (vi) different
context switching mechanisms for the tasks and ISRs (vii) watchdog timers (viii) signal and signal handler
functions for handling exceptions at the tasks (ix) preemptive
(x) time slicing (xi) real time (xii) multitasking kernel.
(a) i, iii, v and ix (b) ii, v to xii (c) iii, viii to x (d) iv, v and vii to xi
75.VxWorks RTOS has the (i) pipe device functions (ii) USB device and USB host
(iii) flesh memory loader (iv) multiple memory file systems (v) GUI platform (vi) probe tools trace
scope, stethoscope for real time monitoring (vii) TCP/IP (viii) CAN (viii) Modbus (ix) Linux
device driver modules (xi) POSIX functions (xii) Device software optimization.
(a) vi to xii (b) all (c) all except ii and viii (d) all except iii and iv
76.VxWorks RTOS has the (i) mailbox functions with limit on number of messages per mailbox (ii)
queue functions with limit on number of messages per mailbox (iii) mailbox functions with one
message pointer per mailbox (iv) queue functions with limit on number of message pointers per
mailbox (v) lock and unlock functions (vi) interrupt lock and interrupt unlock functions (vii) does not
support mailbox.
(a) iv, v and vii (b) i, ii and v (c) ii, v, vi and vii
(d) iii, iv and v
77.VxWorks interrupt handling mechanism is (a) direct Call to an ISR by an interrupting source and
ISR sending an ISR enter message to RTOS (b) RTOS first interrupting on an interrupt, then RTOS
calling the corresponding ISR (c) RTOS first interrupting on interrupt, then RTOS calling the
corresponding ISR, the ISR sending messages to priority queue of interrupt service thread(s), which
runs by preempting the task (d) RTOS first interrupting on interrupt, then RTOS calling the waiting
ISR for the event corresponding the ISR, the ISR then sending messages to priority queue of
interrupt service thread(s), which runs by preempting the task.
78.VxWorks provides for intLock and intUnlock functions are used for (i) handling ISRs (ii) critical
section in a task (iii) preventing interrupts (iv) preventing preemption by any other tasks (v) fast action
compared to use of mutex for exclusive access to system resources by a task or thread (vi) handing OS
functions (vii) event functions.
(a) ii, iv and v (b) all (c) all except iv and vi (d) iii and iv
79.VxWorks provides for (i) mutex (ii) semaphore, which can be used as mutex by initializing it as 1
(iii) semaphore, which can be used as mutex by initializing it as 0 for (iv) handling ISRs (v) critical
section in a task (vi) preventing interrupts (vii) preventing preemption by all other tasks (viii)
preventing preemption by other tasks, which share the same resource as the task taking the mutex (ix)
handing OS functions (x) event functions (xi) options for taking as FIFO or priority.
(a) i, v, vii and xi (b) iii to x (c) iii, v, vii and xi (d) ii, iii and iv
80.VxWorks task scheduling mechanism is (a) cooperative as well as preemptive (b) cyclic only (c)
preemptive only (d) preemptive as well as time slicing round robin.
81.If the statements are used in VxWorks for the user tasks, OS functions low priority tasks and OS
functions high priority tasks having the priorities between
(a) 100 and 200, 201 and 255, and 0 and 99 (b) 4 and 200, 201 and 255, and 0 and 3 (c) 0 and 49, 50
and 99, and 100 and 255 (d) 100 and 255, 0 and 99, and 0 and 99, respectively.
82.VxWorks functions provides for the task states (i) created and active (ii) running
(iii) suspended (iv) resumed (running) after suspension (v) delayed for number of system clock ticks
up to 216 (vi) delayed for defined hour, minute, second and millisecond (vii) resume (run) delayed
task. (viii) created and activate separately (ix) inactivated and deleted separately (x) delayed for
number of system clock ticks up to 264 (xi) delayed for defined hour, minute and second (xii)
suspended and deleted if not resumed within specified time interval (xiii) deleted and inactive.
(a) i to vii (b) all (c) i, ii, iii, iv, vii, viii, ix, x, xii and xiii (d) i, ii, iii, iv