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Techniques for Test Power Reduction in Leading Edge IP Using Cadence
Encounter Test -ATPG:
By Praveen Venkataramani

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To reduce dynamic power during test in scan based designs
To obtain test vector sequences with minimum switching and pattern count without any loss in test coverage

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3
[1]
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Test power consumption is 3x – 5x the functional power
Can cause false failures due to IR drop as a result of high switching in scan test
Shift Power
 Cause
 High toggle during shift
 Fix
 Reduction in overall toggle activity- Use fill techniques
Capture Power
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Cause
 Toggle Activity due to circuit response
Fix
 Using clock gating technique – Functional clock is gated from areas that are not required for functional operation at that time

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45nm Cortex A8 ARM IP
Functional clock - 600 MHz
Flop Count – 130,000
Clock Domains – 5 (only 1 Domain with 97%of flops is used for the experiments)
Launch on Capture
Length of Scan chains
 FULSCAN – 8 chains
 Average chain length : 17281 flip flops

 Longest chain length : 17344 flip flops
Compression- 904 chains
 Average chain length: 152 flip flops
 Longest chain length: 155 flip flops
Tool Used – Cadence Encounter Test (Cadence ET)
 Default setting
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Compaction Effort – Ultimate
Fill – Random fill
 All Flops switch at capture

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Multiple chips are tested on an automated test equipment
(ATE).
Number of available scan channels(ports) from ATE is small compared to the ports in the CUT
Available storage in ATE for test vectors
Need for decompress and compress the test vectors used for test

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[2]

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Broadcast
 One channel from the ATE fanouts (“broadcasts”)to multiple scan chains
Using XOR gates
 The vector on the scan chain is a function of the input and the
XOR gates

ATE
Broadcast Decompression/Spreader
Broadcast spreader XOR Compression
Masking logic
Scan Chain 1
Scan Chan 2
Scan Chain 3
Scan Chain n-2
Scan Chain n-1
Scan Chain n
ATE
Compressed
Output
Mask Enable pins
Scan Enable Pin
Tester clock pin
Internal
Clock generator
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ATE
XOR spreader
Masking logic
XOR Compression
Scan Chain 1
Scan Chan 2
Scan Chain 3
Scan Chain n-2
Scan Chain n-1
Scan Chain n
ATE
Compressed
Output
Mask Enable pins
Scan Enable Pin
Tester clock pin
Internal
Clock generator
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X
X
X
X
X
X
X
X
X
X

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[3]
• Types Wide 0,
Wide1, Wide 2
• CUT uses Wide2
Mask logic
• Contains 2 Mask registers R0 and R1
• Mask register is pre-loaded before scan out.
• Sets the ‘X’ to value in the Mask bit
• Prevents output data from corruption
• Some good values could be masked

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Fill Techniques in Cadence ET[4]
 Toggle activity during scan test is high
 Reduce toggle activity using fill techniques
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Random
Repeat
‘0’ or ‘1’
 Method 1: explicitly specify the fill technique
 Method 2: specify the allowed percentage toggle activity
 Method 3: Dual fill, combination of repeat and random fill.

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Filling of “Don’t-care” Bits- Fullscan Mode
(Cadence ET®)
60
Default Setting
50
40
30
20
10
0
Repeat Fill
Zero Fill
Test Sequence

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Filling of “Don’t-care” Bits- Fullscan Mode
(Cadence ET®)
60
Default setting switching
50
20
10
0
40
30
50% SFF switching
25% SFF switching
Test sequence

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60
Default Setting
Random fill after TC>70%
50
Random fill after TC>85%
40
With 50% of scan flops switching
30
With 25% of scan flops switching
20
Repeat fill after TC>70%
Full Zero Fill Repeat fill after TC>85%
10
0
0 2000 4000
Full Repeat Fill
6000
Test Sequence
8000 10000 12000 14000

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Dynamic Fault Analysis Report
Total Faults Test Coverage % Fill Type Test Sequence
Random
Zero
Repeat
100
50
25
4937768
4937768
4937768
4937768
4937768
4937768
88.51
88.41
88.47
88.51
88.52
88.53
6536
13217
8187
6536
6649
6797

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Full Scan Broad Cast XOR Compression
Fill Type Total Faults
Test sequence increase
% Reduction in Toggle
Test sequence increase
% Reduction in Toggle
Test sequence increase
% Reduction in Toggle
Maxscan_50 5270394 1.02
42.17
1.02
41.17
0.97
0.64
Maxscan_25 5270394 repeat 5270394
1.04
1.25
50.13
79.72
0.89
1.00
51.30
53.94
1.00
1.02
9.53
9.54
one zero
5270394
5270394
1.36
2.02
77.01
87.62
1.04
1.28
54.60
53.23
1.03
1.35
9.72
14.98

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Average Power Analysis using Synopsys
PrimeTime-PX [5] - Fullscan mode
Pattern
Random
Sequential Switching Power (in mW)
Repeat
Initial % Reduction Final % Reduction
3
4
5
0.0281
0.0293
0.0286
0.0166
0.0176
0.0176
40.9
39.9
38.4
0.0167
0.0174
0.0174
40.5
39.9
39.5

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IR Drop occurs due to interconnect resistance between VDD to cell or macro
VDD domains vdd_mpu and vddlsw_mpu result in maximum IR drops
For proper operation of the circuit, the minimum allowable voltage must not be below15% of the reference VDD, in this case 1.08 V.

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Max Dynamic IR Drop Gradient map-
Random Fill vector

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Max Dynamic IR Drop Gradient map-
Repeat Fill Vector

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Switching Histogram- Random Fill
Vector

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Switching Histogram- Repeat Fill
Vector

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Reason for toggle during scan capture
What is clock gating?
Results from Cadence ET

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Capture toggle occurs due to the circuit response
Difficult to control through scan in vectors
Option- to mask the flip flops that don’t need to be toggled
Use clock gates available in the circuit

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Test Clock
Domain (MHz)
Total
Number of Flip flops
Number of flip flops not controllable with clock gates
Number of flip flops controllable with clock gates
Percentage flip flops controllable
Lowest Max capture setting available
200
600
150
200
150
539
127825
64727
749
3859
2
6
2117
4
0
535
127825
375
743
1742
99.26
100
57.96
99.2
45.14
1
1
2
1
0

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Toggle Activity during Capture- Fullscan
Compaction Effort
Ultimate
None
Max Permitted Toggle% during capture none Specified
40
30
20
10 none Specified
40
30
20
10
Max Toggle activity % observed during capture
41.68
41.61
41.61
41.61
41.61
41.66
41.51
41.51
41.51
41.51

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Pattern Generation and analysis for reduction in toggle activity during scan capture.
Use the generated vector on ATE to test the CUT

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2.
3.
4.
5.
6.
7.
1.
Ravi, S. , "Power-aware test: Challenges and solutions," Test Conference, 2007. ITC 2007. IEEE
International , vol., no., pp.1-10, 21-26 Oct. 2007 doi: 10.1109/TEST.2007.4437660
http://www.cadence.com/rl/Resources/conference_papers/3.7Presentation.pdf
Vivek Chickermane, Brian Foutz, and Brion Keller. 2004. Channel Masking Synthesis for
Efficient On-Chip Test Compression. In Proceedings of the International Test Conference on
International Test Conference (ITC '04). IEEE Computer Society, Washington, DC, USA,
452-461.
Encounter Test Low Power user guide
Synopsys PrimeTime PX user guide
Apache Redhawk user guide
“The Power of RTL Clock-gating”, by Mitch Dale, http://chipdesignmag.com/display.php?articleId=915