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C H A P T E R 15

Memory Circuits

Microelectronic Circuits, Sixth Edition

Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 15.1 (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point(s) of the latch.






Figure 15.3 (a) The set/reset (SR) flip-flop and (b) its truth table.


Figure 15.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ö .







Figure 15.7 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips.




Figure 15.8 A block diagram representation of the D flip-flop.


Figure 15.9 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase non-overlapping clock whose waveforms are shown in (b).



Figure 15.10 (a) A master –slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required.



Figure 15.11 A 2 M+N -bit memory chip organized as an array of 2 M rows × 2 N columns.




Figure 15.12 A CMOS SRAM memory cell.




Figure 15.14 The normalized value of V

Q versus the ratio (W/L )

5 determine the maximum value permitted for (W/L )

5

/( W/L )

1

/( W/L )

1 for the circuit in Fig. 15.13. This graph can be used to so that is V

Q kept below a desired level.



Figure 15.15 Voltage waveforms at various nodes in the SRAM cell during a read-1 operation.








Figure 15.18 The one-transistor dynamic RAM (DRAM) cell.


Figure 15.19 When the voltage of the selected word line is raised, the transistor conducts, thus connecting the storage capacitor C

S bit-line capacitance C

B

.

to the







Figure 15.22 An arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left.





Figure 15.24 The active-loaded MOS differential amplifier as a sense amplifier.



Figure 15.25 A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address.



Figure 15.26 A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer.



Figure 15.27 A tree column decoder. Note that the colored path shows the transistors that are conducting when A

0 the address that results in connecting B

5 to the data line.

= 1, A

1

= 0, and A

2

= 1,



Figure 15.28 (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/ 6 tP

.



Figure 15.29 ( a) A one-shot or monostable circuit. Utilizing a delay circuit with a delay T and an XOR gate, this circuit provides an output pulse of width T. ( b) The delay circuit can be implemented as the cascade of N inverters where N is even, in which case T = N tP

.




Figure 15.30 A simple MOS ROM organized as 8 words ×4 bits.


Figure 15.31 (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.






Figure 15.33 The floating-gate transistor during programming.



Figure P15.11


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