Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 – Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon crystal in a two-dimensional representation. Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si When an electron breaks loose and becomes a conduction electron, a hole is also created. EE143 – Ali Javey Semiconductors, Insulators, and Conductors Ec Top of conduction band Ec E g= 9 eV empty E g = 1.1 eV Ev Ev Si, Semiconductor SiO , insulator 2 • Totally filled bands and totally empty bands do not allow current flow. (Just as there is no motion of liquid in a totally filled or totally empty bottle.) • Metal conduction band is half-filled. • Semiconductors have lower EG’s than insulators and can be doped EE143 – Ali Javey filled Conductor Ec Intrinsic Carriers electron - Bottom of conduction band Energy gap =1.12 eV hole + Top of valence band n (electron conc) = p (hole conc) = ni EE143 – Ali Javey Dopants in Silicon Si Si Si Si Si Si Si As Si Si B Si Si Si Si Si Si Si As, a Group V element, introduces conduction electrons and creates N-type silicon, and is called a donor. B, a Group III element, introduces holes and creates P-type silicon, and is called an acceptor. EE143 – Ali Javey Types of charges in semiconductors Hole Electron Ionized Donor Ionized Acceptor Mobile Charge Carriers they contribute to current flow with electric field is applied. Immobile Charges they DO NOT contribute to current flow with electric field is applied. However, they affect the local electric field EE143 – Ali Javey Fermi Function–The Probability of an Energy State Being Occupied by an Electron f (E) 1 1 e Ef is called the Fermi energy or the Fermi level. ( E E f ) / kT Boltzmann approximation: f (E) e E f (E) e EE f f (E) 1 e Ef + 2kT Ef Ef + kT Ef Ef – kT Ef – 2kT f (E) 1 e E f E kT f(E) 0.5 kT E E f kT kT Ef + 3kT Ef – 3kT EE f 1 EE143 – Ali Javey E f E kT E E f kT Electron and Hole Concentrations n N c e( E F EC ) / kT p N v e( EV E F ) / kT Nc is called the effective density of states. Nv is called the effective density of states of the valence band. Remember: the closer Ef moves up to E c , the larger n is; the closer Ef moves down to Ev , the larger p is. For Si, Nc = 2.8 1019 cm-3 and Nv = 1.041019 cm-3 . EE143 – Ali Javey Shifting the Fermi Level EE143 – Ali Javey Quantitative Relationships n: electron concentration (cm-3) p : hole concentration (cm-3) ND: donor concentration (cm-3) NA: acceptor concentration (cm-3) Assume completely ionized to form ND+ and NA- 1) Charge neutrality condition: ND + p = NA + n 2) Law of Mass Action n p = ni2 : What happens when one doping species dominates? EE143 – Ali Javey General Effects of Doping on n and p I. N d N a ni (i.e., N-type) n Nd Na p ni n 2 If N d N a , n Nd II. N a N d ni (i.e., P-type) If N a N d , p Na p ni Nd 2 and p Na Nd n ni and EE143 – Ali Javey 2 p n ni Na 2 Carrier Drift • When an electric field is applied to a semiconductor, mobile carriers will be accelerated by the electrostatic force. This force superimposes on the random thermal motion of carriers: 2 3 1 electron 4 3 2 1 electron 4 5 5 E =0 E E.g. Electrons drift in the direction opposite to the E-field Current flows Average drift velocity = | v|=mE Carrier mobility EE143 – Ali Javey Carrier Mobility • Mobile carriers are always in random thermal motion. If no electric field is applied, the average current in any direction is zero. • Mobility is reduced by 1) collisions with the vibrating atoms “phonon scattering” Si - 2) deflection by ionized impurity atoms “Coulombic scattering” BAs+ EE143 – Ali Javey Total Mobility 1600 1 1400 Electrons 1 1000 m 2 -1 -1 Mobility (cm V s ) 1200 1 phonon 1 m phonon 1 impurity 1 m impurity 800 600 400 Holes 200 0 1E14 1E15 1E16 1E17 1E18 1E19 -3 Na +Concenration Nd (cm-3) Total Impurity (atoms cm ) EE143 – Ali Javey 1E20 Conductivity and Resistivity Jp,drift = qpv = qpmpE Jn,drift = –qnv = qnmnE Jdrift = Jn,drift + Jp,drift = E =(qnmn+qpmp)E conductivity of a semiconductor is = qnmn + qpmp Resistivity, = 1/ EE143 – Ali Javey DOPANT DENSITY cm-3 Relationship between Resistivity and Dopant Density P-type N-type RESISTIVITY (cm) = 1/ EE143 – Ali Javey I V + _ W Sheet Resistance L L R Rs Wt W t Material with resistivity L Rs is the resistance when W = L (in ohms/square) Rs t if is independent of depth x • Rs value for a given conductive layer (e.g. doped Si, metals) in IC or MEMS technology is used – for design and layout of resistors – for estimating values of parasitic resistance in a device or circuit EE143 – Ali Javey Diffusion Current Particles diffuse from higher concentration to lower concentration locations. EE143 – Ali Javey Diffusion Current dn J n ,diffusion qDn dx dp J p ,diffusion qD p dx D is called the diffusion constant. Signs explained: p n x EE143 – Ali Javey x Generation/Recombination Processes Recombination continues until excess carriers = 0. Time constant of decay is called recombination lifetime EE143 – Ali Javey Continuity Equations • Combining all the carrier actions: n t n t drift nt diff nt thermalRG nt others • Now, by the definition of current, we know: n t drift n t diff ( 1 q J Nx x J Ny y J Nz z ) 1q J N • Since a change in carrier concentration must occur from a net current • Therefore, we can compactly write the continuity equation as: n t 1q J N nt thermalR G nt other p t JP 1 q p t thermalR G EE143 – Ali Javey p t other PN Junctions Donors N-type P-type – V + I I N P V Reverse bias Forward bias diode symbol A PN junction is present in almost every semiconductor device. EE143 – Ali Javey Energy Band Diagram and Depletion Layer N-region P-region Ef (a) Ec (b) Ec Ef Ev Ev Ec Ef Ev (c) Neutral N-region Depletion layer n 0 and p 0 in the depletion layer Neutral P-region Ec Ef Ev (d) EE143 – Ali Javey kT N d N a bi ln 2 q ni Qualitative Electrostatics Band diagram Built in-potential From e=-dV/dx EE143 – Ali Javey a) b) Depletion-Layer Model N Nd N eut ra l Re gion N P Na D eple tion L a yer –xn N e utral R egi on P On the P-side of the depletion layer, = –qNa xp 0 d E qN a es dx qNd xp c) –xn x –qN a qN a On the N-side, = qNd E ) ) –xn bi xp 0 qN a p E( x) e s x C e s ( x x) 1 x V EE143 – Ali Javey x E( x) qN d es ( x xn ) Effect of Bias on Electrostatics EE143 – Ali Javey Current Flow - Qualitative EE143 – Ali Javey PN Diode IV Characteristics I I 0 (e qV kT 1) Dp Dn I 0 Aqni L N L N p d n a 2 Ir I0 A EE143 – Ali Javey qniWdep τ dep MOS Capacitors MOS: Metal-Oxide-Semiconductor Vg Vg gate metal gate SiO 2 SiO 2 N+ N+ P-body Si body MOS transistor MOS capacitor EE143 – Ali Javey MOS Band Diagram – EE143 – Ali Javey Flat-band Condition and Flat-band Voltage E0 cSiO2 =0.95 eV Ec qyM qys = cSi + (Ec –Ef ) 3.1 eV cSi 3.1 eV =4.05eV Ec, Ef Ec Vfb Ev N+ -poly-Si E0 : Vacuum level E0 – Ef : Work function E0 – Ec : Electron affinity Si/SiO2 energy barrier 9 eV P-body 4.8 eV Ev SiO2 EE143 – Ali Javey Ef Ev Vfb yM ys Biasing Conditions EE143 – Ali Javey Biasing Conditions (2) EE143 – Ali Javey Depletion and the Depletion Width • The charge within the depletion region is: qVox q s qV g Wde p depletion region Ec,E f Ev M Ef Ev -- O S (b) qN A Ec • Poisson’s equation reduces to: de qN A 0 x W dx e Si e Si • Integrating twice gives: qN A 2 S W 2e Si • Or: W EE143 – Ali Javey 2e SiS qN A Surface Depletion V g > Vfb qVox q s gate ++ + + + + V -- -- -- -- -- -- -- SiO2 Wde p depletion region Ec,E f depletion layer charge, Q de p Ef Ev -- qV g Ev P-Si body Qdep qN aWdep Qs Vox (a) Cox Cox Cox M qN a 2e s s Vg V fb s Vox V fb s EE143 – Ali Javey Cox qN a 2e s s Cox O S (b) Ec Threshold Condition and Threshold Voltage threshold of inversion Ec st threshold : ns = Na A (Ec–Ef)surface= (Ef – Ev)bulk A=B, and C = D Ei C = q D B qVg = qVt Ef Ev Ec,Ef kT N a st 2 B 2 ln q ni Ev M O S kT N v kT N v kT N a q B ( E f Ev ) |bulk ln ln ln 2 q ni q N a q ni Eg EE143 – Ali Javey Threshold Voltage Vg V fb Vs Vox qN a 2e s 2 B Vt V fb 2 B Cox Summarizing both polarities: st 2 B qN sub 2e s | st | Vt V fb st Cox + : N-type device, – : P-type device EE143 – Ali Javey Strong Inversion–Beyond Threshold • Past VT, the depletion width no longer grows Vg > Vt Wdep 2e s st Wdmax gate qN a SiO 2 qV g - - - - - - - - Ef Ev --- ++++++++++ • All additional voltage - - V results in Qinversion Qinv de p P-Si substrate layer charge Ec - E c,Ef Ev Qinv Cox (Vg Vt ) (a) M O (b) EE143 – Ali Javey S Review : Basic MOS Capacitor Theory s 2B accumulation Vf b depletion Vt Vg inversion Wdep Wdmax Wdm ax = (2es 2 q a s)1/2 accumulation Vfb depletion Vt EE143 – Ali Javey Vg inversion Review : Basic MOS Capacitor Theory Qdep = qNaWdep accumulation Vfb depletion (a) 0 –qNaWdep inversion Vg Vt total substrate charge, Qs Qs Qacc Qdep Qinv –qNaWdmax Qinv Qs accumulation Vfb depletion inversion Vg Vt (b) accumulation regime depletion regime inversion regime slope = Cox Vf b 0 Vg Vt Qa cc Qinv slope = Cox slope = Cox (c) accumulation Vfb depletion Vt Vg inversion EE143 – Ali Javey Quasi-Static CV Characteristics C ox accumulation Vfb depletion C Vt Vg inversion 1 1 1 C Cox Cdep 1 1 2(Vg V fb ) 2 C Cox qN ae s EE143 – Ali Javey Qualitative MOSFET Operation Depletion Layer EE143 – Ali Javey Channel Length Modulation EE143 – Ali Javey MOSFET I-V Characteristics – A 1st attempt The Square Law Theory • Current in the channel should be mainly drift-driven d J N qm n ne qm n n dy • The current is: I D J Ny dx dz qZ d mn dy Z m n QN xc ( y ) n( x, y)dx 0 d dy EE143 – Ali Javey MOSFET I-V Characteristics – A 1st attempt • But, current is constant through the channel: VD L I D dy I D L Z m n QN d 0 0 V D Z I D m n Q N d L 0 • We know the inversion layer charge: Qinv Cox (VG VT ) • Accounting for the non-uniformity: Qinv ( y) Cox (VG VT ) 2 Z VD 0 VD VDsat I D m nCox VG VT VD L 2 VG VT EE143 – Ali Javey MOSFET I-V Characteristics – A 1st attempt • Past pinch-off, the drain current is constant I D ,VD VDsa t I D ,VD VDsa t I Dsat • So: 2 VDsat Z I D m nCox VG VT VDsat L 2 • Now, in the pinched-off region: Qinv ( y ) Cox (VG VT VDsat ) 0 VDsat VG VT Z ID m nCox VG VT 2 2L EE143 – Ali Javey N-channel MOSFET Layout (Top View) 4 lithography steps are required: 1. active area 2. gate electrode 3. contacts 4. metal interconnects EE143 – Ali Javey Simple NMOS Process Flow 1) Thermal oxidation (~10 nm “pad oxide”) 2) Silicon-nitride (Si3N4) deposition by CVD (~40nm) 3) Active-area definition (lithography & etch) 4) Boron ion implantation (“channel stop” implant) EE143 – Ali Javey Simple NMOS Process Flow 5) Thermal oxidation to grow oxide in “field regions” 6) Si3N4 & pad oxide removal 7) Thermal oxidation (“gate oxide”) 8) Poly-Si deposition by CVD 9) Poly-Si gate-electrode patterning (litho. & etch) 10) P or As ion implantation to form n+ source and drain regions Top view of masks EE143 – Ali Javey Simple NMOS Process Flow Top view of masks 11) SiO2 CVD 12) Contact definition (litho. & etch) 13) Al deposition by sputtering 14) Al patterning by litho. & etch to form interconnects EE143 – Ali Javey