InterPACK'01
The Pacific Rim/ASME International Electronic Packaging Technical Conference and Exhibition
July 8–13, 2001, Kauai, Hawaii, USA
An Object-Oriented Internet-based Framework
for Chip Package Thermal & Stress Simulation
IPACK2001-15810
1Russell
S. Peak, 2Ryuichi Matsuki, 1Miyako W. Wilson,
1Donald Koo,1Andrew J. Scholand, 2Yukari Hatcho, 1Sai Zeng
Georgia Tech 1
Engineering Information Systems Lab
eislab.gatech.edu
Shinko Electric Industries Co., Ltd. 2
Package Design Center
Nagano, Japan
www.shinko.co.jp
Phase 1 Summary - Shinko Project
Abstract Accepted for InterPACK'01
http://www.asme.org/conf/ipack01/
An Object-Oriented Internet-based Framework for
Chip Package Thermal and Stress Simulation
1
Russell S. Peak, 2Ryuichi Matsuki, 1Miyako W. Wilson, 1Donald Koo,
1
Andrew J. Scholand, 2Yukari Hatcho, 1Sai Zeng
1
Engineering Information Systems Lab
Georgia Institute of Technology
Atlanta, Georgia USA
http://eislab.gatech.edu/
2
Package Design Center
Shinko Electric Industries Co., Ltd.
Nagano, Japan
http://www.shinko.co.jp/
Abstract
Simulating the behavior of electronic chip packages like ball grid arrays (BGAs) is important to guide and
verify their designs. Thermal resistance, thermomechanical stress, and electromagnetics impose some of
the main challenges that package designers need to address. Yet because packages are composed of
numerous materials and complex shapes, with current methods an analyst may spend hours to days creating
simulations like finite element analysis (FEA) models.
This paper overviews work to reduce design cycle time by automating key aspects of FEA modeling and
results documentation. The main objective has been automating FEA-based thermal resistance model
creation for a variety of package styles: quad flat packs (QFPs), plastic BGAs (PBGAs), and enhanced
BGAs (EBGAs). Pilot production tools embody analysis integration techniques that leverage rich product
models and idealize them into FEA models. We have also demonstrated how the same rich product models
can drive basic stress models with different idealizations.
In this framework, Internet standards like CORBA enable worldwide access to simulation solvers (e.g.,
Ansys and Mathematica). Automation and ease-of-use enable access by chip package designers and others
who are not simulation specialists. Pilot industrial usage has shown that total simulation cycle time can be
decreased 75%, while modeling time itself can be reduced 10:1 or more (from hours to minutes).
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
2
Chip Package Products
Shinko
Quad Flat Packs (QFPs)
Plastic Ball Grid Array (PBGA) Packages
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
3
VTMB = variable topology multi-body
Traditional VTMB FEA Model Creation
Manually Intensive: 6-12 hours
FEA Model Planning Sketches - EBGA 600 Chip Package
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
4
Outline

Analysis Integration Background
– CAD-CAE Interoperability Research & Development



© 1993-2001 GTRC
Chip Package Analysis Tool Overview
On Automating Variable Topology Multi-Body
(VTMB) FEA Problems
Summary
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
5
X-Analysis Integration Techniques
X = Design, Mfg., Sustainment, …
a. Multi-Representation Architecture (MRA)
3
Analyzable
Product Model
Design Model
4 Context-Based Analysis Model
2 Analysis Building Block
1 Solution Method Model
CBAM
ABB
Solder
Joint
material
C
L

Epoxy
PWB
body3
h1
APM ABB
core: FR4
Plane Strain Bodies System
2 ABB

 total height, h c
base: Alumina
ABBSMM
body 1
body4
Solder Joint
Solder Joint Plane Strain Model
4 CBAM
Component
Solder
Joint
T0
Component
 linear-elastic model
 primary structural
SMM
APM ABB
Analysis Model
PWA Component Occurrence
3 APM
APM
Printed Wiring Assembly (PWA)
Component
b. Explicit Design-Analysis Associativity
body 1
body 4
body
body 2
body 2
PWB
Printed Wiring Board (PWB)
Design Tools
4 CBAM
Analysis Module Catalogs
Analysis Procedures

3 APM
sj
solder joint
shear strain
range

Lc
total height
hc
primary structural material
T0
linear-elastic model
length 2 +
total thickness
Product
Model
1.25
[1.1]
Physical Behavior Research,
Know-How, Design Handbooks, ...
Commercial
Design Tools
pwb
(Module Usage)
Selected Module
Solder Joint Deformation Model
Commercial
Analysis Tools
primary structural material
solder
hs
linear-elastic model
rectangle
solder joint
ECAD
Idealization/
Defeaturization
Component
Solder Joint
[1.1]
detailed shape
[1.2]
linear-elastic model
[2.1]
© 1993-2001 GTRC
Ts
average
bilinear-elastoplastic model
Ansys
CAE
PWB
APM  CBAM  ABB SMM
Tc
Ls
[1.2]
[2.2]
MCAD
Plane Strain
Bodies System
(Module Creation)
component
1 SMM
deformation model
Fine-Grained Associativity
approximate maximum
inter-solder joint distance
component
occurrence
c
ABB SMM
2 ABB
Ubiquitization
Ubiquitous Analysis
3
plane strain bodyi , i = 1...4
geometryi
materiali (E,  ,  )
Informal Associativity Diagram
Solution Tools
c. Analysis Module Creation Methodology
To
a
L1
h1
stress-strain
model 1
T1
L2
h2
stress-strain
model 2
T2
geometry model 3
stress-strain
model 3
T3
 xy, extreme, 3
T sj
 xy, extreme, sj
Constrained Object-based Analysis Module
Constraint Schematic View
Abaqus
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
6
An Introduction to X-Analysis Integration (XAI)
Short Course Outline
Part 1: Constrained Objects (COBs) Primer
– Nomenclature
Part 2: Multi-Representation Architecture (MRA) Primer
– Analysis Integration Challenges
– Overview of COB-based XAI
Part 3: Example Applications
» Airframe Structural Analysis (Boeing)
» Circuit Board Thermomechanical Analysis
(DoD: ProAM; JPL/NASA)
» Chip Package Thermal Analysis (Shinko)
– Summary
Part 4: Advanced Topics & Current Research
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
7
Outline

Analysis Integration Background
– CAD-CAE Interoperability Research & Development



© 1993-2001 GTRC
Chip Package Analysis Tool Overview
On Automating Variable Topology Multi-Body
(VTMB) FEA Problems
Summary
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
8
Tool Usage Overview
Preliminary Design
Analysis Module Setup & Usage
1
2b
3a
Automated FEA Meshing & Solution
2a
© 1993-2001 GTRC
Thermal Results
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
3b
Documentation
Assistance
9
Flexible High Diversity Design-Analysis Integration
Electronic Packaging Examples: Chip Packages/Mounting
Shinko Electric Project: Phase 1 (completed 9/00)
Design Tools
y
L
L
Lo
F
material model
youngs modulus, E
mv6
cte, 
mv5
sr1
temperature, T
reference temperature, To
ts1
E
T  T  To
L
A
ts2
Shaft
Sleeve 2
smv1
ds1
area, A
r4
F

A
A
Leff
linkage
e

s
Sleeve 1
force, F
mv4
F
E, A, 
T, ,  x
One D Linear
Elastic Model
(no shear)
ds2
T
t


mv2
elastic strain, e
mv3
thermal strain, t
mv1
strain,
effective length, Leff
Prelim/APM Design Tool
XaiTools ChipPackage
start, x1
end, x2
cross section:
effective ring
r1
reaction
material
L  L  Lo
L  x2  x1
allowable
L
r3 ro
outer radius,
L
linear elastic model
allowable stress
twist mos model
Margin of Safety
(> case)
polar moment of inertia, J

r2
condition
Torsional Rod
stress,al1

temperature change,T
mode: shaft torsion
undeformed length, Lo
deformation model
al2a
al2b
shear modulus, G
al3
total elongation,L
length, L
Lo

1
2
Modular, Reusable
Template Libraries
J
r

G

T
stress mos model
allowable
twist
Margin of Safety
(> case)
allowable
actual
actual
MS
MS
Analyzable
Product Model
PWB DB
Analysis Modules (CBAMs)
of Diverse Behavior & Fidelity
Thermal
Resistance
Analysis Tools
XaiTools
General Math
ChipPackage
Mathematica
FEA
Ansys
3D
XaiTools
Materials DB*
Thermal
Stress
EBGA, PBGA, QFP
PKG

Basic
3D**
Chip
Cu
Ground
** = Demonstration module
© 1993-2001 GTRC
Basic
Documentation
Automation
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
Authoring
MS Excel
10
Using Internet/Intranet-based Analysis Solvers
Thick Client Architecture
Users
Self-Serve
Engineering Service Bureau (ESB)
Client PCs
Server Machines
Internet/Intranet
© 1993-2001 GTRC
EIS Lab
CORBA Daemon
Iona orbixdj
- Regular internal use
U-Engineer.com
CORBA Servers
XaiToolsAnsys
Ansys
XaiTools
XaiTools
Math.
XaiTools
SolverAnsys
Server
Solver
Server
Solver
Server
Solver Server
FEA Solvers
Ansys
Math Solvers
- Demo usage:
- US
- Japan
Nov.’00-Present:
Electronics Co.
- Began production usage
(dept. Intranet)
Future:
...
XaiTools
CORBA
IIOP
Internet
Thick Client
June’99-Present:
Mathematica
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
Company Intranet
and/or
U-Engineer.com
(commercial)
- Other solvers
11
APM Design Tool
Preliminary Design of Packages - PBGA Screens
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
APM =
analyzable
product model
12
Example Chip Package Idealizations (PBGA)
Idealization for solder-joint/thermal ball
[ Outer Balls ]
Average Thermal Conductivity
Vertical Direction
v: v = Vff+(1-Vf )m [W/mK]
Horizontal Direction h: 1/h = Vf/f+(1-Vf )/m [W/mK]
y2 y1
Where:
f: thermal conductivity of solder ball [W/mK]
m: thermal conductivity of air [W/mK]
Vf: volume ratio of solder ball
x1
Idealization for thermal via
% Ball Area = (Pi * (ball diameter / 2)^ 2) / (x2 * y2 - x1 * y1 )
x2
[ Inner Balls (Thermal Balls) ]
r : a radius of ball
l : a side length of square
x : number of balls
y : number of squares
r
+
l
x r
Thermal Conductivity
2
(Ball value in all directions)
y

l
r
r
=
5 - 10 Balls
Equation for Total
Sectional Via Area
R r

S  R 2  r 2  n
l
-
S : total section area of vias
R : outer 
r : inner 
n : number of via
Via + Air
=
Air
Via
Courtesy of Shinko - see [Koo, 2000]
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
13
COB-based Analysis Template
Typical Input Objects for EBGA Thermal Resistance Module
COB =
constrained
object
Customized
Analysis Module Tool
with idealized
package cross-section
Generic COB Browser
with design and analysis objects
(attributes and relations)
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
14
COB-based Analysis Template
Typical Highly Automated Results
Analysis Module Tool
COB =
constrained
object
Auto-Created
FEA Inputs
(for Mesh Model)
FEA
Temperature
Distribution
Thermal Resistance
vs.
Air Flow Velocity
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
15
Test Cases - Shinko
Auto-Generated FEA Mesh Model of PBGA 256 with Thermal Vias
FEA mesh model with
strong inter-body coupling
Small
Idealized Vias
29 idealized bodies
10 idealized materials
1 main pattern
~3 sub patterns
© 1993-2001 GTRC
Thin
Copper Layers
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
16
Results Validation
EBGA 352 (4L-PCB)
14
Thermal
resistance
12
 ja [degreeC/W]
10
COSMOS (PB)
8
COSMOS (BB)
ANSYS (PB)
ANSYS (BB)
6
Measure
(a)
(b)
(c)
4
2
0
0
1
2
3
4
Air Flow Velocity [m/s]
Good comparisons:
© 1993-2001 GTRC
(a) simulation via VTMB algorithm (in XCP)
(b) simulation via traditional manual approach
(c) physical measurements
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
17
Outline

Analysis Integration Background
– CAD-CAE Interoperability Research & Development



© 1993-2001 GTRC
Chip Package Analysis Tool Overview
On Automating Variable Topology Multi-Body
(VTMB) FEA Problems
Summary
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
18
VTMB = variable topology multi-body
Traditional VTMB FEA Model Creation
Manually Intensive: 6-12 hours
FEA Model Planning Sketches - EBGA 600 Chip Package
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
19
Variable Topology Multi-Body (VTMB)
FEA Meshing Challenges
Idealized Analytical Bodies
Design
Model
Decomposed FEA Geometry Models
1a
1b
2
1c
3a
3b
Meshing
& Solving
1
2
3
original
Labor-intensive
“chopping”
3c
1a
1b
1c
2
1d
1e
3a
3b
1
2
3
topology change (no body change)
2
3
1
4
1a
1b
2
3
1c
1d
4a
4b
4c
body change (includes topology change)
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
20
Product Information-Driven FEA Methodology
Purpose of VTMB Methodology
thermal stress CBAMs
PWB APMs
VTMB
Methodology
Chip package APMs
VTMB FEA Models thermal resistance CBAMs
create algorithmij
once
algorithmij
use algorithmij
many times
ANSYS SMMs
Design Instances
Analysis Instances
Design Types i = 1…m
Analysis Types j = 1…n
for a given ij
j{1…n} (not all design types have all analysis types)
e.g.) for i=1(EBGA), j=1(thermal resistance) j=2 (thermal stress)
for i=2 (PWB), j=1 (warpage)
VTMB= variable topology multi-body
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
21
Methodology
Scope of VTMB algorithmij for cbamij
[Tamburini, 1999]
Context-Based
Analysis Model
(CBAM)
[Peak, 2001]
Analysis
Context
Part Feature
& Assembly Structure
Analyzable
Product Model
Boundary Condition
Objects & Discipline
Conditions &
Next-Higher
CBAMs
VTMB
algorithmij
for cbamij
Analysis Subsystems
Pseudo-Analysis
Building Blocks
(pseudo-ABBs)
[Koo, 2000]
idealizations, 
Step 2
Step 1a
transformations,
Step 1b
Solution
Method Models
(SMMs)
boundary variables
Step 3
Behavior/Mode
allowables
Objectives
MoS
© 1993-2001 GTRC
allowable
actual
Associativity
Linkages, 
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
Step 4
22
Design Changes with Large Topology Impact
Example Variations: PBGAs & EBGAs
EBGA 600
with
2 Steps
PBGA 313
with
Thermal Vias &
Thermal Balls
EBGA 325
with
No Steps
2D partial views of 3D models
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
23
Design Change with Small Topology Impact
Heat Spreader Size Variations - EBGA 600
Idealized Analytical Models
thin & large
thick & small
FEA Mesh Models
z-direction topology changes
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
2D partial views of 3D models
24
Test Cases - Shinko
Auto-Generated FEA Model: QFP PCDPH
FEA mesh model with
strong inter-body coupling
23 idealized bodies
9 idealized materials
1 main pattern
~3 sub patterns
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
25
Design Changes with Large Topology Impact
Example Variations: QFPs
QFP 208 DPH
HS/Tape
QFP 128 SL
Die Pad
2D partial views of 3D models
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
26
Basic Stress Analysis Module Tool
Highly automated FEA model creation
PBGA 625
Re: thermal model:
• Same APM
(but different
idealizations)
• CORBA-based
solvers, etc.
Pattern-based
meshing
• Adjustable
mesh density
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
27
Multi-Fidelity Idealizations
Mode-dependent Idealized Geometries; Same Dimension
Thermal Resistance Idealized Geometry (3D)
FEA Model
Common Design Model
Thermal Stress
© 1993-2001 GTRC
Idealized Geometry (3D)
FEA Model
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
28
Outline

Analysis Integration Background
– CAD-CAE Interoperability Research & Development



© 1993-2001 GTRC
Chip Package Analysis Tool Overview
On Automating Variable Topology Multi-Body
(VTMB) FEA Problems
Summary
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
29
VTMB = variable topology multi-body technique [Koo, 2000]
Pilot & Initial Production Usage Results
Product Model-Driven Analysis


Reduced FEA modeling time > 10:1 (days/hours  minutes)
References
Reduced simulation cycle > 75%
[1] Shinko 5/00 (in Koo, 2000)
[2] Shinko evaluation 10/12/00
Analysis Model Creation Activity
With Traditional
Practice
With VTMB
Methodology*
Example
Create initial FEA model (QFP cases)
8-12 hours
10-20 minutes
QFP208PIN
Create initial FEA model (EBGA cases)
6-8 hours
10-20 minutes
EBGA352PIN
Create initial FEA model (PBGA cases)
8-10 hours
10-20 minutes
PBGA256PIN
Create variant - small topology change
0.3-6 hours
(10-20 minutes) - Moderate dimension change
(e.g., EBGA 600 heat sink size variations)
Create variant - moderate topology change
(6-8 hours)-
(10-20 minutes) - Add more features
(e.g., increase number of EBGA steps)
Create variant - large topology change


(6-8 hours)+
(10-20 minutes)or N/A
Add new types of features
(e.g., add steps to EBGA outer edges)
Enables greater analysis intensity  Better designs
Leverages XAI / CAD-CAE interoperability techniques
– Objects, Internet/web services, ubiquitization methodology, …
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
30
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
31
Summary of Tools and Services
offered via Georgia Tech Research Corp.
http://eislab.gatech.edu/

XaiTools FrameWork
™
– General-purpose analysis integration toolkit

Product-Specific Toolkits
– XaiTools PWA-B™
– XaiTools ChipPackage™

™
U-Engineer.com
– Internet-based engineering service bureau (ESB)
– Self-serve automated analysis modules  Full-serve consulting

Research, Development, and Consulting
–
–
–
–
Analysis integration & optimization
– Short courses
Product-specific analysis module catalogs
Internet/Intranet-based ESB development
Knowledge-based engineering & information technology
» PDM, STEP, GenCAM, XML, UML, Java, CORBA, Internet, …
– CAD/CAE/CAM, parametric FEA, thermal & mechanical analysis
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
32
For Further Information ...

EIS Lab web site: http://eislab.gatech.edu/
– Publications, project overviews, tools, etc.
– See: Publications  DAI/XAI  Suggested Starting Points
X-Analysis Integration (XAI) Technology
http://eislab.gatech.edu/pubs/reports/EL002/

XaiTools home page: http://eislab.gatech.edu/tools/XaiTools/

Pilot commercial ESB: http://www.u-engineer.com/
– Internet-based self-serve analysis
– Analysis module catalog for electronic packaging
– Highly automated front-ends to general FEA & math tools
™
© 1993-2001 GTRC
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
33
Nomenclature



ABB
AMCOM
APM
CAD
CAE
CBAM
COB
COI
COS
CORBA
DAI
EIS
ESB
FEA
FTT
GUI
IIOP
MRA
ORB
OMG
PWA
PWB
SBD
SBE
SME
SMM
ProAM
PSI
STEP
VTMB
XAI
XCP
XFW
XPWAB
© 1993-2001 GTRC
ABB-SMM transformation
idealization relation between design and analysis attributes
APM-ABB associativity linkage indicating usage of one or more i
analysis building block
U. S. Army Aviation and Missile Command
analyzable product model
computer aided design
computer aided engineering
context-based analysis model
constrained object
constrained object instance
constrained object structure
common ORB architecture
design-analysis integration
engineering information systems
engineering service bureau
finite element analysis
fixed topology template
graphical user interface
Internet inter-ORB protocol
multi-representation architecture
object request broker
Object Management Group, www.omg.com
printed wiring assembly (a PWB populated with components)
printed wiring board
simulation-based design
simulation-based engineering
small-to-medium sized enterprise (small business)
solution method model
Product Data-Driven Analysis in a Missile Supply Chain (ProAM) project (AMCOM)
Product Simulation Integration project (Boeing)
Standard for the Exchange of Product Model Data (ISO 10303).
variable topology multi-body
X-analysis integration (X= design, mfg., etc.)
XaiTools ChipPackage™
XaiTools FrameWork™
XaiTools PWA-B™
Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu
34