An Integrated Physical-Electrical
Design Verification Flow
Emad Hegazi
SysDsoft Inc.
Hazem Hegazy
Mentor Graphics
Outline

Motivations

Design yield & Verification challenges

Verification framework requirements

Examples
2
Motivations
 Design robustness and reliability
 Circuit verification automation
 Design-yield-based rather than Fabrication-yieldbased tools
 Rules complexity (Topology-aware)
 Multi-tool flow
3
Design/Fabrication Yield!
Fabrication Yield
•
•
•
•
Physical implementation
Defect shapes/layout features
#of Defects/Wafer
Where on wafer/process steps
Design Yield
•
•
•
•
Performance
Compliance
Functional
Physical and electrical effects
4
Verification Challenges
System Implementation
Frontend Simulation
-Architecture
-Configurations
-Power domains
-Interactions
-OP data
-Logical operations
-Elec. behavior
Physical Implementation
-Design rules
-Requirements
-EM
Analysis, verification and validation
5
Verification Framework Requirements
……
Sim.
Data
Device
Ext.
Geoprocessing
Circuit ID
..
Shared Database
 Topology-aware verification platform
—
—
—
—
—
Define and Identify certain configurations
Geometrical measurements
Circuit extraction
Simulation data
Up/down stream usage
6
Mentor Graphics CONFIDENTIAL
Copyright ©-2008, Mentor Graphics.
Circuit/Topology-aware Examples
LDO
3.3 V
LDO
Pierce Crystal Oscillator (XO):

OUT
OUT
Normal ESD rules will
overlook a CDM problem
1.2 V
XO
IN

IN
Path to external supply is
higher in resistance
LDO

LDO
Internal supply, LDO, is the
targeted least resistive path
OUT
3.3 V
3.3 V
RESD
RESD
IN
7
OUT
CDM charge
IN
Circuit/Topology-aware Examples….
VDD
Frequency Divider Shutdown:



Cascaded common mode
stages
Turn-off current sources is
the common approach
Special setup to avoid
electrical problems
8
Turn-off
High
High
Inputs
Float
Example: Current Mirror Design Robustness
Introduction



Commonly used circuits
Few transistors
Highly sensitive to
mismatch:
- Geometrical
- Electrical

Shutdown enabled
9
Io
M1
M2
MshD
Practical Implementation issues

Noisy bias current

Noise filtering

Io
M1
Shutdown device position
MshD
10
R
R
C
C
M2
MshD
What About Mismatch?

Geometrical:
- W/L ratios…Symmetry
- Topology related DRC rules


OD extension
IR-Drop
Electrical:
- IR-Drop due to leakage

Io
ILeakage Igate
M1
R
R
C
Geo-Electrical:
- Stress differences
11
M2
Isub
C
Sh_D
Calibre PERC Overview
 Schematic/Layout Verification
 Fully integrated into Calibre
 Prevent Chip Failure
- ESD
- Multi-Domain
 Integration of Topology identification, Geometry
and Electrical rule checking
- User-configurable verification
 Validate electrical compliance/design guidelines
12
Verification Strategy
1.
2.
3.
Current mirror topology identification
according to user definition.
If found, examine the presence of shut down
transistor and it proper placement.
Perform geometrical measurements:
a)
b)
4.
5.
6.
STI for both M1 and M2 transistors
Topology related DRC rules like OD extension.
Get SPICE operating point gate leakage current
from simulation database.
Calculate the total resistance in noise filter and
multiply by leakage current to examine
compliance versus x%
Flag violations if found in any of the above steps
13
SPICE
Rules
DB
Calibre PERC
Schematic
Netlist
Layout
Design
Violations
Verification Strategy Flowchart
Define Topology
 Combined flow
Found
NO
Pass
YES
Shutdown
Transistor
 Able to verify:
- Physical checks
- Electrical checks
Spice
NO
In-place
YES
Electrical mismatch check
 Integrated flow
Geometrical mismatch check
Violation
Leakage IR drop exceeds x%
Pass
Stress mismatch/DRC violations
End
14
MshD not connected properly
OP database
Rule Example
proc rule_1 {}
{
perc::check_net -netType { Gate1 } -pathType { Gate2 } cellName { ! RC } -condition {cond_1} -comment "Error in mirror
configuration"
}
proc cond_1 {net} {
set result [perc::count -net $net -type {MN} -pinPathType { {g}
{Gate2} {d} {Gate2} } -list]
set nmos_count [lindex $result 0]
if { $nmos_count == 0 }
{
return 0
}
set nmos_list [lindex $result 1]
set nmos_each [lindex $nmos_list 0]
set nmos_val [perc::property $nmos_each IL]
set result [ perc::count -net $net -type {MN} -pinAtNet {d} pinNetType { {s} {Ground} } ]
if { $result <= 1 } {
perc::report_base_result -title " Improperly
connected shutdown transistor"
return 1
}
15
set result [perc::count -net $net -type {RC} -instanceAlso -list]
set res_count [lindex $result 0]
if { $res_count == 0 } {
perc::report_base_result -title "Missing RC filter"
return 1
}
set res_list [lindex $result 1]
set RC_1 [lindex $res_list 0]
set RC_string [perc::get_instances_in_series $RC_1 $net 1 2]
set total_res_val 0
foreach RC_SUB $RC_string {
set placItr [perc::descend $RC_SUB]
set insItr [perc::get_instances $placItr]
set propItr [perc::get_properties $insItr -name R ]
set result [ perc::value $propItr ]
set total_res_val [ expr "$total_res_val + $result"]
}
set mult [ expr "$total_res_val * $nmos_val"]
set max_leakage [tvf::svrf_var leakage_value]
if { $mult > $max_leakage } {
perc::report_base_result -value "Unallowed value
for IR-drop through filter : $mult volt > max allowed drop :
$max_leakage volt "
return 1
}
return 0
}
Reported violations
16
Conclusion
 Multi-tool verification flow
 Design yield focused
 Verify designers’ intent
 Avoid circuit mis-implementation
 Automated flow to save time and effort
17