EE 330 Lab Experiment #11
MOSFET Characteristics and Applications
Joe O’Connor | Onochie Ani
Due: 5/1/2015
In this experiment, we used transistors and their applications. We studied the i-v characteristic
relationships of transistors and built circuits using them. The main purpose of this experiment is to
familiarize us with transistors and how to apply them in circuits. Transistors are vital for signal
processing and are extremely important in engineering.
Steps 1-2:
To start, we set up our circuit indicated in the lab manual. Then we measured the relationship
between iDS and vDS. We connected PS1 and PS2 to one of the NMOS transistors in CD4007. We then set
VDS to equal 5V. Next we measured iDS vs vDS by incrementing the PS2 from 0 to 2V in 100mV steps and
then 2 to 10V in 500mV steps. The values we got are below.
IDS (mA)
.0085
0.292
0.582
0.861
1.144
1.861
2.21
2.516
2.799
3.033
3.426
3.662
3.710
VDS (V)
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.5
3.0
3.5
4.0
4.5
IDS (mA)
3.921
4.101
4.221
4.362
4.481
4.52
4.61
4.74
4.91
4.99
5.003
5.022
5.043
VDS (V)
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IDS (mA)
5.103
5.111
5.139
5.146
5.152
5.160
5.172
5.189
5.201
5.221
5.236
iDS vs vDS(V)
6
5
4
iDS (mA)
VDS (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
3
2
1
0
0
2
4
6
vDS(V)
8
10
Step 3:
For step 3 we had to repeat the steps above but change vgs to 3.5V instead of 5V. We also had to
do it again with 1V. The values get got are below
vGS 3.5 V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
iDS (mA)
0.00069
1.224
0.434
0.633
0.811
1.11
1.199
1.899
1.962
2.081
2.112
2.122
2.188
2.252
2.276
2.295
2.301
2.321
vGS 3.5 V
1.8
1.9
2.0
2.5
3.0
3.5
4.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10
iDS (mA)
2.326
2.332
2.338
2.359
2.374
2.386
2.393
2.408
2.416
2.411
2.429
2.434
2.438
2.446
2.451
2.456
2.463
2.469
vGS 1 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
3
2
1
0
0
5
V_DS (V)
0.0001
0.000155
0.000164
0.000164
0.000166
0.000167
0.000169
0.000170
0.000166
0.000164
0.000175
0.000176
0.000173
0.000173
0.000171
0.000171
0.000172
0.000173
vGS 1V
1.8
1.9
2.0
2.5
3.0
3.5
4.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10
iDS (mA)
0.000173
0.000173
0.000174
0.000186
0.000189
0.000190
0.000184
0.000177
0.000181
0.000181
0.000182
0.000181
0.000179
0.000180
0.000180
0.000180
0.000180
0.000180
1V I-V graph
I_DS(mA)
I_DS(mA)
3V I-V graph
iDS (mA)
10
0.0002
0.0001
0
0
5
10
V_DS(V)
Step 4:
This step we had to first set the vDS to 5V. Then we had to experimentally determine Vt of the
NMOS by finding VGS that produced IDS less than or equal to 6uA. We did this by slowly reducing VGS from
2.5V while monitoring iDS. We got vGS to equal 1.3V, iDS to equal 0.005mA, and VT to equal 1.28V.
Steps 5-6:
For steps 5 and 6, we had to analyze the plot of data from steps 1-3. We found what the
saturated current would be when VGS equaled 5, 3.5, and 1V. We got the following chart.
vGS
iDS_sat
5V
4.95 mA
1.87 mA
0A
3.5 V
1V
iDS (mA)
iDS vs. vDS
6
5
4
3
2
1
0
vGS = 5 V
vGS = 3.5 V
vGS = 1 V
0
1
2
3
4
5
6
7
8
9
10
vDS (V)
Step 7:
For this step we had to re-plot the data from steps 1-3 with iDS as a function of vDS. We have vDS
to range from 0 to 0.6V. We also have Vgs to be fixed a 5, 3.5, and 1V. Then we need to find slope. The
slope relates to the conductance of our values. We saw that different values of Vgs cause resistance to
decrease or increase. From the lines of the graph we determined that it does go through the origin. The
MOFSET behavior is linear. For 5V our slope was 3.05, for 3.5V it was 1.6 and for 1V it was 0.
iDS vs. vDS
iDS (mA)
3
vGS = 5 V
vGS = 3.5V
2
1
vGS = 1 V
0
0
0.1
0.2
0.3
vDS (V)
0.4
0.5
0.6
Step 8:
For step 8 we had to measure RDS and vary values from 2 to 5V in 0.5V steps. We had to do this
by first building the circuit shown on figure 4. We replaced PS2 with the DMM to measure the resistance
between the drain and source when vds > Vt. Our Values are to the right. We noticed that the channel
resistance decreases as the VGS increases from 2 to 5V.
vGS (V)
RDS (kΩ)
2.0
1.049
2.2
0.891
2.4
0.754
2.6
0.660
2.8
0.596
3.0
0.686
3.2
0.539
3.4
0.464
3.6
0.411
3.8
0.377
4.0
0.348
4.2
0.366
4.4
0.336
4.6
0.289
4.8
0.277
5.0
0.263
R_DS (Kohms)
V_GS v. R_DS
1.5
1
0.5
0
1
2
3
4
5
6
V_GS (V)
Step 9:
For step 9 we had to design a resistor divider circuit using the NMOS as a variable resistor (R2) by
choosing R1 so that the R1 = 10x of the smallest channel resistance (R2-min). We got R1 to equal 2.5kohms.
We designed the circuit to replicate fig 5.
Step 10:
This step we had to actually build the circuit we designed above. We used the value in step 9 to
design a voltage divider. We had to use the DMM to monitor VZW while varying VGS between 0 and 5V
using 300mV steps. The values we got are below.
VGS (V)
VZW (V)
VGS (V)
VZW (V)
0.01
1.23
3.0
0.189
0.3
1.233
3.3
0.166
0.6
1.233
3.6
0.153
0.9
1.223
3.9
0.144
1.2
1.111
4.2
0.136
1.5
0.929
4.5
0.125
1.8
0.632
4.8
0.121
2.1
0.466
5.0
0.106
2.4
0.286
2.7
0.224
V_ZW (V)
V_ZW v. V_GS
2
1
0
0
1
2
3
4
5
V_GS(V)
Steps 11-12:
This step was simply to read pg. 86 of the lab text book.
Steps 13-14:
For these steps we had to set up a circuit that replicated the circuit shown. We connected
CD4066 using the triple output power supply for +-5V. We also had to use the single output DC supply
for VCONTROL and connect to pin 13. We then used the triple output power supply to generate the 5V at
pin 7 and 14. We then used the DMM to measure the resistance between pins 2 and 1. Our values when
we measured the resistance between pins 1 and 2 are below.
VCONTROL
R
1V
95.5 ohm
-1V
289.1 k ohm
2V
98.1 ohm
-2 V
0.3 M ohm
Steps 15-16:
For steps 15 and 16 we started out by setting up our circuit by combining figure 6a and 8a. We
then had to use two function generators. We set the first function generator to produce VIN which was a
1kHZ sine wave with +-1V and 0V offset. Then we had to use the second function generator to produce
VCONTROL which is a 10kHS square wave with +- 2V and 0V offset. Our resistor was 5.5k ohms. Our
overlapping wave forms is below. The switch state for Vout is on when VCONTROL is 2V, adversely the
switch state is off when VCONTROL is -2V.
Step 17:
This step was to simply read pages 88-89 of the lab textbook.
Steps 18-19:
The last couple steps used the same setup as step 16 but we replaced the resistor with a 0.01uF
capacitor. We set up our circuit to replicate figure 6a and 9a combined. We connected the first function
generator to pin 1 of the VD4066 and then we connected the second function generator to pin 13. We
set the first function generator to generate a 1kHz sine wave and the second function generator to
generate a 10kHz square wave. The waveform we got is below. Replacing the capacitor with the resistor
made it so when VOUT gains a ripple effect we are able to get a wave signal for Vout similar to Vin.
+