EE 435 Experiment 1
Fall, 2013
Lab 1: Function Design and Simulation
Xia, Jiwei
Li, Muzi
9/8/2013
EE 435 EXPERIMENT 1
September 8, 2013
Lab 1: Function Design and Simulation
Introduction: Our task is to perform Verilog code for a mathematical
function circuit and write a test-bench Verilog code for this circuit. We
are required to deliver Verilog code, test bench code and the function
simulation result to the Teaching assistant.
The target mathematical function is:
oRESULT= iA0*iB0+iA1*iB1+ iA0* iA1* iB0*iB1 when iSEL=0
oRESULT= iA0*iB0+iA1*iB1
when iSEL=1
The structure of the gate level circuit is:
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EE 435 EXPERIMENT 1
September 8, 2013
Code for module:
module lab1(
iCLK,
iRST_N,
iA0,
iB0,
iA1,
iB1,
iSEL,
oRESULT,
);
input iCLK;
input iRST_N;
input [7:0] iA0;
input [7:0] iB0;
input [7:0] iA1;
input [7:0] iB1;
input iSEL;
output [16:0] oRESULT;
reg
reg
reg
reg
reg
[7:0] iA00;
//Corresponding to the first level 4 registers
[7:0] iB00;
//to pass the input when positive edge of clk comes.
[7:0] iA11;
[7:0] iB11;
[16:0] oRESULT; //Corresponding to the last level registers
//to pass the output when positive edge of clk comes.
always@(posedge iCLK or negedge iRST_N)
begin
if (~iRST_N)
//iRST_N is active low: when iRST_N=0, trigger resetting.
begin
iA00 <= 8'b0;
//reset all the registers to 0.
iB00 <= 8'b0;
iA11 <= 8'b0;
iB11 <= 8'b0;
oRESULT<= 17'b0;
end
else
//When iRST_N is 1
begin
iA00<=iA0;
//pass the data to the registers
iB00<=iB0;
iA11<=iA1;
iB11<=iB1;
if (~iSEL)
//According to the value of iSEL,
//choose the value for oRESULT
oRESULT <= iA00*iB00 + iA11*iB11 + iA00*iA11*iB00*iB11;
else
oRESULT <= iA00*iB00 + iA11*iB11;
end
end
endmodule
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EE 435 EXPERIMENT 1
September 8, 2013
Code for test bench:
`timescale 1ns/1ns
module lab1_tb;
reg iCLK;
reg iRST_N;
reg [7:0] iA0;
reg [7:0] iB0;
reg [7:0] iA1;
reg [7:0] iB1;
reg iSEL;
wire [16:0] oRESULT;
initial begin
iA0<=8'b0;
iB0<=8'b0;
iA1<=8'b0;
iB1<=8'b0;
iSEL<=0;
//Give initial value to the registers
iRST_N <=1'b0;
#5 iRST_N <=1'b1;
end
//Try reset
//deactivate iRST_N
initial begin
#1500;
$finish;
end
//Total time until finished
initial iCLK = 1'b0;
always
always
always
always
always
always
#5 iCLK = ~iCLK;
#10 iA0 = iA0+1;
#20 iB0= iB0+1;
#40 iA1= iA1+1;
#80 iB1= iB1+1;
#320 iSEL=~iSEL;
lab1 lab1_0 (
.iCLK(iCLK),
.iRST_N(iRST_N),
.iA0(iA0),
.iB0(iB0),
.iA1(iA1),
.iB1(iB1),
.oRESULT(oRESULT),
.iSEL(iSEL)
);
//Make clk change every 5ns
//Make iA0 change when clk on the falling edge
//so that when data is passed to iA00(pos edge of clk)
//iA0 is stable.
//Connect the ports
endmodule
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EE 435 EXPERIMENT 1
September 8, 2013
Simulation results
Overal
Details
To verify our result
First randomly pick a point on the wave
iSEL= 0, so
oRESULT= iA0*iB0+iA1*iB1+ iA0* iA1* iB0*iB1
= 16 * 8 + 4 * 2
+ 16*8*4*2
= 1160
From the structure of the circuit, we are aware that the 5 registers pass the value at
the same time which leads to one clock cycle delay of the output results.
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EE 435 EXPERIMENT 1
September 8, 2013
Move the cursor a little bit to the right
At this time new value of iA0, iB0… come, but the positive value of the clock
hasn’t come yet. As a result, the four registers on the input side has not changed
the value. Neither does the output result.
Move the cursor a little bit more to the right
When positive edge of clock comes, the new value of iA0, iB0…are passed to the
4 registers on the input side. The original output results are passed out from the
output register.
Now “1160” comes.
As predicted, the result calculated from current iA0, iB0… should release when
next positive edge of clock comes.
oRESULT= iA0*iB0+iA1*iB1+ iA0* iA1* iB0*iB1
= 17 * 8 + 4 * 2
+ 17*8*4*2
= 1232
From the figure, it is accurately displayed.
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EE 435 EXPERIMENT 1
September 8, 2013
Conclusion: From this lab, we reviewed what we learned about Verilog from
EE330. We get our memory refreshed and get a better understanding of how digital
circuit works. When we first look at the result, we thought the result would be
corresponding to the values shown in the same cycle. Then we realize it is actually
a circuit, flip-flops can only pass the data when edge of the cycle comes. Even
more, when input and output registers are driven by the same clock, the results will
be delayed for one cycle.
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