Denni Kurniawan (0260813)
Department of Electrical Engineering and Computer Science
National Chiao Tung University

Outline
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NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813) 2

Introduction
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Introduction
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013 4

Introduction
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013 5

Solid-State Drive
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Solid-State Drive
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Solid-State Drive
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NAND Flash Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Campordo et al. 2005
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NAND Flash Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Campordo et al. 2005
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NAND Flash Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Campordo et al. 2005
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NAND Flash Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Campordo et al. 2005
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SSD Architecture
A memory controller task:
 To provide the most suitable interface and protocol towards the host and flash memories.
 To efficiently handle data, maximizing transfer speed, data integrity and information retention.
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Takeuchi, 2009
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SSD Architecture
 FTL is used to map logical blocks to their locations within physical flash memory.
 An FTL allows file systems and SSD to maintain the block interface of disks and control over how the flash is managed.
 Two types of FTL a log-based approach and mapping consecutive ranges.
 Wear leveling techniques rely on the concept of logical to physical translation.
 Bad Block Management module creates and maintains a map of bad blocks.
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Takeuchi, 2009
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NAND Flash Trend
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Wei Hwang, NCTU
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NAND Flash Trend
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Wei Hwang, NCTU
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NAND Flash Trend
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013 17

NAND Flash Trend
Denni Kurniawan (260813)
IEEE International solid-state circuit conference
NCTU IEE5011 Memory Systems 2013 18

NAND Flash Trend
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Wei Hwang, NCTU
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NAND Flash Trend
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Wei Hwang, NCTU
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Storage Class Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Takeuchi, 2008
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Storage Class Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Wei Hwang, NCTU
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Storage Class Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: IBM
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Storage Class Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Papers presented at
Symposium on VLSI Technology
IEDM (Int. Electron Devices Meeting)
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Storage Class Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Everspin technologies
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Storage Class Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Everspin technologies
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Storage Class Memory
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013
Source: Wei Hwang, NCTU
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Conclusion
• SSD based NAND flash technology successfully replace
HDD as storage device.
• SCM is a new class that reduce boundaries between storage/memory technology.
• The features of SCM technologies should be: nonvolatile, short access times (~DRAM like), low cost per bit
(more DISK like), and solid state
• The goal of SCM development is to create compact, robust storage and memory systems with greatly improved cost/performance ratios relative to other technologies.
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013 28

Conclusion
 There are many technologies that claim the best for SCM application such as PCRAM, RRAM, FeRAM, and MRAM, but all of them are still in the competition.
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013 29

References
1.
F. Masuoka et al., “New ultra high density EPROMand flash EEPROM with NAND structured cell,” in IEDM Tech. Dig., 1987, pp. 552–555.
2.
J. K. Kim et al., “A 120-mm 64-Mb NAND flash memory achieving 180 ns/byte effective program speed,” IEEE J. Solid-State
Circuits, vol.32, pp. 670–680, 1997.
3.
S. Aritome et al., “A reliable bi-polarity write/erase technology in flash EEPROMs,” in IEDM Tech. Dig., 1990, pp. 111–114.
4.
Fontana, R.E.; Decad, G.M.; Hetzler, S.R., "The impact of areal density and millions of square inches (MSI) of produced memory on petabyte shipments of TAPE, NAND flash, and HDD storage class memories," Mass Storage Systems and
Technologies (MSST), 2013 IEEE 29th Symposium on , vol., no., pp.1,8, 6-10 May 2013
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K. Takeuchi et al., “A56 nmCMOS 99mm 8 Gbit multi-level NAND flash memory with 10 Mbyte/sec program throughput,” in
IEEE ISSCC Dig., 2006, pp. 144–145.
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430–431.
7.
K. Takeuchi, “NAND successful as a media for SSD,” presented at the IEEE ISSCC, Tutorial T7, 2008.
8.
K. Takeuchi., Novel co-design of NAND flash memory and NAN flash controller circuits for sub-30 nm low-power high-speed solid-state drives (SSD), Journal of solid-state circuits, vol. 44, no. 4, 2009.
9.
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11. G. Campardo, R. Micheloni et al., 40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash memory. IEEE J Solid-State
Circuits. 35(11), 1655–1667 (Nov 2000)
12. R. Micheloni et al., A 4Gb 2b/cell NAND flash memory with embedded 5b BCH ECC for 36 MB/s system read throughput, in
IEEE International Solid-State Circuits Conference Dig.Tech. Papers, Feb 2006, pp. 142–143
Denni Kurniawan (260813) NCTU IEE5011 Memory Systems 2013 30

References
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Dordrecht. 2013.
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Dissertation, University of California, United States.
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447, 2008.
16. J.G.Yun, Y. Kim, H. Shin. "Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory." Electron Devices, IEEE Transactions on 58.4 (2011): 1006-1014.
17. B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, and A. Modelli, ‘‘Multilevel Flash Cells and Their Trade-offs,’’
International Electron Devices Meeting, IEDM Technical Digest, December 8–11, 1996, pp. 169–172.
18. K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, R. S. King, Y. Zhang, B. Kurdi, L. D. Bozano, et al., ‘‘The Micro to Nano
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11, 829–832 (2004).
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Seventh International Conference on Solid-State and Integrated Circuits Technology, October 18–24, 2004, pp. 668–672.
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