MSP430 Teaching Materials
UBI
Lecture 4
MSP430X Architecture & Assembly
Language Instructions
Texas Instruments Incorporated
University of Beira Interior (PT)
Pedro Dinis Gaspar, António Espírito Santo, Bruno Ribeiro, Humberto Santos
University of Beira Interior, Electromechanical Engineering Department
www.msp430.ubi.pt
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
Contents (1/2)
UBI
 MSP430X architecture:
 Central Processing Unit (MSP430X CPU)
 Addressing modes
 Instructions set
 Exploring the addressing modes of the MSP430X
architecture:
 Instruction format in the MSP430X CPU
 Exceptions to the representation of the extended Format II
instructions
 Extended emulated instructions
 MSP430X address instructions
 MSP430X CPU addressing modes
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
2
Contents (2/2)
UBI
 Arithmetic and logic operations
 Stack pointer management
 Routines
 Interrupts
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
3
UBI
Central Processing Unit (MSP430X CPU)
(1/9)
 Main features of the MSP430X CPU architecture:
 The MSP430X CPU extends the addressing capabilities of the
MSP430 family beyond 64 kB to 1 MB;
 To achieve this, some changes have been made to the
addressing modes and two new types of instructions have
been added;
 One instruction type allows access to the entire address
space, and the other is designed for address calculations;
 The MSP430X CPU address bus has 20 bits, although the
data bus still has 16 bits. Memory accesses to 8-bit, 16-bit
and 20-bit data are supported;
 Despite these changes, the MSP430X CPU remains
compatible with the MSP430 CPU, having a similar number
of registers.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
4
UBI
Central Processing Unit (MSP430X CPU)
(2/9)
 Organization of the MSP430X CPU:
 Although the MSP430X CPU structure is
similar to that of the MSP430 CPU, there
are some differences that will now be
highlighted;
 With the exception of the status register
SR, all MSP430X registers are 20 bits;
 The CPU can now process 20-bit or 16bit data.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
5
UBI
Central Processing Unit (MSP430X CPU)
(3/9)
 The MSP430X CPU has 16 registers, some of which have
special use:
 R0 (PC) Program Counter:
 Has the same function as the MSP430 CPU, although now it
has 20 bits.
 R1 (SP) Stack Pointer:
 Has the same function as the MSP430 CPU, although now it
has 20 bits.
 R2 (SR) Status Register:
 Has the same function as the MSP430 CPU, but it still has 16
bits.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
6
UBI
Central Processing Unit (MSP430X CPU)
(4/9)
 R2 (SR) Status Register:
 Description of the SR bits:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
7
UBI
Central Processing Unit (MSP430X CPU)
(5/9)
 R2 (SR/CG1) and R3 (CG2) Constant Generators:
 Registers R2 and R3 can be used to generate six different
constants commonly used in programming, without adding
an additional 16-bit word to the instruction;
 The constants are fixed and are selected by the (As) bits of
the instruction. (As) selects the addressing mode.
 Values of constants
generated:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
8
UBI
Central Processing Unit (MSP430X CPU)
(6/9)
 R2 (SR/CG1) and R3 (CG2) Constant Generators:
 Whenever the operand is one of the six constants, the
registers are selected automatically;
 Therefore, when used in constant mode, registers R2 and R3
cannot be used as source registers.
 R4-R15 – General-purpose registers:
 Have the same function as in the MSP430 CPU, although
they now have 20 bits;
 These registers can process 8-bit, 16-bit or 20-bit data;
 If a byte is written to one of these registers it takes bits 7:0,
the bits 19:8 are filled with zeroes. If a word is written to
one of these registers it takes bits 15:0, the bits 19:16 are
filled with zeroes.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
9
UBI
Central Processing Unit (MSP430X CPU)
(7/9)
 R4-R15 – General-purpose registers:
 Handling byte data (8 bits) using the suffix .B:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
10
UBI
Central Processing Unit (MSP430X CPU)
(8/9)
 R4-R15 – General-purpose registers:
 Handling word data (16 bits) using the suffix .W:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
11
UBI
Central Processing Unit (MSP430X CPU)
(9/9)
 R4-R15 – General-purpose registers:
 Manipulation of a 20-bit address using the suffix .A:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
12
UBI
Instruction format in the MSP430X CPU
(1/2)
 There are three possibilities to choose between the
instructions of the MSP430 CPU and MSP430X CPU:
• Use only the MSP430 CPU instructions. The following
rules must be followed, with the exception of the
instructions CALLA/RETA, BRA:
– Put all the data in memory below 64 kB and access
the data using 16-bit pointers;
– Place the routines at an address within the range
PC 32 kB;
– No 20-bits data.
• Use only the MSP430X CPU instructions. This causes a
reduction in the application execution speed and an
increase in the memory space occupied by the program;
• Use an appropriate selection of the instruction types.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
13
Instruction format in the MSP430X CPU (2/2)
UBI
 The MSP430X CPU supports all functions of the MSP430
CPU;
 It also offers a set of instructions that provide full access
to the 20-bit addressing space;
 An additional op-code word is added to some of the
instructions. Therefore all addresses, indexes and
immediate numbers have 20 bits.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
14
UBI
Extension word for register addressing
mode (1/2)
 In register mode, the
extension word of an
instruction of format type I
(two operands) or format
type II (single operand) is
coded as:
 The description of each field:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
15
UBI
Extension word for register addressing
mode (2/2)
 Unlike the MSP430, the MSP430X CPU supports the
repeated execution of the same instruction, provided
that the operands are of the register type;
 The repetition is set by placing the repeat RPT instruction
before the instruction to be executed;
 The assembler incorporates information in the extension
word in the fields # (bit 7) and in the repetition counter
(bits 3:0);
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
16
UBI
Extension word for the other addressing
modes
 In a non-register
addressing mode, the
extension word of an
instruction, whether
format I (double
operands) or format II
(single operand), is
coded as:
 The description of each
field:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
17
UBI
Extended format I -Double operandinstructions
 There are twelve extended instructions that use two
operands:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
18
Examples: Extended double operand
instructions (1/7)
UBI
 Move the contents of register R5 to register R4:
MOVX R5,R4
 Instruction code: 0x1840 – 0x4504
0
0
0
1
1
0
0
ZC
#
A/L
0
0
n-1/Rn
0
0
0
1
1
0
0
0
0
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0101
0
0
00
0100
MOVX
R5
Register
16-bit
Register
R4
 This instruction uses 2 words;
 The instruction coding specifies that the CPU must perform
the 16-bit data function MOVX, using the contents of the
source register R5 and the destination register R4.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
19
Examples: Extended double operand
instructions (2/7)
UBI
 Move the contents of the register R5 to the memory
address TONI:
MOVX R5,TONI
 Instruction code: 0x184F – 0x4580
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0000
1
0
0
1111
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0101
1
0
00
0000
MOVX
R5
Symbolic
16-bits
Register
PC
 This instruction uses 3 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
20
Examples: Extended double operand
instructions (3/7)
UBI
 Move the contents of the register R5 to the memory
address TONI (continued):
MOVX R5,TONI
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0000
1
0
0
1111
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0101
1
0
00
0000
MOVX
R5
Symbolic
16-bits
Register
PC
 The instruction coding specifies that the CPU must perform
the 16-bit data function MOVX, the source being the contents
of register R5 and the destination being the memory address
pointed to by (dst 19:16: X1 + PC);
 The bits dst 19:16 is stored in the extension word and the
value X1 is stored in the word following.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
21
Examples: Extended double operand
instructions (4/7)
UBI
 Move the contents of the memory address TONI to
register R5:
MOVX TONI,R5
 Instruction code: 0x1FC0 – 0x4015
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
1111
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
0
0
01
0101
MOVX
PC
Register
16-bit
Symbolic
R5
 This instruction uses 3 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
22
Examples: Extended double operand
instructions (5/7)
UBI
 Move the contents of the memory address TONI to
register R5 (continued):
MOVX TONI,R5
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
1111
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
0
0
01
0101
MOVX
PC
Register
16-bit
Symbolic
R5
 The coding specifies that the CPU must perform the 16-bit
data function MOVX, the source being the contents of memory
address pointed to by (src 19:16: X1 + PC) and the
destination being register R5;
 The bits dst 19:16 are stored in the extension word and the
value X1 is stored in the word following.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
23
Examples: Extended double operand
instructions (6/7)
UBI
 Move the contents of the memory address TONI to the
memory address EDEN:
MOVX TONI,EDEN
 Instruction code: 0x1FCF – 0x4090
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
1111
1
0
0
1111
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
1
0
01
0000
MOVX
PC
Symbolic
16-Bit
Symbolic
PC
 This instruction uses 4 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
24
Examples: Extended double operand
instructions (7/7)
UBI
 Move the contents of the memory address TONI to the
address memory EDEN:
MOVX TONI,EDEN
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
1111
1
0
0
1111
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
1
0
01
0000
MOVX
PC
Symbolic
16-Bit
Symbolic
PC
 The coding specifies that the CPU must perform the 16-bit
data function MOVX, the source being the contents of the
memory address pointed to by (src 19:16: X1 + PC) and
the destination being the contents of the memory address
pointed to by (dst 19:16: X2 + PC);
 The bits src 19:16 and dst 19:16 are stored in the
extension word and the words X1 and X2 are stored in the
words following.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
25
UBI
Extended format II - single operandinstructions (1/2)
 Extended instructions using format II are:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
26
Extended format II - single operandinstructions (2/2)
UBI
 The MSP430X CPU has some additional capabilities in
addition to those of the MSP430 CPU:
 The ability to push/pop several registers on/off the data
stack using only a single instruction;
 The ability to rotate the contents of a register several times
during the execution of a single instruction.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
27
Examples: Extended single operand
instructions (1/4)
UBI
 Rotate right the 20-bit contents of register R5 with the
carry flag:
RRCX.A
R5
 Instruction code: 0x1800 – 0x1045
0
0
0
1
1
0
0
ZC
#
A/L
0
0
n-1/Rn
0
0
0
1
1
0
0
0
0
0
0
0
0000
Op-code
B/W
Ad
D/S-reg
000100000
1
00
0101
RRCX
20-bit
Register
R5
 This instruction uses 2 words;
 The coding specifies that the CPU must perform the function
RRCX using the 20-bit data contents of register R5.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
28
Examples: Extended single operand
instructions (2/4)
UBI
 Rotate right the 20-bit contents of the memory address
TONI with carry flag:
RRCX.A
TONI
 Instruction code: 0x180F – 0x1050
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0000
0
0
0
1111
Op-code
B/W
Ad
D/S-reg
000100000
1
01
0000
RRCX
20-bit
Symbolic
PC
 This instruction uses 3 words;
 The coding specifies that the CPU must perform the function
RRCX using the 20-bit data contents of the memory address
pointed to by (dst 19:16: X1 + PC);
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
29
Examples: Extended single operand
instructions (3/4)
UBI
 Rotate right the 20-bit contents of the memory address
TONI with carry flag (continued):
RRCX.A
TONI
 Instruction code: 0x180F – 0x1050
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0000
0
0
0
1111
Op-code
B/W
Ad
D/S-reg
000100000
1
01
0000
RRCX
20-bit
Symbolic
PC
 The bits dst 19:16 are stored in the extension word and the
value X1 is stored in the word following;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
30
Examples: Extended single operand
instructions (4/4)
UBI
 Rotate right the 20-bit contents of the memory address
TONI with carry flag (continued):
RRCX.A
TONI
 Because the instruction operand is located in memory rather
than in a CPU register, two words are used to store the
operand. The format is shown in the figure below:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
31
Exceptions to the representation of the
extended Format II instructions (1/7)
UBI
 Store the 20-bit registers R10, R9, R8:
PUSHM.A
#3,R10
 The instructions PUSHM and POPM are coded according to the
structure given in the figure below:
 Instruction code: 0x142A
Op-code
n-1
D-reg
00010100
0010
1010
PUSHM.A
#3
R10
 This instruction uses 1 word;
 The coding specifies that the CPU must perform the function
PUSHM of the 20-bit registers R10 to R8.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
32
Exceptions to the representation of the
extended Format II instructions (2/7)
UBI
 Rotate right three times the contents of the 20-bit register
R5 with the carry flag:
RRCM.A
#3,R5
 The instructions RRCM, RRAM, RRUM and RLAM are coded
according to the structure given in the figure below:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
33
Exceptions to the representation of the
extended Format II instructions (3/7)
UBI
 Rotate right three times the content of the 20-bit register
R5 with the carry flag (continued):
RRCM.A
#3,R5
 Instruction code: 0x0845
C
n-1
Op-code
R-reg
0000
10
000100
0101
#3
RRCM
R5
 This instruction uses 1 word;
 The coding specifies that the CPU must perform the function
RRCM using the contents of the 20-bit register R5 a total of 3
times.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
34
Exceptions to the representation of the
extended Format II instructions (4/7)
UBI
 Perform a branch in the program flow:
BRA
R5
 This type of instruction can be coded in three different
formats, as shown in the figure below:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
35
Exceptions to the representation of the
extended Format II instructions (5/7)
UBI
 Perform a branch in the program flow (continued):
BRA
R5
 Instruction code: 0x05C0
C
R-reg
Op-code
0(PC)
0000
0101
1100
0000
R5
BRA
PC
 This instruction uses 1 word;
 The coding specifies that the PC must be loaded with the
value in register R5.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
36
Exceptions to the representation of the
extended Format II instructions (6/7)
UBI
 Call a routine:
CALLA
R5
 This type of instruction can be coded in three different
formats, as shown in the figure below:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
37
Exceptions to the representation of the
extended Format II instructions (7/7)
UBI
 Call a routine (continued):
CALLA
R5
 Instruction code: 0x1345
Op-code
D-reg
000100110100
0101
CALLA
R5
 This instruction uses 1 word;
 The coding specifies that the PC must be loaded with the
value in register R5;
 The execution of this instruction saves the PC on the data
stack, so the function can return at the end of execution of
the routine.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
38
Extended emulated instructions
UBI
 The constant generator provide a set of extended
emulated instructions, as shown in the following table:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
39
MSP430X address instructions
UBI
 Address instructions support 20-bit operands, but they
have restrictions on the addressing modes they can use;
 List of extended address instructions:
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
40
MSP430X CPU addressing modes
UBI
 As with the MSP430 CPU, the MSP430X CPU supports
seven addressing modes for the source operand and four
addressing modes for the destination operand;
 Both the MSP430 CPU and MSP430X CPU instructions can
be used throughout the 1 MB address space;
 In the following sections we will explore the different
addressing modes available to the MSP430X CPU.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
41
Register mode (1/3)
UBI
 This addressing mode is identical to that of the MSP430
CPU;
 There are three different types of access to the registers:
 8-bit access (Byte operation);
 16-bit access (Word operation);
 20-bit access (Address-word).
 The instruction SXT is the only exception, as the sign of
the value is extended to the other bits of the register.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
42
Register mode (2/3)
UBI
 Move the 20-bit contents of register R5 to register R4:
MOVX.A R5,R4
 Instruction code: 0x1800 – 0x4544
0
0
0
1
1
0
0
ZC
#
A/L
0
0
n-1/Rn
0
0
0
1
1
0
0
0
0
0
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0101
0
1
00
0100
MOVX
R5
Register
20-bit
Register
R4
 The instruction uses 2 words.
 The 20-bit contents (B/W = 1 and A/L = 0) of register R5
(S-reg = 0101) is transferred to register R4
(D-reg = 0100);
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
43
Register mode (3/3)
UBI
 Move the 20-bit contents of register R5 to register R4
(continued):
MOVX.A R5,R4
 After the execution of the instruction, the PC is incremented
by 4 and pointed to the next instruction;
 The addressing mode used for the source and destination
operands is specified by Ad = 0 (Register mode) and
As = 00 (Register mode).
CPU Registers
Before
R5
0x12345
Address Space
Code
After
R5
Before
0x12345
R4
0xXXXXX
R4
0x12345
PC
0x03110
PC
0x03114
>> Contents
After
0x03114
0x03112
0x03110
0x4544
0x1800
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
PC
0x03114
0x03112
0x03110
PC
0x4544
0x4504
44
Indexed mode
UBI
 Indexed mode can be used in three different situations:
 Indexed mode in the memory address space below 64 kB;
 Indexed mode in the memory address space above 64 kB;
 Indexed mode using a MSP430X CPU instruction.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
45
Indexed mode: below 64 kB (1/4)
UBI
 Indexed mode in the memory address space below 64 kB:
 If the CPU register Rn points to a memory address located
below 64 kB, the address resulting from the sum of the index
and the register Rn has the value zero in bits 19:16.
 This ensures that the address is always located in memory
below 64 kB.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
46
Indexed mode: below 64 kB (2/4)
UBI
 Move the word pointed to by (R5 – 0x30) to the word
pointed to by (R4 + 2):
MOV 0XFFD0(R5),2(R4)
 Instruction code: 0x4594
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0101
1
0
01
0100
MOV
R5
Indexed
16-bit
Indexed
R4
 This instruction uses 3 words;
 The instruction coding specifies that the word (B/W = 0)
pointed to by the sum of register R5 contents (S-reg = 0101)
and the word X1 should be moved to the memory address
pointed to by the sum of the register R4 contents
(D-reg = 0100) and the word X2;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
47
Indexed mode: below 64 kB (3/4)
UBI
 Move the word pointed to by (R5 – 0x30) to the word
pointed to by (R4 + 2) (continued):
MOV 0XFFD0(R5),2(R4)
 The words X1 and X2 are located in the memory addresses
following the instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 1 (Indexed mode) and
As = 01 (Indexed mode), because D-reg = 0100 and
S-reg = 0101 respectively;
 In this example, bits 19:16 are set to zero when the operand
addresses are calculated.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
48
Indexed mode: below 64 kB (4/4)
UBI
 Move the word pointed to by (R5 – 0x30) to the word
pointed to by (R4 + 2) (continued):
MOV 0XFFD0(R5),2(R4)
CPU Registers
Address Space
Code
Before
R5
0x00200
After
R5
Before
0x03116
0x03114
0x03112
0x03110
0x00200
R4
0x00200
R4
0x00200
PC
0x03110
PC
0x03116
After
0x0002
0xFFD0
0x4594
X2
X1
PC
0x03116
0x03114
0x03112
0x03110
0x0002
0xFFD0
0x4594
PC
X2
X1
Data
Destination Address
0x00200
0x00002
0x00202
Source Address
0x00200
0xFFFD0
0x001D0
>> Contents
(R4)
(X2)
(R5)
(X1)
0x00202
0xXXXX X2(R4)
0x00202
0x1234
X2(R4)
0x001D0
0x1234
0x001D0
0x1234
X1(R5)
X1(R5)
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
49
Indexed mode: above 64 kB (1/2)
UBI
 Indexed mode in the memory address space above 64 kB:
 If the CPU register Rn points to a memory address above 64
kB, bits 19:16 are used to calculate the operand of the
address;
 A prerequisite is that the operand must be located in the
range Rn  32KB, because the index is a signed 16-bit value;
 Outside this range, the operand address can overflow or
underflow the memory address space below or above the
64 kB.
 If the registers now point to a memory address space above
64 kB, bits 19:16 are used to determine the address in the
operands.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
50
Indexed mode: above 64 kB (2/2)
UBI
 Indexed mode in the memory address space above 64 kB
(continued):
CPU Registers
Address Space
Code
Before
R5
0x101D0
After
R5
Before
0x101D0
R4
0x00200
R4
0x00200
PC
0x03110
PC
0x03116
0x03116
0x03114
0x03112
0x03110
0x0002
0xFFD0
0x4594
After
X2
X1
PC
0x03116
0x03114
0x03112
0x03110
0x0002
0xFFD0
0x4594
PC
X2
X1
Data
Destination Address
0x00200
0x00002
0x00202
Source Address
0x101D0
0xFFFD0
0x101A0
>> Contents
(R4)
(X2)
(R5)
(X1)
0x00202
0xXXXX
X2(R4)
0x00202
0x1234 X2(R4)
0x101A0
0x1234
X1(R5)
0x101A0
0x1234
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
X1(R5)
51
Indexed mode: MSP430X CPU (1/4)
UBI
 Indexed mode using a MSP430X CPU instruction:
 When a MSP430X CPU instruction is used in indexed mode,
the operand can reside anywhere in the range of addresses
Rn  19 bits;
 The operand address is calculated from the sum of the 20-bit
contents of the register Rn and the signed 20-bit index.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
52
Indexed mode: MSP430X (2/4)
UBI
 Move the word pointed to by (R5 – 0x30) to the word
pointed to by (R4 + 2):
MOVX 0xFFFD0(R5),2(R4)
 Instruction code: 0x1FC0 – 0x4594
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
1111
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
1000
0101
1
0
01
0100
MOVX
R5
Indexed
16-bit
Indexed
R4
 This instruction uses 4 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
53
Indexed mode: MSP430X CPU (3/4)
UBI
 Move the word pointed to by (R5 – 0x30) to the word
pointed to by (R4 + 2) (continued):
MOVX 0xFFFD0(R5),2(R4)
 The instruction coding specifies that the word (B/W = 0 and
A/L = 1) pointed to by the sum of register R5 contents
(S-reg = 0101) and the word X1 should be moved to the
memory address pointed to by the sum of the register R4
contents (D-reg = 0100) and the word X2;
 The four MSB indices are placed in the extension word of the
instruction and the other 16 bits are placed in the words
following the instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 1 (Indexed mode) and
As = 01 (Indexed mode), because D-reg = 0100 and
S-reg = 0101 respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
54
Indexed mode: MSP430X CPU (4/4)
UBI
 Move the word pointed to by (R5 – 0x30) to the word
pointed to by (R4 + 2) (continued):
MOVX 0xFFFD0(R5),2(R4)
CPU Registers
Address Space
Code
Before
After
R5
0x101D0
R5
0x101D0
R4
0x00200
R4
0x00200
PC
0x03110
PC
0x03118
Before
0x03118
0x03116 0x0002
0x03114 0xFFD0
0x03112 0x4594
0x03110 0x1FC0
X2
X1
PC
After
0x03118
0x03116 0x0002
0x03114 0xDDF0
0x03112 0x4594
0x03110 0x1FC0
PC
X2
X1
Data
Destination Address
0x00200
0x00002
0x00202
Source Address
0x101D0
0xFFFD0
0x101A0
>> Contents
(R4)
(X2)
(R5)
(X1)
0x00202
0xXXXX
X2(R4)
0x00202
0x1234 X2(R4)
0x101A0
0x1234
X1(R5)
0x101A0
0x1234
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
X1(R5)
55
Symbolic mode
UBI
 The symbolic addressing mode uses the register PC to
determine the location of the operand based on an index;
 Similar to the previous addressing mode, there are three
different ways to use symbolic mode with the MSP30X
CPU.
 Symbolic mode in the memory address space below 64 kB;
 Symbolic mode in the memory address space above 64 kB;
 Symbolic mode using a MSP430X CPU instruction.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
56
Symbolic mode: below 64 kB (1/3)
UBI
 As in the indexed addressing mode, if the PC register
points to a memory address below 64 kB, the bits 19:16
of the address calculated from the sum of the PC register
and the signed 16-bit index are set to zero.
 Move the contents of the address EDEN located at
0x00200 to the address TONI located at 0x00202:
MOV EDEN,TONI
 Instruction code: 0x4090
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
1
0
01
0000
MOV
PC
Symbolic
16-bit
Symbolic
PC
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
57
Symbolic mode: below 64 kB (2/3)
UBI
 Move the contents of the address EDEN located at
0x00200 to the address TONI located at 0x00202 (cont.):
MOV EDEN,TONI
 This instruction uses 3 words;
 The instruction decoding specifies that the word (B/W = 0)
pointed to by the sum of the register PC contents
(S-reg = 0000) and the word X1 should be moved to the
memory address pointed to by the sum of the register PC
contents (D-reg = 0000) and the word X2;
 The words X1 and X2 are stored in the memory addresses
following the instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 1 (Symbolic mode)
and As = 01 (Symbolic mode), because D-reg = 0000 and
S-reg = 0000, respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
58
Symbolic mode: below 64 kB (3/3)
UBI
 Move the contents of address the EDEN located at
0x00200 to the address TONI located at 0x00202 (cont.):
MOV EDEN,TONI
CPU Registers
Address Space
Code
Before
PC
0x03110
After
PC
Before
0x03116
0x03114
0x03112
0x03110
0x03116
After
PC
X2
X1
0xD0EE
0xD0EE
0x4090
X2
X1
PC
0x03116
0x03114
0x03112
0x03110
0xD0EE
0xD0EE
0x4090
0x00202
0xXXXX
TONI
0x00202
0x1234
TONI
0x00200
0x1234
EDEN
0x00200
0x1234
EDEN
Data
Destination Address
0x03114
0xD0EE
0x0202
Source Address
0x03112
0xD0EE
0x0200
>> Contents
(PC)
(X2)
(PC)
(X1)
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
59
Symbolic mode: above 64 kB (1/4)
UBI
 If the PC register points to a memory address above 64
kB, bits 19:16 of the PC are used to calculate the operand
address;
 The operand must be located in the memory range
PC  32 kB, because the index is a signed 16-bit value;
 If outside this range, there may be an overflow or
underflow in the address space corresponding to memory
below 64 kB.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
60
Symbolic mode: above 64 kB (2/4)
UBI
 Move the contents of the address EDEN located at
0x10200 to register R5:
MOV EDEN,R5
 Instruction code: 0x4015
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
0
0
01
0101
MOV
PC
Register
16-bit
Symbolic
R5
 This instruction uses 2 words;
 The instruction coding specifies that the word (B/W = 0)
pointed to by the sum of the register PC contents
(S-reg = 0000) and the word X1 should be moved to the
register R5 (D-reg = 0101);
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
61
Symbolic mode: above 64 kB (3/4)
UBI
 Move the contents of the address EDEN located at
0x10200 to register R5 (continued):
MOV EDEN,R5
 The word X1 is in the memory address following the
instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 0 (Register mode) and
As = 01 (Symbolic mode), because D-reg = 0101 and
S-reg = 0000, respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
62
Symbolic mode: above 64 kB (4/4)
UBI
 Move the contents of the address EDEN located at
0x10200 to register R5 (continued):
MOV EDEN,R5
Address Space
CPU Registers
Code
After
Before
R5
PC
0xXXXXX
0x10018
R5
PC
After
Before
0x01234
0x1001C
0x1001A
0x10018
0x1001C
0x01E6
0x4015
X1
PC
0x1001C
0x1001A
0x10018
0x01E6
0x4015
0x1234
EDEN
0x10200
0x1234
PC
X1
Data
Destination Address
Source Address
0x1001A
0x001E6
0x10200
>> Contents
(PC)
(X1)
0x10200
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
EDEN
63
Symbolic mode: MSP430X CPU (1/4)
UBI
 When a MSP430X CPU instruction is used in symbolic
mode, the operand can be located anywhere in the range
of the addresses PC  19 bits;
 The operand address is calculated from the sum of the
20-bit contents of the PC register and the signed 20-bit
index.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
64
Symbolic mode: MSP430X CPU (2/4)
UBI
 Move the contents of the address EDEN located at
0x00200 to register R5:
MOVX EDEN,R5
 Instruction code: 0x1FC0 – 0x4015
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
1111
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
0
0
01
0101
MOVX
PC
Register
16-bit
Symbolic
R5
 This instruction uses 3 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
65
Symbolic mode: MSP430X CPU (3/4)
UBI
 Move the contents of the address EDEN located at
0x00200 to register R5 (continued):
MOVX EDEN,R5
 The instruction coding specifies that the CPU must perform
the function MOVX of the 16-bit data (B/W = 0 and A/L = 1),
from the memory address contents pointed to by
(src 19:16:X1 + PC) to register R5;
 The bits (src 19:16) are stored in the extension word and
the word X1 is stored in the word following the instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 0 (Register mode) and
As = 01 (Symbolic mode), because D-reg = 0000 and
S-reg = 0101, respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
66
Symbolic mode: MSP430X CPU (4/4)
UBI
 Move the contents of the address EDEN located at
0x00200 to register R5 (continued):
MOVX EDEN,R5
CPU Registers
Address Space
Code
Before
After
R5
0xXXXXX
R5
0x01234
PC
0x03110
PC
0x03116
Before
0x03116
0x03114 0xD0EC
0x03112 0x4015
0x03110 0x1FC0
After
PC
0x03116
0x03114
0x03112
0x03110
0xD0EC
0x4015
0x1FC0
EDEN
0x00200
0x1234
X1
PC
X1
Data
Destination Address
Source Address
0x03114
0xFD0EC
0x00200
>> Contents
(PC)
(X1)
0x00200
0x1234
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
EDEN
67
Absolute mode
UBI
 Absolute mode uses the word contents following the
instruction as the operand address;
 There are two different ways to use absolute mode with
the MSP30X CPU.
 Absolute mode in the memory address space below 64 kB:
• In memory space below 64 kB, this instruction operates
in the same way as the MSP430 CPU.
 Absolute mode using a MSP430X CPU instruction.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
68
Absolute mode: MSP430X CPU (1/4)
UBI
 If a MSP430X CPU instruction is used with an address in
absolute mode, the 20-bit absolute address of the
operand is used with an index of zero (generated by the
constant generators) to point to the operand;
 The four MSBs of the indices are placed in the extension
word of the instruction and the other 16 bits are placed
in the words following the instruction.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
69
Absolute mode: MSP430X CPU (2/4)
UBI
 Move the contents of the address EDEN located at
0x00200 to the address TONI located at 0x00202:
MOVX
&EDEN,&TONI
 Instruction code: 0x1840 – 0x4292
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0000
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0010
1
0
01
0010
MOVX
SR/CG1
Absolute
16-bit
Absolute
SR/CG1
 This instruction uses 4 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
70
Absolute mode MSP430X CPU (3/4)
UBI
 Move the contents of the address EDEN located at
0x00200 to the address TONI located at 0x00202 (cont.):
MOVX
&EDEN,&TONI
 The instruction coding specifies that the CPU must perform
the function MOVX of 16-bit data (B/W = 0 and A/L = 1) from
the memory address contents pointed to by (src 19:16:X1)
to the memory address contents pointed to by
(dst 19:16:X2);
 The bits src 19:16 and dst 19:16 are stored in the
extension word;
 The words X1 and X2 are stored following the instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 1 (Absolute mode)
and As = 01 (Absolute mode), because D-reg = 0010 and
S-reg = 0010, respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
71
Absolute mode: MSP430X CPU (4/4)
UBI
 Move the contents of the address EDEN located at
0x00200 to the address TONI located at 0x00202 (cont.):
MOVX
&EDEN,&TONI
CPU Registers
Address Space
Code
Before
PC
0x03110
After
PC
0x03118
0x03118
0x03116
0x03114
0x03112
0x03110
Before
After
PC
X2
X1
0x0202
0x0200
0x4292
0x1840
PC
0x03118
0x03116
0x03114
0x03112
0x03110
0x00202
0xXXXX
TONI
0x00202
0x1234
TONI
0x00200
0x1234
EDEN
0x00200
0x1234
EDEN
X2
X1
0x0202
0x0200
0x4292
0x1840
Data
Destination Address
Source Address
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
72
Indirect register mode (1/3)
UBI
 Indirect addressing mode uses the contents of register
Rn to point to the 20-bit operand;
 It can only be used to point to the source operand.
 Move the operand pointed to by the contents of register
R5 to the memory address TONI located at 0x00202:
MOVX
@R5,&TONI
 Instruction code: 0x1840 – 0x45A2
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0000
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0101
1
0
10
0010
MOVX
R5
Absolute
16-bit
Indirect
SR/CG1
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
73
Indirect register mode (2/3)
UBI
 Move the operand pointed to by the contents of register
R5 to the memory address TONI located at 0x00202:
MOVX
@R5,&TONI
 This instruction uses 3 words;
 The instruction coding specifies that the CPU must perform
the function MOVX of 16-bit data (B/W = 0 and A/L = 1),
from the memory address contents pointed to by the register
R5 to the memory address contents pointed to by
(dst 19:16:X1);
 The bits dst 19:16 are stored in the extension word;
 The words X1 is stored following the instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 1 (Absolute mode)
and As = 10 (Indirect mode), because D-reg = 0010 and
S-reg = 0101, respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
74
Indirect register mode (3/3)
UBI
 Move the operand pointed to by the contents of register
R5 to the memory address TONI located at 0x00202:
MOVX
@R5,&TONI
CPU Registers
Address Space
Code
Before
R5
PC
0x00200
0x03110
After
R5
PC
Before
0x00200
0x03116
0x03116
0x03114
0x03112
0x03110
After
PC
X1
0x0202
0x45A2
0x1840
PC
0x03116
0x03114
0x03112
0x03110
0x00202
0xXXXX
TONI
0x00202
0x1234
TONI
0x00200
0x1234
EDEN
@R5
0x00200
0x1234
EDEN
@R5
X1
0x0202
0x45A2
0x1840
Data
Destination Address
Source Address
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
75
Indirect auto-increment mode (1/4)
UBI
 This addressing mode uses the contents of register Rn to
point to the 20-bit source operand;
 The register Rn is automatically incremented by 1 for a
byte operand, by 2 for a word operand and by 4 for an
address operand.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
76
Indirect auto-increment mode (2/4)
UBI
 Move the word pointed to by register R5 to the memory
address TONI located at 0x00202:
MOVX
@R5+,&TONI
 Instruction code: 0x1840 – 0x45B2
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0000
1
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0101
1
0
11
0010
MOVX
R5
Absolute
16-bit
Ind. aut. inc.
SR/CG1
 This instruction uses 3 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
77
Indirect auto-increment mode (3/4)
UBI
 Move the word pointed to by register R5 to the memory
address TONI located at 0x00202 (continued):
MOVX
@R5+,&TONI
 The instruction coding specifies that the CPU must perform
the function MOVX of the 16-bit data (B/W = 0 and A/L = 1),
from the memory address contents pointed to by the register
R5 to the memory address contents pointed to by
(dst 19:16:X1);
 The bits dst 19:16 are stored in the extension word;
 The word X1 is stored following the instruction;
 The addressing modes used for the source and destination
operands are specified by the bits Ad = 1 (Absolute mode)
and As = 11 (Indirect auto-increment mode), because
D-reg = 0010 and S-reg = 0101, respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
78
Indirect auto-increment mode (4/4)
UBI
 Move the word pointed to by register R5 to the memory
address TONI located at 0x00202 (continued):
MOVX
@R5+,&TONI
CPU Registers
Address Space
Code
Before
R5
PC
0x00200
0x03110
After
R5
PC
Before
0x00202
0x03116
0x03116
0x03114
0x03112
0x03110
After
PC
X1
0x0202
0x45B2
0x1840
PC
0x03116
0x03114
0x03112
0x03110
0x00202
0xXXXX
TONI
0x00202
0x1234
TONI
0x00200
0x1234
@R5
EDEN
0x00200
0x1234
EDEN
@R5
X1
0x0202
0x45B2
0x1840
Data
Destination Address
Source Address
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
79
Immediate mode
UBI
 The immediate addressing mode allows constants to be
placed after the instruction and use them as source
operands;
 There are two ways to use immediate mode:
 A 8-bit or 16-bit constant with a MSP430 CPU instruction:
• The operation in this situation is similar to that of the
MSP430 CPU.
 A 20-bit constant with a MSP430X CPU instruction:
• If a MSP430X CPU instruction is used in immediate
addressing mode, the constant has a 20-bit value;
• The bits 19:16 are stored in the extension word and the
remaining bits are stored following the instruction.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
80
Immediate mode: MSP430X CPU (1/3)
UBI
 Move the constant #0x12345 to register R5:
MOVX.A #0x12345,R5
 Instruction code: 0x1880 – 0x4075
0
0
0
1
1
src 19:16
A/L
0
0
dst 19:16
0
0
0
1
1
0001
0
0
0
0000
Op-code
S-reg
Ad
B/W
As
D-reg
0100
0000
0
1
11
0101
MOVX
PC
Register
20-bit
Immediate
R5
 This instruction uses 3 words;
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
81
Immediate mode: MSP430X CPU (2/3)
UBI
 Move the constant #0x12345 to register R5 (continued):
MOV.A #0x12345,R5
 The instruction coding specifies that the CPU must perform
the function MOVX using 20-bit data (B/W = 1 and A/L = 0),
from the location src 19:16:X1 to register R5;
 The bits src 19:16 are stored in the extension word;
 The word X1 is stored following the instruction;
 The addressing mode used for the source and destination
operands is specified by the bits Ad = 0 (Register mode) and
As = 11 (Immediate mode), because D-reg = 0101 and
S-reg = 0000, respectively.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
82
Immediate mode: MSP430X CPU (3/3)
UBI
 Move the constant #0x12345 to register R5 (continued):
MOV #0x12345,R5
CPU Registers
Address Space
Code
Before
R5
PC
0xXXXXX
0x03110
>> Contents
After
R5
PC
0x12345
0x03116
Before
0x03116
0x03114
0x03112
0x03110
0x2345
0x4075
0x1880
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
After
X1
PC
0x03116
0x03114
0x03112
0x03110
0x2345
0x4075
0x1880
PC
X1
83
Arithmetic and logic operations (1/9)
UBI
 Special operations with MSP430X CPU - Repetition of an
instruction:
 An MP430X CPU instruction, provided that it is used in
Register addressing mode, can be repeated a preset number
of times, up to a maximum of 15 times;
 It uses the instruction:
RPT
#n
; repeat n times
RPT
Rn
; repeat Rn.3:0 times
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
84
Arithmetic and logic operations (2/9)
UBI
 Special operations with MSP430X CPU - Repetition of an
instruction (continued):
 In the following example, the instructions sequence starts by
loading the value 0x05AD into register R5;
 The CPU is informed that it must repeat the arithmetic shift
left instruction 3 times;
 The resulting value in register R5 is the original value
multiplied by 8.
MOV #0x05AD,R5
RPT #3
RLAX R5
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
85
Arithmetic and logic operations (3/9)
UBI
 Special operations with MSP430X CPU - Arithmetic
successive shifts and carry flag (C) shifts:
 The MSP430X CPU has an instruction set that allows a number
of arithmetic shifts or shifts with carry to be carried out;
 Up to a maximum of 4 shifts can be performed on a 16-bit or
20-bit value;
 To perform #n shifts right of a register with the carry flag, the
following instruction is used:
RRCM
#n,Rdst or RRCM.W #n,Rdst
RRCM.A #n,Rdst
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
86
Arithmetic and logic operations (4/9)
UBI
 Special operations with MSP430X CPU - Arithmetic
successive shifts and carry flag (C) shifts (continued):
RRCM
RRCM.A
#n,Rdst or RRCM.W #n,Rdst
#n,Rdst
 If this is a 16-bit operation, then bits 19:16 of the register are
reset to zero;
 The Carry (C) flag content is copied to the MSB, while the LSB
is copied into the carry flag.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
87
Arithmetic and logic operations (5/9)
UBI
 Special operations with MSP430X CPU - Arithmetic
successive shifts and carry flag (C) shifts (continued):
 To perform an unsigned #n shifts right of a register:
RRUM
#n,Rdst or RRUM.W #n,Rdst
RRUM.A #n,Rdst
 If this is a 16-bit operation, then bits 19:16 of the register are
reset to zero;
 The MSB of the register is cleared to zero and the LSB is
copied to the carry (C) flag.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
88
Arithmetic and logic operations (6/9)
UBI
 Special operations with MSP430X CPU - Arithmetic
successive shifts and carry flag (C) shifts (continued):
 To perform a #n arithmetic shift right of a register:
RRAM
#n,Rdst or RRAM.W #n,Rdst
RRAM.A #n,Rdst
 If this is a 16-bit operation, then bits 19:16 of the register are
cleared to zero;
 The operation allows the division of the register contents by 2,
4, 8 or 16, depending on the parameter #n;
 During the arithmetic shift right of the register contents, the
MSB is maintained, while the LSB is copied to the carry flag.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
89
Arithmetic and logic operations (7/9)
UBI
 Special operations with MSP430X CPU - Arithmetic
successive shifts and carry flag (C) shifts (continued):
 To perform a #n arithmetic shift left of a register:
RLAM
#n,Rdst or RLAM.W #n,Rdst
RLAM.A #n,Rdst
 If this is a 16-bit operation, then bits 19:16 of the register are
reset to zero;
 The operation allows multiplication of the register contents by
2, 4, 8 or 16, depending on the parameter #n;
 The MSB is copied into the carry flag, while the LSB is cleared
to zero.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
90
Arithmetic and logic operations (8/9)
UBI
 Special operations with MSP430X CPU - Arithmetic
successive shifts and carry flag (C) shifts (continued):
 All the previous rotate operations modify the CPU status flags;
 In the following example, the value 0x1234 is multiplied by
1.25:
>> Contents
MOV
MOV
#0x1234,R4
R4,R5
;load 0x1234 in R4
;store R4 in R5
RRAM
ADD
#2,R4
R4,R5
; R4 = 0.25*R4
; R5 = (1.00+0.25)*R4
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
91
Arithmetic and logic operations (9/9)
UBI
 Special operations with MSP430X CPU - 20-bit addressing
instructions:
 The addressing instructions can use the 20-bit addresses.
There is the limitation that with the exception of the
instruction MOVA, only Register and Immediate addressing
modes can be used;
 A 20-bit address can be manipulated using the following
operations: addition (ADDA), subtraction (SUBA), doubleincrement (INCDA) and double-decrement (DECDA);
 The contents of a register can be cleared by the instruction
(CLRA);
 A 20-bit operand can be moved using the instruction (MOVA);
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
92
Stack pointer management (1/6)
UBI
 MSP430X CPU stack pointer:
 Stack access functions:
 In addition to 8-bit or 16-bit values, the MSP430X CPU
provides instructions with the ability to handle 20-bit data in
memory;
 This usually requires two instruction words to carry out a
stack operation;
 To place a 20-bit value on the stack, use the instruction:
PUSHX.A
source
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
93
Stack pointer management (2/6)
UBI
 Stack access functions (continued):
 The register SP is decremented by 4 and the source address
operand is placed on the stack;
 The following figure shows the use of this instruction:
CPU Registers
Address Space
Data
Before
After
SP
0x0020A
SP
0x00206
R4
0x12345
R4
0x12345
Before
0x0020A
0x00209
0x00208
0x00207
0x00206
0x00205
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
After
SP
0x0020A
0x00209
0x00208
0x00207
0x00206
0x00205
0xXX
0xXX
0x01
0x23
0x45
0xXX
SP
 The code that performs this task is:
PUSHX.A
R4
; place the 20-bit address in R4
; on the stack
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
94
Stack pointer management (3/6)
UBI
 Stack access functions (continued):
 The MSP430X CPU has the following instruction available for
removing a 20-bit data value from the stack:
POPX.A
destination
 This instruction moves the 20-bit value pointed to by register
SP from the stack to the destination register;
 Then, the register SP is incremented by 4.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
95
Stack pointer management (4/6)
UBI
 Stack access functions (continued):
 The following figure shows the use of this instruction:
CPU Registers
Address Space
Data
Before
After
SP
0x0020A
SP
0x00206
R4
0xXXXXX
R4
0x12345
Before
0x0020A
0x00209
0x00208
0x00207
0x00206
0x00205
0xXX
0xXX
0x01
0x23
0x45
0xXX
After
SP
0x0020A
0x00209
0x00208
0x00207
0x00206
0x00205
0xXX
0xXX
0x01
0x23
0x45
0xXX
SP
 The code that performs this task is:
POPX.A
R4 ; extract the 20-bits address from
; to the register R4
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
96
Stack pointer management (5/6)
UBI
 Data access on stack with the SP in indexed mode:
MOVX.A -6(SP),R6
; address stack access
 The stack structure is shown in the following figure:
CPU Registers
Address Space
Data
Before
After
SP
0x0020A
SP
0x0020A
R4
0xXXXXX
R4
0x0000B
R5
0xXXXXX
R5
0x00A09
R6
0xXXXXX
R6
0x70605
>> Contents
Before
0x0020A
0x00209
0x00208
0x00207
0x00206
0x00205
0x00204
0x00203
0x00202
0x00201
0x00200
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
After
SP
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
0x0020A
0x00209
0x00208
0x00207
0x00206
0x00205
0x00204
0x00203
0x00202
0x00201
0x00200
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
SP
97
Stack pointer management (6/6)
UBI
 Data access on stack with the SP in indexed mode (cont.):
 The code moves the contents of the address SP - 6 =
0x00204 to register R6;
 The entire procedure is performed without modifying the
register SP value.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
98
Routines
UBI
 Invoking a routine:
 The MSP430X CPU also has the instruction:
CALLA
destination
 This instruction decrements the register SP by four to store
the return address;
 The register PC is then loaded with the routine address and
the routine executed;
 The return is performed by the instruction RETA.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
99
Interrupts
UBI
 Stack management during an interrupt:
 Interrupt processing for the MSP430X CPU:
 When the instruction RETI is executed, the PC and SR
registers are restored, enabling the return to the program
execution point before the interrupt occurred.
>> Contents
Copyright 2009 Texas Instruments
All Rights Reserved
www.msp430.ubi.pt
100