Department of Computer Science
x86
RISC
CISC
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Department of Computer Science
Power Struggles: Revisiting the RISC vs. CISC
Debate on Contemporary ARM and x86
Architectures
Emily Blem, Jaikrishnan Menon,
and Karthikeyan Sankaralingam
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Department of Computer Science
x86
x86
x86
What role if any does RISC vs. CISC play in
this power struggle?
RISC
RISC
& CISC
RISCCISC
& CISC
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Department of Computer Science
ISA being RISC or CISC does not matter for
modern microprocessors
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Overview


Methods
11 Key Findings
6 on performance
 3 on power
 2 on power/performance tradeoffs


Conclusion
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Department of Computer Science
Overview


Methods
11 Key Findings
6 on performance
 3 on power
 2 on power/performance tradeoffs


Conclusion
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Platforms
BeagleBoard
ARM Cortex A8
PandaBoard
ARM Cortex A9
Linux 2.6
Intel Atom
N450
GCC
Intel Sandy Bridge
Core i7
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Workloads
Mobile
CoreMark
WebKit
Desktop
Server
SPEC CPU2006
Lighttpd
CLucene
Database kernels
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/ 37
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Measurements

Performance measurement on real hardware

Extensive use of performance counters


Cycles, instructions, cache misses, branch misses…
Power measurements using Wattsup meters
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Overview


Methods
11 Key Findings
6 on performance
 3 on power
 2 on power/performance tradeoffs


Conclusion
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But first…
What is performance?
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𝑇 = 𝑁 × 𝐶𝑃𝐼 ×
𝑓
“Iron Law of Performance” – Clark
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Performance
30
(130)
(72)
(24)
(344)
Normalized Time
25
20
A8
Atom
15
A9
10
i7
5
0
Mobile
SPEC - INT
SPEC - FP
Server
Key Finding 1
Large performance differences due to varying clock
frequencies and core characteristics
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Cycle counts
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Normalized Cycles
5
4
A8
Atom
3
A9
2
i7
1
0
Mobile
SPEC - INT
SPEC - FP
Server
Key Finding 2
Cycle count differences are less than 2.5X
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Instruction counts
Normalized Macro-ops
Macro-op counts are nearly same across
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ARM and x86
1.5
ARM
1
x86
0.5
0
Mobile
SPEC - INT
SPEC - FP
Server
Key Finding 3
CPI is less for x86 implementations
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Instruction Mix
Key Finding 4
ISA effects are indistinguishable
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Key Findings
1. Large performance gaps across cores
2. After accounting for clock frequency,
performance gaps within 2.5X
3. CPI is less for x86 implementations
4. ISA effects are indistinguishable
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Why are performance gaps present?
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Normalized Cycle Count
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Instruction Count
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Cache Related
7
Branch Related
6
Issue Width Related
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4
3
2
1
0
Benchmarks
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Case study: omnetpp
Cycle Count (Billions)
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Insts
4
Branch
Branch
Misses
Misses
3
I-Cache
Microarchitecture
Key
ISAFinding
Effect: Effect
5
1:
2:
3:
Issue
2
A9
A9experiences
Performance
experiences
A9’s
ARM
issue
has
15x
gaps
29x
width
4%
more
more
due
more
isinstruction
to
branch
half
instructions
microarchitecture
thatmispredictions
of
cache
i7’s misses
Width
1
0
i7
A9
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Key Findings
4.
Large performance gaps across cores
After accounting for clock frequency, performance gaps within 2.5X
CPI is less for x86 implementations
ISA effects are indistinguishable
5.
Performance gaps due to microarchitecture
6.
RISC or CISC choice does not play a role in
performance-driving µarch decisions
1.
2.
3.

Details in paper
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Power and Energy
1.
2.
3.
4.
5.
6.
Large performance gaps across cores
After accounting for clock frequency, performance gaps within 2.5X
CPI is less for x86 implementations
ISA effects are indistinguishable
Performance gaps due to microarchitecture
RISC or CISC choice does not play a role in performance-driving µarch decisions
7. x86 implementations are higher power – dictated
by performance targets
8. Power consumption is tied to microarchitectural
design decisions
9. Energy consumption also tied to microarchitectural
design decisions
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Power-Performance Tradeoffs
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Power (W)
35
30
25
i7
20
15 Cortex A8
Cortex A9
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Atom
5
0
0
1
2
3
4
5
6
7
8
Performance (MIPS)
Key Finding 10
Regardless of ISA, processors follow cubic
power/performance trends
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Energy-Delay analysis
Considering ED, A15 is 46% lower
than any other design we considered.
Considering
ED,2,i7i7isisbest
more than 2X
Considering
ED>1.4
better than next best design
Key Finding 11
Microarchitecture and design choices are key –
not the ISA
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Conclusion
ISA being RISC or CISC does not matter for
power and performance of modern
processors.
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What is the ISA’s role?

Supporting specialization
AVX crypto, Virtualization extensions
 Jazelle DBX, ARM Trustzone…


Exposing more workload-specific semantic
information to the substrate
Transactional Memory support
 Reliability-oriented extensions
 Many more…

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Questions?
Additional resources
(detailed report and raw data spreadsheet)
available at http://research.cs.wisc.edu/vertical/isa-power-struggles
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