Adaptive Mirror
Control System
Final Presentation
Performed by: Boris Goychman & Eyal Tsin
Instructor: Tsachi Martsiano
Annual project – Part B, Winter 2013
Abstract
Joint project with the physics faculty, the objective of
which is to build a system that interfaces with a PC on the
one end and controls an adaptive mirror that is connected
to it on the other end.
An adaptive Mirror –
contains 59 capacitors
to control the convexity in
order to correct distortions
of light.
Now Used for eye retina
distortion corrections.
Specifications
Data transfer
rates
Supply
voltage
Power
consumption
Interfaces
Test
requirements
DLP-USB
D2A
FPGA
Sample & Hold
1Mbps
460ns per
channel
50Mhz
4.15us per
channel
3.3V
5V
3.3V
Up to 300V
125uW
3mW
217mW
240mW
PC
FPGA
Sample & Hold
FPGA
USB
D/A
D/A
Adaptive Mirror
Emulation
Simulation –
ModelSim
Read from dat file
(signal tap)
Scope
Write to FPGA FIFO
Emulation for
each external
component
Scope
DVM
System Block Diagram
Analog Board
DE2 - FGPA
D2A
ALTERA
CHIP
HV
S&H
HV
S&H
DLP - USB
PC
DLP
CHIP
GUI
System timings
Timing Requirements of the mirror(as given by the physics
department) : 2ms  T  20ms
18ms margin
2.1ms
0ms
20ms
From PC to DLP-USB :
From FPGA to D2A :
59  8  2  944bits
t PC 2 DLP
59 channels (8 bit each)
944

 1.888mSec
0.5M
t FPGA 2 DAC  59  460n sec  27.14  sec
From DLP-USB to FPGA's internal FIFO :
From D2A TO Sample and Hold :
944bits (8 bit parallel transfer)
t FPGA 2 HV 
t DLP 2 FPGA  118  200ns  23.6  Sec
Write Cycle
Tone update
cycle
30
  75n  4   75n  
writing to both HVs at the same time
 160.2  sec
 1888  23.6   27.14   160.2   2.1ms
2ms  2.1ms  20ms
Ext_START_KEY0
Ext_SD_KEY1
Ext_RESET_KEY2
FPGA Block Diagram
START
CLR _ DE 2 _ DA
CS
WR
DB[7..0]
A0, A1
D2A
D2A
Controller
GAIN
DATA _ DE 2 _ DA[7..0]
RESET
GAIN _ DE 2 _ DA
RD
ADDRESS _ DE 2 _ DA[1..0]
RXF
RESET
FINISH
LDAC
CLR
DLP_
Controller
DLP245USB
OE
RESET
PD _ NOT
DATAOUT
START _ POWER _ UP
VNN _ SWITCH
D_inout[7..0]
START _ POWER _ DOWN
RELAY-AQY274
S&HHV257
B _ OUT [4..0]
S&HHV257
MUX-ADG784
RESET
A _ OUT [4..0]
EN _ HV
D[7..0]
START _ SAMPLING
RELAY _ 300
wrreq
VDD _ SWITCH
full
SWITCHADG202AKN
MANAGER
HV257
Controller
A _ IN [4..0]
sclr
B _ IN [4..0]
rdreq
FINISH _ SU
EN _ MUX
FINISH _ SD
IN _ MUX
FINISH _ SAMPLE
Q[7…0]
empty
(SC)FIFO
System Testing
300
250
200
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
50
100
150
200
250
300
Digital Input
150
HV‫מוצא צפוי ב‬
Expected Voltage from D2A [V]
HV-‫מוצא ה‬
100
Analog Voltage Output
Analog High-Voltage Output
Actual voltage from D2A with [V]
Analog Voltage Output
High Voltage Output - Expected and
Actual Output Voltage
50
0
0
1
2
3
4
Analog Low-Voltage Input
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
50
100
150
Digital Input
200
250
300