High Performance Analog
Solutions for lower mass satellite
modules
Paul McCormack
AMICSA 2008
September 1st
Company Information
• National Semiconductor creates energy-efficient
analog and mixed-signal semiconductors
– PowerWise® products consume less power, extend
battery life, and generate less heat
– SolarMagic™technology increases the overall
energy output of solar electric power generating
systems
• Founded in 1959 in Danbury, Connecticut, USA
• Headquartered in Santa Clara, California since 1967
• $1.89 billion sales for FY 2008 (June through May)
• Portfolio of over 3,095 patents
• 7,300+ employees worldwide
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PowerWise® Initiative
• PowerWise Devices
– 300 products selected by
strict power-to-performance
efficiency metrics in 25
product categories
PowerWise® Architecture
PowerWise®
Subsystem
• PowerWise Subsystems
– Complementary devices
act as a unit to provide
optimal mix of low power
consumption and heat
• PowerWise Architectures
Energy
Mgmt
Unit
Power
LDO
I
AMP
ADC
FPGA
RF
Q
AMP
SER/
DES
ADC
LDO
– Collaborations with system
designers to significantly
lower power consumption
while boosting performance
Clock
3
PowerWise® Devices
Data
National Space Operations
• 30+ years in the Space Market
• World Class Analog Products
– High Speed Converters
– High Speed and Precision Amplifiers
– Low Jitter Clocking and High Speed SerDes
• European Focus on Space
– Wafer Fab in Greenock Scotland
– Multiple Design Centres in Europe
– Dedicated Marketing & Engineering in European
Headquarters
• Radiation Testing
– TID: 60Co gamma cell in South Portland Maine and Santa
Clara California
– ELDRS:
ELDRS Free products
– SEE: SEL and SEU testing
4
National Space Strategy
– A Rich Space Analog Portfolio
QMLV Qualified Products
Analog Building Blocks
World-Class Product Portfolio
• State of the art radiation tolerant process technology
• Industry leading hermetic package technology
• Quality, Delivery and Performance
5
Focused Satellite Applications
Applications
AOCS
System Function
Maintain or
Change Orbit
System
Requirements
Lower Power,
Increase
Precision
Technology
Needed Now
GP ADC & DACs
Precision Amps,
Temp Sensors
Timing/Interface Communication
Payload & Bus
Communication &
Signal Integrity
Space
Imaging
Backbone of
Communications
Market
Integral in National
Security and
Tracking
Low Power, High Speed,
Low Phase Noise and
Jitter, Increase
Precision
Higher Bandwidth,
Lower Noise Power
Ratio, Lower Power
Lower Power,
Higher
Resolution, More
Integration
Precision Clock
Conditioners &
References, SerDes &
Buffers, Comparators
High Speed & Giga
Sample ADCs, Giga
Sample DACs
Low Power Analog
Front Ends
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High Performance Analog for
Communications
Broadcast
Satellites
Two-way Comm
Satellites
ATM Space
System
Navigation
Satellites
(GPS, Galileo,
GLONASS)
Network Centric
ATM_213
Tx/Rx Solution
for Communications Satellites
Jitter Clean Up
Clock
Dist
To Tx
Module
RF Gain Block
PA
1st Stage – Discrete Filter
Stage – Gain w/Low Noise
2nd
VCO
Processing
Module
PLL
Clock
LVDS
IF Gain Stage
1st Stage – Discrete Filter
2nd Stage – Gain w/Low Noise
DAC
De-Ser
Ser
FPGA
or
VCO
PLL
ASIC
Tx – RF Module
Jitter Clean Up
VCO
PLL
To Rx
Module
Clock
Dist
VCO
PLL
Clock
FPGA
Low Noise Block
1st Stage - Low Noise X-tor
2nd Stage – Gain w/Low Noise
or
LVDS
IF Gain Stage
1st Stage – Discrete Filter
2nd Stage – Gain w/Low Noise
3rd Stage – Discrete Attenuator
ADC
Ser
Rx – RF Module
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ASIC
De-Ser
ADC08D1520
QMLV Available
• Dual Channel 8-Bit 1.5 GSPS ADC,
Single 8-bit 3 GSPS ADC
–
–
–
–
–
–
–
–
–
–
Max sampling frequency 1.7GSPS
Inputs may be interleaved to obtain a
3GSPS single ADC
Full power bandwidth of 2 GHz
7.15 ENOBs out to Nyquist
Lowest Power in the industry at 1 W per
channel at 1.5 GSPS from single 1.9V
supply
Very low cross-talk (-71 dB @ 867 MHz)
Low-noise deMUX’d LVDS outputs
Guaranteed no missing codes
In 128 pin Hermetic Ceramic Quad Flat
Pack
Space Level Version
•
•
–
TID of 300 krad(Si)
Single Event Latchup > 120 Mev
Order as 5962F0721401VZC
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ADC08D1520WG-QV Block Diagram
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Bench FFT , Sample Rate = 1500Mhz
Input 97.47MHz I Channel
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Bench FFT , Sample Rate = 1500Mhz
Input 797.47MHz I Channel
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Bench FFT , Sample Rate = 1500Mhz
Input 997.47MHz I Channel
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The Need for More Dynamic Range
Higher Orders of Modulation
• Higher dynamic range enables higher orders of modulation giving satellite
operators higher data rates, increased functionality & power savings
Modulation Example:
16-QAM Example
QAM – Quadrature Amplitude Modulation
Data
Modulator
+
90° out of phase and
varying amplitude
QPSK (4-QAM)
θ
= Phase
At receiver, unique
amplitude and phase of
received signal determines
the symbol sent, 1100 in
this 16-QAM example
Transmitted signal has an
amplitude and phase component
64-QAM
16-QAM
……...128-QAM ….....256-QAM ….
Spacing Between Symbols Decreases
Higher Resolution ADCs & More Dynamic Range Needed
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The Need for More Dynamic Range
Higher Orders of Modulation
• As modulation order increases, the spacing between symbols
decreases
• Increased SNR due to increased resolution allows higher order
modulation schemes to be resolved
QPSK (4-QAM)
16-QAM
64-QAM
……...128-QAM
….....256-QAM ….
Spacing Between Symbols Decreases
Higher Resolution ADCs & More Dynamic Range Needed
• Higher order modulation encodes more bits per symbol increasing
Bandwidth efficiency
– Enables satellite operators increased functionality (data, voice, video)
• Increased bits per symbol reduces the number of transmissions
required
– Lower power consumption of satellite receiver
– Longer battery life for terrestrial mobile handsets
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The Need for More Dynamic Range
• Increase in dynamic range
– Improves satellite
reception in harsh
weather conditions
• Permits processing of
weak and high strength
signals
• Reduces downgrading of
modulation order
– Maintains data rate
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The Need for
Speed & Increased Input Bandwidth
• Giga Sample ADCs increase
Nyquist bandwidth (Wideband
Communications)
– More carriers allowing for more
user channels available for lease
– More flexibility in modulation
techniques
• More flexibility in CDM sub-carrier
bandwidth
• Large Input Bandwidth
– Reduces the number of down
conversion stages
– Higher IF sampling
– Direct RF sampling of L-Band
and some S-Band payloads
– Reduces payload power budget
and weight
RF
Stage
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IF
Stage
ADC
Digital
Proc
Narrowband Receiver
RF
Stage
IF
Stage
IF
Stage
BPF
ADC
(Passive)
Digital
Proc
• Sufficient ADC BW can eliminate 2nd IF Stage (RF mixer & freq synthesizer)
– Reduces system cost – fewer components per RX channel
– Reduces system weight and power, benefit is multiplied over multiple channels
• High X MSPS Sample Rate allows instantaneous sampling of ½X MHz BW signal
– More FDM channels & Fewer RX channel
– Overall reduction in power consumption and payload weight
• Large SNR and SFDR allows higher order modulation schemes
– Increases overall system throughput
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ADC14155 – Solution for narrowband
Now
communications systems Space Sampling
Level Release Sep 08
• 14-bit 155 MSPS ADC
–
Input bandwidth of 1.1GHz
–
11.4 ENOBs out to Nyquist, 11.3 ENOBs at
fin=200MHz
–
SNR of 71 dB at Nyquist, 70 dB at fin=200MHz
–
SFDR of 87 dB at Nyquist, 81 dB at fin=200MHz
–
Power Consumption of 967mW at 155 MSPS
–
INL of +/- 1.9 LSBs
–
DNL of +/-0.5 LSBs
–
Guaranteed no missing codes
–
Dual 1.8V and 3.3V operation
–
In 48 pin Hermetic Ceramic Quad Flat Pack
–
Space Level Version
• TID of 100 krad(Si)
• Single Event Latchup > 120 MeV
–
Order as 5962R0626201VXC
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High Performance Analog for
Attitude & Orbit Control Systems (AOCS)
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AOCS Signal Path Products
Driver Amps
LMP2012
Sensors
DAC121S101
DAC
Gyroscope
Pressure
Temperature
Sun
Star
FPGA
DATA
PROCESSING
ADC128S102
ADC
Temp
Analog
Switches
Buffer Amps
LMP2012
Vref
• ADC - Low Power, 12-bit, 8 Input Mux, 1MSPS, with SPI output
• DAC - Low Power, 12-bit, 12μs settling time, 20MHz SPI input
• Precision Amplifier - Dual Channel, No 1/f noise, Stable over Time and
Temperature, 5V RRO, Gain Bandwidth 3MHz
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ADC128S102 – Application Advantages
ADC Sampling Clock
Serial Data IN
Serial Data OUT
N analog lines
from sensors
Logic
x ADC Decoder
CS lines
ADC128S102
ADC124S101
Pressure Sensor
Earth Sensor
Sun Sensor
Inertial Sensor
Etc…
ADC Selection
Eight sensors can be monitored with
one ADC
Large number of analog sensor
measurements are digitized early in the
signal path.
ADC addressing through CS decoder
All ADC serialized data shares the same
input bus to onboard FPGA/ASIC
ADC128S102
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LMP2012
QMLV Available!
Dual Channel, High Precision,
Rail-to-Rail Output Op Amp
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–
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–
–
–
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Very Low TCVOS – 0.015uV/°C
Low Input offset voltage of 60 μV
over time and temperature.
No 1/f noise - input-referred voltage
noise of 35 nV/ Hz
Low supply current – 920uA
Wide gain bandwidth – 3MHz
2.7 to 5.0V supply voltage range
High CMRR – 130 dB
High PSRR – 120 dB
Hermetic 10-pin ceramic gullwing flat
package
Space Level version
•
•
•
–
TID of 50 krad(Si)
ELDRS qualified to 50 krad(Si)
Low SET Cross-Section
Order as 5962L062061VZA
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Thank you!
Questions????
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