COMP 3202
The Nature of Computing
Short Report 3
Semester 1 2014/15
Assessed Learning Outcome
ILO1: Critically reflect on how to design computer
hardware components or systems.
Words:
You may achieve the maximum grade for 750 words.
You will NOT be penalised for exceeding this.
Item Weighting
Author and Moderator
25%
Written by Colin Price, Moderated by Pete Moody
Report Structure.
You must address only one question. Each question carries the same weight. Please consult the Assessment Matrix below.
Question 1. SAM-4 CPU Simulator
Using the SAM-4 CPU Simulator, critically reflect on the design and operation of a register-based RISC CPU. In particular you should explain the FetchExecute cycle for one or more instructions. You may wish to explain in detail how data moves to its intended location on the CPU depending on the particular
instruction executed
Question 2. Synthesising a CPU using VHDL
Critically reflect on your experiences using the VHDL language to design a CPU circuit. In particular you should explain how one component of the CPU can
be synthesised using VHDL and tested using a testbench waveform. You may choose a component from the following list: ALU, MUX, RAM, Registers or the
Control Unit. You should also explain how your chosen component works with the entire CPU design.
Handing In and Return of Marked Report
Assessment: You will email your Tutor with your final report by 15:00 on Monday 5th January 2015 for grading. Your grades will be available the following
week.
Grading Matrix Template
This matrix captures the assessment criteria for this part of the coursework.
Student Number:
Academic Year and
Semester: 2014-15 S1
Assessment Criteria
Module Code:
COMP3202
Module Title:
Nature of Computing
Assignment No:
1
Assignment Weighting:
25%
Occurrence:
A/B
Assignment Description:
Short Report 3
ILO1: Critically reflect on how to design computer
hardware components or systems.
Assessment Criteria
GRADE
Criteria (Question 1)
Criteria (Question 2)
A
Comprehensive and correct explanation of the fetch-execute cycle for
SAM4, drawing out the differences between fetch-execute cycles for two
or more carefully chosen example instructions
Correct explanation of how one CPU component is designed using VHDL and
an explanation of how the testbench waveform verifies your design is correct.
In depth and correct explanation of how this component fits into the overall
working of the CPU including reference to testbench waveforms
B
Correct explanation of the fetch-execute cycle (SAM-4) for two CPU
instructions, and an attempt at drawing out the differences between the
corresponding fetch-execute cycles.
Correct explanation of how one CPU component is designed using VHDL and
an explanation of how the testbench waveform verifies your design is correct.
Attempt at explaining how this component fits into the overall working of the
CPU.
C
Correct explanation of the fetch-execute cycle (SAM-4) for one CPU
instruction
Correct explanation of how one CPU component is designed using VHDL and
an explanation of how the testbench waveform verifies your design is correct.
D
Attempt at a correct explanation of the fetch-execute cycle (SAM-4) for
one CPU instruction
Attempt at a correct explanation of one CPU component is designed using
VHDL and an attempt at using a testbench waveform to verify the design is
correct.
Fail (E-G)
Very weak or no attempt at explaining the fetch-execute cycle (SAM-4) for
one CPU instruction
Very weak or no attempt at explaining the design of one CPU component using
VHDL and a weak or no attempt at using a testbench waveform.