Virtual memory
Build new hardware that automatically translates each memory reference from a virtual address (that the programmer sees as an array of bytes) to a physical address (that the hardware uses to either index DRAM or identify where the storage resides on disk)
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Basics of Virtual memory
Any time you see the word virtual in computer science/architecture it means “ using a level of indirection ”
Virtual memory hardware changes the virtual address the programmer see into the physical ones the memory chips see.
0x800
Virtual address Physical address
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Another View of the Memory Hierarchy
Thus far
Next:
Virtual
Memory
{
{
Regs
Instr. Operands
Cache
Blocks
L2 Cache
Blocks
Memory
Pages
Disk
Files
Tape
Upper Level
Faster
Larger
Lower Level
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Virtual Memory
If Principle of Locality allows caches to offer
(usually) speed of cache memory with size of DRAM memory, then recursively why not use at next level to give speed of DRAM memory, size of Disk memory?
Called “ Virtual Memory ”
• Also allows OS to share memory, protect programs from each other
• Today, more important for protection vs. just another level of memory hierarchy
• Historically, it predates caches
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Basic Issues in Virtual Memory System Design
• Size of information blocks that are transferred from secondary to main storage (M)
• Block of information brought into M, and M is full, then some region of M must be released to make room for the new block replacement policy
• which region of M is to hold the new block --> placement policy mem disk cache reg pages frame
Paging Organization virtual and physical address space partitioned into blocks of equal size page frames pages
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Virtual Memory View
Virtual memory lets the programmer “see” a memory array larger than the DRAM available on a particular computer system.
Virtual memory enables multiple programs to share the physical memory without:
• Knowing other programs exist.
• Worrying about one program modifying the data contents of another.
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Managing virtual memory
Managed by hardware logic and operating system software.
• Hardware for speed.
• Software for flexibility and because disk storage is controlled by the operating system.
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Virtual to Physical Address Translation
Program operates in its virtual address space virtual address
(inst. fetch load, store)
HW mapping physical address
(inst. fetch load, store)
Physical memory
(incl. caches)
Each program operates in its own virtual address space;
~only program running
Each is protected from the other
OS can decide where each goes in memory
Hardware (HW) provides virtual -> physical mapping
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Virtual Memory
Treat main memory like a cache
• Misses go to the disk
How do we minimize disk accesses?
• Buy lots of memory.
• Exploit temporal locality
 Fully associative? Set associative? Direct mapped?
• Exploit spatial locality
 How big should a block be?
• Write-back or write-through?
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Virtual memory terminology
Blocks are called Pages
• A virtual address consists of
 A virtual page number
 A page offset field (low order bits of the address)
Virtual page number Page offset
0 31 11
Misses are call Page faults
• and they are generally handled as an exception
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Address Translation
Virtual address
Address translation
0
0
Physical address
0
Disk addresses
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Need a Page Table (table that tracks where all virtual memory pages are) components
Page table register
Virtual page number Page offset valid Physical page number
1 Physical page number
Physical page number Page offset
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Page table components
Page table register
0x00004 valid Physical page number
0x0F3
1 0x020C0
0x020C0 0x0F3
Physical address = 0x020C00F3
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Page table components
Page table register
0x00002 valid Physical page number
0 Disk address
0x082
Exception: page fault
1.
Stop this process
2.
Pick page to replace
3.
Write back data
4.
Get referenced page
5.
Update page table
6.
Reschedule process
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Putting it all together
Loading your program in memory
• Ask operating system to create a new process
• Construct a page table for this process
• Mark all page table entries as invalid with a pointer to the disk image of the program
 That is, point to the executable file containing the binary.
• Run the program and get an immediate page fault on the first instruction.
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Mapping Virtual Memory to Physical Memory
Divide into equal sized chunks (about 4KB)
Any chunk of Virtual Memory assigned to any chuck of Physical Memory
(“ page ”)
Page Frame (PF) holds a page in
Physical Memory
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Paging Organization (assume 1 KB pages)
Physical
Address
0
Page is unit of mapping page 0 1K
1 024
page 1
1K
Addr
Virtual
Address
0
Trans
1 024 page 0 1K page 1
2 048 page 2
1K
1K
7 168 page 7
1K MAP
Physical
Memory
31 744
Page also unit of transfer from disk to physical memory page 31
Virtual
Memory
1K
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Virtual Memory Mapping Function
Cannot have simple function to predict arbitrary mapping
Use table lookup of mappings
Use table lookup (“ Page Table ”) for mappings: Page number is index
Virtual Memory Mapping Function
• Physical Offset = Virtual Offset
• Physical Page Number
= PageTable[Virtual Page Number]
(P.P.N. also called “ Page Frame ”)
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Page Table
A page table is an operating system structure which contains the mapping of virtual addresses to physical locations
• There are several different ways, all up to the operating system, to keep this data around
Each process running in the operating system has its own page table
• “ State ” of process is PC, all registers, plus page table
• OS changes page tables by changing contents of Page
Table Base Register
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Size of page table
How big is a page table entry?
• For MIPS the virtual address is 32 bits
 If the machine can support 1GB of physical memory and we use 4KB pages , then the physical page number is 30-12 or 18 bits . Plus another valid bit + other useful stuff ( read only, dirty, etc .)
 Let say about 3 bytes.
How many entries in the page table?
• MIPS virtual address is 32 bits – 12 bit page offset = 2 20 or ~1,000,000 entries
Total size of page table: ~ 3 megabytes
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Address Mapping: Page Table
Virtual Address: page no.
offset concatenation
Page Table
Base Reg index into page table
Page Table
V A.R.
P. P. A.
Val
-id
Access
Rights
Physical
Page
Address
.
+
Physical
Memory
Address
Page Table located in physical memory
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VM Address Translation
Parameters
• P = 2 p = page size (bytes). Typically 1KB –16KB
• N = 2 n = Virtual address limit
• M = 2 m = Physical address limit n–1 virtual page number p p–1 page offset
0 virtual address address translation m–1 physical page number p p–1 page offset
0 physical address
Notice that the page offset bits don't change as a result of translation
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Page Tables
Virtual Page
Number
Valid
1
1
0
1
1
1
0
1
1
0
Page Table
(physical page or disk address)
Physical Memory
Disk Storage
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A System with Physical Memory Only
Example:
• Most Cray machines, early PCs, nearly all embedded systems, etc.
Memory
0:
1:
Store 0x10
CPU
Load 0xf0
N-1:
CPU’s load or store addresses used directly to access memory.
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A System with Virtual Memory
Examples:
• workstations, servers, modern PCs, etc.
0:
1:
Memory
CPU
Virtual
Addresses
Store 0x10
Page Table
0:
1:
Physical
Addresses
Load 0xf0
P-1:
N-1:
Disk
Address Translation: the hardware converts virtual addresses into
physical addresses via an OS-managed lookup table (page table)
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Page Faults (Similar to “Cache Misses”)
What if an object is on disk rather than in memory?
• Page table entry indicates that the virtual address is not in memory
•
An OS trap handler is invoked, moving data from disk into memory
 current process suspends, others can resume
 OS has full control over placement, etc.
Memory
0:
1:
Virtual
Addresses
Page Table
0:
1:
Physical
Addresses
Load 0x05
CPU
Store 0xf8
P-1:
N-1:
Disk
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Servicing a Page Fault
Processor Signals Controller
• Read block of length P starting at disk address X and store starting at memory address Y
Read Occurs
• Direct Memory Access
• Under control of I/O controller
(1) Initiate Block Read
Processor
Reg (3) Read
Done
Cache
Memory-I/O bus
• Interrupt processor
• Can resume suspended process
Memory
I/O controller
Dis k
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Motivation: Memory Management for
Multiple Processes
Multiple processes can reside in physical memory.
How do we resolve address conflicts?
(Virtual) Memory Image for Alpha Process
Reserved
0000 03FF 8000 0000
Not yet allocated
$gp
0000 0001 2000 0000
$sp
Dynamic Data
Static Data
Text (Code)
Stack e.g., what if two different processes access their stacks at address 0x11fffff80 at the same time?
0000 0000 0001 0000
Not yet allocated
Reserved
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Solution: Separate Virtual Address Spaces
•
Virtual and physical address spaces divided into equal-sized blocks
 “Pages” (both virtual and physical)
• Each process has its own virtual address space
 operating system controls how virtual pages as assigned to physical memory
Process 1:
Virtual Addresses
0
VP 1
VP 2
Address
Translation
N-1
Physical Addresses
0
PP 2
Process 2:
0
VP 1
VP 2
N-1
M-1
PP 7
PP 10
(Read-only library code)
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Motivation : Process Protection
Page table entry contains access rights information
• Hardware enforces this protection (trap into OS if violation occurs)
Process i:
Page Tables
VP 0:
Read? Write?
Yes No
VP 1:
VP 2:
Yes
No
•
Yes
No
•
Physical Addr
PP 9
PP 4
XXXXXXX
•
Process j:
VP 0:
Read? Write?
Yes Yes
VP 1:
VP 2:
Yes
No
•
No
No
•
Physical Addr
PP 6
PP 9
XXXXXXX
•
0:
1:
Memory
N-1:
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Virtual Memory Problem #1
Not enough physical memory!
• Only, say, 64 MB of physical memory
• N processes, each 4GB of virtual memory!
• Could have 1K virtual pages/physical page!
Spatial Locality to the rescue
• Each page is 4 KB, lots of nearby references
• No matter how big program is, at any time only accessing a few pages
• “ Working Set ”: recently used pages
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Virtual Memory Problem #2
Map every address

1 extra memory accesses for every memory access
Observation: since locality in pages of data, must be locality in virtual addresses of those pages
Why not use a cache of virtual to physical address translations to make translation fast? (small is fast)
For historical reasons, cache is called a Translation
Lookaside Buffer , or TLB
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Translation Look-Aside Buffers
• TLBs usually small, typically 128 - 256 entries
• Like any other cache, the TLB can be fully associative, set associative, or direct mapped
Processor
VA hit PA
TLB
Lookup miss
Translation
Cache hit miss
Main
Memory data
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Virtual Memory Summary
Caches: Location, Organization (block size and associativity),
Replacement
Virtual memory provides
• protection, sharing, illusion of large main memory
Virtual Memory requires twice as many memory accesses, so we cache page table entries in the TLB.
Three things can go wrong on a memory access: cache miss, TLB miss, page fault.
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