First Course on
Chapter 1
Power Electronics
1-1
1-2
1-3
1-4
1-5
1-6
1-7
Ned Mohan
Oscar A. Schott Professor of Power Electronics and Systems
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455
USA
© Copyright Ned Mohan 2007
1
Role of Power Electronics
Power Electronics: An Enabling Technology
Introduction to Power Electronics
Applications and the Role of Power Electronics
Energy and the Environment
Need for High Efficiency and High Power Density
Structure of Power Electronics Interface
Voltage-Link Structure
Recent and Potential Advancements
References
Problems
© Copyright Ned Mohan 2007
2
Powering the Information Technology
Power Electronics
Interface
Converter
Source
24 V (dc)
Vin
Load
Power
Converter
Vo
5 V (dc)
Utility
3.3 V (dc)
Controller
Figure 1-1 Power electronics interface between the source and the load.
Controller
(a)
The power electronics interface facilitates the transfer of power from the source to the
load by converting voltages and currents from one form to another, in which it is possible
for the source and load to reverse roles. The controller shown in Fig. 1-1 allows
management of the power transfer process in which the conversion of voltages and
currents should be achieved with as high energy-efficiency and high power density as
possible.
0.5 V (dc)
Vo,ref
(b)
Figure 1-2 Regulated low-voltage dc power supplies.
3
© Copyright Ned Mohan 2007
4
Boost Converter
Adjustable Speed Drives
Electric
Drive
Battery
Cell (1.5 V)
fixed
form
9 V (dc)
Power
Processing
Unit (PPU)
Motor
speed /
position
adjustable
form
Electric Source
(utility)
Load
Sensors
Controller
measured
speed/ position
Figure 1-3 Boost dc-dc converter needed in cell operated equipment.
Power
Signal
input command
(speed / position)
Figure 1-4 Block diagramof adjustable speed drives.
© Copyright Ned Mohan 2007
5
Induction Heating
© Copyright Ned Mohan 2007
Electric Welding
Power
Electronics
Interface
High
Frequency
AC
Power
Electronics
Interface
Utility
DC
Utility
Figure 1-5 Power electronics interface required for induction heating.
© Copyright Ned Mohan 2007
6
Figure 1-6 Power electronics interface required for electric welding.
7
© Copyright Ned Mohan 2007
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Energy and the Environment: The Percentage
Energy Consumption
Role of adjustable speed drives in
pump-driven systems
Lighting 19%
Outlet
IT
14%
Adjustable
Speed Drive
(ASD)
utility
HVAC 16%
Inlet
Pump
Figure 1-8 Role of adjustable speed drives in pump-driven systems.
Motors 51%
Figure 1-7 Percentage use of electricity in various sectors in the U.S.
© Copyright Ned Mohan 2007
9
10
Transportation
Compact Fluorescent Lamps
Power
Electronics
Interface
© Copyright Ned Mohan 2007
CFL
Figure 1-10 Hybrid electric vehicles with much higher gas mileage.
Utility
Figure 1-9 Power electronics interface required for CFL.
• Hybrid electric vehicles with much higher gas mileage
• light rail, fly-by-wire planes
• all-electric ships
• drive-by-wire automobiles.
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
12
Renewable Energy
Wind-Electric Systems
Photovoltaic Systems
DC Input
Generator
and
Power Electronics
Power
Electronics
Interface
Utility
Utility
Figure 1-12 Wind-electric systems.
(b)
(a)
Figure 1-11 Photovoltaic Systems.
© Copyright Ned Mohan 2007
13
14
Strategic Space and Defense Applications
Uninterruptible Power Supplies
Uninterruptible
Power Supply
Utility
© Copyright Ned Mohan 2007
More Electric Aircraft
Electric Warship
Critical
Load
Figure 1-13 Uninterruptible power supply (UPS) system.
© Copyright Ned Mohan 2007
15
Source: James Soeder, NASA and Terry Ericsen, ONR.
© Copyright Ned Mohan 2007
16
NEED FOR HIGH EFFICIENCY AND
HIGH POWER DENSITY
η=
Po
Po + Ploss
Po =
η
1 −η
Summarizing the Role of Power Electronics
Ploss
Power
Electronics
Interface
500
450
Pin
Power
Electronics
Equipment
Po
Po
Power Rating
400
utility
350
300
250
Figure 1-15 Block diagramof power electronic interface.
Ploss = 20 W
200
Output to Load
- Adjustable DC
- Sinusoidal AC
- High-frequency AC
150
Ploss
(a )
Ploss = 10 W
100
50
0
0.8
0.82
0.84
0.86
0.88
0.9
0.92
Efficiency
η
0.94
0.96
(b)
Figure 1-14 Power output capability as a function of efficiency.
© Copyright Ned Mohan 2007
17
STRUCTURE OF POWER ELECTRONICS INTERFACE
© Copyright Ned Mohan 2007
18
• Current-Link Systems
• Matrix Converters
conv1
conv2
utility
Load
controller
Figure 1-16 Voltage-link structure of power electronics interface.
Voltage-link structure of power electronics interface
• Unipolar voltage handling transistors used
• Decoupling of two converters
• Immunity from momentary power interruptions
© Copyright Ned Mohan 2007
19
© Copyright Ned Mohan 2007
20
ia
va
vc
AC1
daA
vb
dbA
dcA
vA
daB
dbB
dcB
daC
vB
vC
dbC
dcC
AC2
Figure 1-18 Matrix converter structure of power electronics interface [13].
Figure 1-17 Current-link structure of power electronics interface.
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
22
SWITCH-MODE LOAD-SIDE CONVERTER
conv1
Group 1
Adjustable dc or a low-frequency sinusoidal ac output in
- dc and ac motor drives
- uninterruptible power supplies
- regulated dc power supplies without electrical isolation
•
Group 2
High-frequency ac in
- compact fluorescent lamps
- induction heating
- regulated dc power supplies where the dc output voltage needs to be
electrically isolated from the input, and the load-side converter
internally produces high-frequency ac, which is passed through a
high-frequency transformer and then rectified into dc.
conv2
utility
Load
controller
Figure 1-19 Load-side converter in a voltage-source structure.
© Copyright Ned Mohan 2007
•
23
© Copyright Ned Mohan 2007
24
Pulse-Width Modulation (PWM) of the Switching Power-Pole
Switch-Mode Conversion: Switching PowerPole as the Building Block
qA
idA
+
Vin
+
Vin
vvA
-
qA
vA
q A = 1or 0
t
d A ( = Tup / Ts )
vA =
© Copyright Ned Mohan 2007
25
Switching Power-Pole in a Buck DC-DC Converter:
An Example
qA
iin
0
iL
vA
+
+
vA
Vo
−
−
qA
Example 1-2
Vin = d AVin
0 ≤ dA ≤ 1
26
In the converter of Fig. 1-22a, the input voltage Vin = 20V . The
width Tup , if the switching frequency f s = 200 kHz .
t
dATs
Ts
Vin
Solution
0
v A = Vo = 12V .
t
t
0
t
Vo 12
1
= 5µs .
=
= 0.6 and Ts =
fs
Vin 20
1
qA
0
0
iin
Using Eq. 1-4, d A =
Therefore, as shown in Fig. 1-23, Tup = d ATs = 0.6 × 5µ s = 3µ s .
vA
iL
t
3µ s
5µ s
Vin = 20V
Vo = 12V
vA
0
Figure 1-22 Switching power-pole in a Buck converter.
0 ≤ Vo ≤ Vin
Ts
output voltage Vo = 12V . Calculate the duty-ratio d A and the pulse
1
(b)
Vo = v A = d AVin
Tup
© Copyright Ned Mohan 2007
(a)
© Copyright Ned Mohan 2007
t
Figure 1-21 PWM of the switching power-pole.
Figure 1-20 Switching power-pole as the building block in converters.
−
vA
0
(b)
(b)
(a)
+
Vin
(a)
00
Vin
t
Tup
Ts
-
Vin
A
+
vA
-
dA
0
vA
-
qA = 1
iA
d A Ts
+
1
t
Figure 1-23 Waveforms in the converter of Example 1-2.
27
© Copyright Ned Mohan 2007
28
RECENT AND POTENTIAL ADVANCEMENTS
Transistor and diode forming a switching power-pole
in a Buck converter
+
• Devices that can handle voltages in kVs and currents in kAs
• ASICs
iL
Vin
+
Vo
−
−
• DSPs
• Micro-controllers
• FPGA
(a)
+
iL
Vin
−
qA = 1
(b)
+
+
Vo
−
• Integrated and intelligent power modules
iL
−
qA = 0
• Packaging
+
Vo
−
Vin
• SiC-based solid-state devices
• High energy density capacitors
(c)
Figure 1-24 Transistor and diode forming a switching power-pole in a Buck converter.
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
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CONCEPT OF PEBB
Power Electronics Building Block (PEBB) [15] is a broad concept that
incorporates the progressive integration of power devices, gate drives,
and other components into building blocks, with clearly defined
functionality that provides interface capabilities able to serve multiple
applications. This building block approach results in reduced cost,
losses, weight, size, and engineering effort for the application and
maintenance of power electronics systems. Based on the functional
specifications of PEBB and the performance requirements of the
intended applications, the PEBB designer addresses the details of
device stresses, stray inductances, switching speed, losses, thermal
management, protection, measurements of required variables, control
interfaces, and potential integration issues at all levels.
Chapter 2
2-1
2-2
2-3
Power Transistors and Power Diodes
Selection of Power Transistors
Selection of Power Diodes
2-4
Switching Characteristics and Power Losses in Power-Poles
2-5
Justifying Switches and Diodes as Ideal
2-6
2-7
Design Considerations
The PWM Controller IC
References
Problems
Appendix 2A Diode Reverse-Recovery and Power Losses
It has numerous benefits such as technology insertion and upgrade via
standard interfaces, reduced maintenance via plug and play modules,
reduced cost via increased product development efficiency, reduced time to
market, reduced commissioning cost, reduced design and development risk,
and increased competition in critical technologies [14].
© Copyright Ned Mohan 2007
Design of Switching Power-Pole
31
© Copyright Ned Mohan 2007
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POWER TRANSISTORS AND POWER DIODES
• Voltage Rating
Power (VA)
108
• Current Rating
• Switching Speeds
Thyristor
• On-State Voltage
IGCT
IGBT
IGCT
IGBT
104
102
MOSFET
(a)
• MOSFETs
106
Thyristor
SELECTION OF POWER TRANSISTORS
MOSFET
101 102 103 104
Switching Frequency (Hz)
(b)
Figure 15-1 Power semiconductor devices.
• IGBTs
• IGCTs
• GTOs
• Niche devices: BJTs, SITs, MCTs
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
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MOSFETs
IGBTs
D
iD
iD
iD
RDS (on ) = 1/slope
VGS = 11V
+
9V
VDS
G
+
VGS
−S
7V
C
iC
+
5V
VGS ≤ VGS (th )
−
(a)
Io
0
VDS
(b)
0
VGS (th ) VGS ( I o )
(c)
VGS
G
Figure 2-1 MOSFET: (a) symbol, (b) i-v characteristics, (c) transfer characteristic.
+
VGE
−
E
(a)
2.5 to 2.7
RDS ( on ) α VDSS
© Copyright Ned Mohan 2007
iC
VGE
VCE
VCE
−
(b)
Figure 2-2 IGBT: (a) symbol, (b) i-v characteristics.
35
© Copyright Ned Mohan 2007
36
SELECTION OF POWER DIODES
Power Semiconductor Price Trends
0.7
iAK
USD/A
K
A
Pricing (USD/A) 1200 V IGBTs
0
0.6
0.5
(b)
(a)
0.4
v AK
Figure 2-3 Diode: (a) symbol, (b) i-v characteristic.
0.3
• Line-frequency diodes
0.2
• Fast-recovery diodes
0.1
0
• Schottky diodes
1990
1995
2000
2005
• SiC Schottky diodes
© Copyright Ned Mohan 2007
37
© Copyright Ned Mohan 2007
SWITCHING CHARACTERISTICS AND
POWER LOSSES IN POWER-POLES
iD
+
VGG
RGG
Vin
−
Turn-on Characteristic
Io
D
on
G
+
0
vGG
iD
vDS
Io
S
B
0
(b)
vDS
off
Io 0
off
Vin
vGG
Vin
iD
A
−
0
(a)
Vin
vDS
(b)
0
td ( on )
tri
t
vDS
Io
t fv
t
(c)
Figure 2-5 MOSFET turn-on.
Figure 2-4 MOSFET in a switching power-pole.
© Copyright Ned Mohan 2007
on
Vin
Io
(a)
vGS
vGS ( Io )
vGS (th )
iD
iD
+
vDS
−
38
39
© Copyright Ned Mohan 2007
40
Turn-off Characteristic
Example 2-1
In the converter of Fig. 2-4a, the transistor is a MOSFET which carries
a current of 5 A when it is fully on. If the current through the
transistor is to be limited to 40 A during a malfunction in which case
the entire input voltage of 50 V appears across the transistor, what
should be the maximum on-state gate voltage that the gate-drive circuit
should provide? Assume the junction temperature T j of the MOSFET
vGG
vGS ( Io )
vGS (th )
to be 1750 C .
Solution
iD
The transfer characteristic of this MOSFET is shown in Fig. 2-6. It shows that
G
vGG
100 A
40 A
+
Vin
−
10 A
ID
1A
D
iD
vDS
Io
S
0
on
C
0
D
Io
VGS
0.1 A
4.0 5.0 6.0 7.0 8.0 9.010.0
7.5V
(a)
if VGS = 7.5V is used, the current through the MOSFET will be limited to 40 A.
t
Vin
Io
off
Vin vDS
0
vGS
0
vDS
td ( off )
t rv
(b)
iD
t
t fi
(c)
Figure 2-7 MOSFET turn-off.
Figure 2-6 MOSFET transfer characteristic.
© Copyright Ned Mohan 2007
41
PSpice Modeling: C:\FirstCourse_PE_Book07\Power_pole_PSpice_Diode.sch
© Copyright Ned Mohan 2007
42
Simulation Results: MOSFET Voltage and Current
50
40
30
vDS
20
iD
10
0
-10
0s
V(M2:d,M2:s)
0.2us
-I(V2)
0.4us
0.6us
0.8us
1.0us
1.2us
1.4us
1.6us
Time
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
44
Calculating Power Losses Within the MOSFET
(assuming an ideal diode)
Conduction Loss:
Pcond = d RDS ( on ) I o2
Switching Losses:
1
Psw = Vin I o (tc , on + tc , off ) f s
2
Vin
vDS
iD
0
t fv
tri
tc , on
0
tc , off = trv + t fi
iD
t fi
trv
vc
S
t
tc , off
Vin I o
psw
Io
Vext = 12 V
VCC
tc , on = tri + t fv
Vin
vDS
Gate Driver Integrated Circuits (ICs) with Builtin Fault Protection
tc , on
Vin I o
psw
tc , off
Figure 2-9 Gate-driver IC functional diagram.
t
Figure 2-8 MOSFET switching losses.
© Copyright Ned Mohan 2007
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JUSTIFYING SWITCHES AND DIODES AS
IDEAL
© Copyright Ned Mohan 2007
46
DESIGN CONSIDERATIONS
Very High Converter Efficiencies
• Switching Frequency
• Low on-state voltage drops across devices
• Selection of Transistors and Diodes
• Low switching losses
• Magnetic components
Ap =
• Capacitor Selection
C
ESL
ˆ
LII
rms
kwJmaxBmax
Ap =
kconv ∑Vy Iy,rms
kwBmax Jmax fs
ESR
Figure 2-10 Capacitor ESR and ESL.
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
48
PSpice Modeling: C:\FirstCourse_PE_Book07\Capacitor_Characteristics.sch
Simulation Results: Individual and Total Admittances
50A
40A
30A
20A
10A
0A
1.0KHz
I(L2)
I(L1)
3.0KHz
-I(V3)
10KHz
30KHz
100KHz
300KHz
1.0MHz
Frequency
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
50
Design Tradeoffs
Thermal Design
T j = Ta + ( Rθ jc + Rθ cs + Rθ sa ) Pdiss
size
Heatsink
isolation pad
heat sink
Tj
case
Tc
Rθ jc
chip
Ts
Rθcs
Ta
Rθ sa
Magnetics and
capacitors
ambient
Ta
Pdiss
fS
Tj
Tc
Ts
(a)
Ta
Figure 2-12 Size of magnetic components and
heat sink as a function of frequency.
(b)
Figure 2-11 Thermal design: (a) semiconductor on a heat sink, (b) electrical analog.
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
52
APPENDIX 2A:
Diode Reverse Recovery and Power Losses
PWM CONTROLLER IC
Pdiode , F = (1 − d ) ⋅VFM I o
Diode Forward Loss:
Vˆr
0
dTs
Diode Reverse Recovery Characteristic:
vc (t)
vr
Ts
q(t)
ta
t
tb
0
t
1
0
t
Qrr
0
vc ( t )
Vˆr
t
Vd , neg
Figure 2A-1 Diode reverse recovery characteristic.
Diode Switching Losses:
© Copyright Ned Mohan 2007
I RRM
VFM
Figure 2-13 PWMIC waveforms.
d (t ) =
trr
53
PSpice Modeling: C:\FirstCourse_PE_Book07\ Power_pole_MUR2020.sch
© Copyright Ned Mohan 2007
1
Pdiode , sw = ( I RRM tb ) ⋅Vd , neg ⋅ f s
2
54
Simulation Results: MOSFET Voltage and Current
50
40
30
20
10
0
-10
0s
V(M2:d,M2:s)
0.2us
-I(V2)
0.4us
0.6us
0.8us
1.0us
1.2us
1.4us
1.6us
Time
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
56
Example 2A-1 In the switching power-pole of Fig. 2-4a, Vin = 40V and the output
current is I o = 5 A . The switching frequency f s = 200 kHz . The MOSFET switching
Chapter 3
Switch-Mode DC-DC Converters: Switching Analysis, Topology
Selection and Design
times are tri = 15 ns and t fv = 15 ns . The diode snaps-off at reverse recovery such that
3-1
trr = ta = 20 ns (such that tb = 0 ) and the peak reverse-recovery current I RRM = 2 A .
3-2
Switching Power-Pole in DC Steady State
3-3
Simplifying Assumptions
Calculate the additional power loss in the MOSFET due to the diode reverse recovery.
Vin
t fv
vDS
0
t
t fv
I RRM
Io
iD
0
t
psw
DC-DC Converters
3-4
Common Operating Principles
3-5
Buck Converter Switching Analysis in DC Steady State
3-6
Boost Converter Switching Analysis in DC Steady State
3-7
Buck-Boost Converter Switching Analysis in DC Steady State
3-8
Topology Selection
3-9
Worst-Case Design
3-10
Synchronous-Rectified Buck Converter for Very Low Output Voltages
3-11
Interleaving of Converters
3-12
Regulation of DC-DC Converters by PWM
3-13
Dynamic Average Representation of Converters in CCM
3-14
Bi-Directional Switching Power-Pole
3-15
Discontinuous-Conduction Mode (DCM)
References
Problems
t
0
tri
ta = trr
Figure 2A-2 Waveforms with diode reverse-recovery current.
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
58
Switching power-pole as the building block of dc-dc converters
Regulated switch-mode dc power supplies
iL
Vin
Vin
dc-dc
converter
topology
Vo
(a)
DTs
Ts
B
iL
t
0
q
(a)
(b)
Figure 3-2 Switching power-pole as the building block of dc-dc converters.
Vo , ref
iL(t) = iL(t −Ts )
(b)


DTs
Ts


1
VL =  ∫ vL ⋅ dτ + ∫ vL ⋅ dτ  = 0
Ts  0

DTs


A
area
area B


vC (t ) = vC (t − Ts )
Figure 3-1 Regulated switch-mode dc power supplies.
© Copyright Ned Mohan 2007
t
0
vL
Vin , Vo
I in , I o
controller
A
vL
59
© Copyright Ned Mohan 2007
60
Example 3-2
The capacitor current iC , shown in Fig. 3-4a, is flowing through a
capacitor of 100 µ F . Calculate the peak-peak ripple in the capacitor
voltage waveform due to this ripple current.
Example 3-1
If the current waveform in steady state in an inductor of 50µ H is as
Solution For the given capacitor current waveform, the capacitor voltage waveform, as
shown in Fig. 3-4b, is at its minimum at time t1 , prior to which the capacitor current has
shown in Fig. 3-3a, calculate the inductor voltage waveform vL (t ) .
Solution
During the current rise-time,
vL = L
been negative. This voltage waveform reaches its peak at time t2 , beyond which the
di (4 − 3)  1  A
=
=   . Therefore,
dt
3µ
 3µ  s
current becomes negative.
di
1
= 50µ ×
= 16.67V .
dt
3µ
The hatched area in Fig. 3-4a equals the charge Q
t2
Q = ∫ iC ⋅ dt =
di (3 − 4)  1  A
During the current fall-time,
=
= −
 . Therefore,
dt
2µ
 2µ  s
vL = L
t1
1
× 0.5 × 2.5µ = 0.625µC
2
Using Eq. 3-6, the peak-peak ripple in the capacitor voltage is ∆V p − p =
di
1
= 50µ × ( − ) = −25V .
dt
2µ
Q
= 6.25 mV .
C
Therefore, the inductor voltage waveform is as shown in Fig. 3-3b.
iC
0.5A
iL
4A
(a )
3A
(a )
0
( b)
t
−0.5A
3µ s
2µ s
2.5µ s
vC ,ripple
16.67V
0
3µ s
t
5µ s
vL
Q
0
( b)
∆V p − p
0
t
t
t1
t2
Figure 3-4 Example 3-2.
−25V
Figure 3-3 Example 3-1.
© Copyright Ned Mohan 2007
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© Copyright Ned Mohan 2007
62
BUCK CONVERTER SWITCHING ANALYSIS IN DC STEADY STATE
iin
• Simplifying Assumptions
Vin
• Two-Step Process
vL
vA
• Common Operating Principles
1
q
iC
Io
Vo
(a)
q
vA
q =1
vL
VA = Vo
Vin
vA
t
0
vL
0
t
(−Vo )
B
∆iL
Vo iL ,ripple
t
0
vL = Vin − Vo
(b)
iL
vL = −Vo
Vin
vA
iL
I L = Io
0
Vo
t
I in
iin
t
0
q=0
Vo = VA = DVin
A (V − V )
in
o
iL
Vin
t
0
iL
vA = 0
(d)
(c)
∆iL =
Vin − Vo
V
DTs = o (1 − D )Ts
L
L
I L = Io =
Vo
R
Vin I in = Vo I o
I in = DI L = DI o
Figure 3-5 Buck dc-dc converter.
iC (t ) iL ,ripple (t )
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© Copyright Ned Mohan 2007
64
Example 3-3
In the Buck dc-dc converter of Fig. 3-5a, L = 24 µ H . It is operating in
PSpice Modeling: C:\FirstCourse_PE_Book07\Buckconv.sch
dc steady state under the following conditions: Vin = 20V , D = 0.6 , Po = 14 W , and
f s = 200 kHz . Assuming ideal components, calculate and draw the waveforms shown
Fig. 3-6
earlier in Fig. 3-5d.
Solution
q
With f s = 200 kHz , Ts = 5µ s and Ton = DTs = 3µ s . Vo = DVin = 12V .
1
0
The inductor voltage vL fluctuates between (Vin − Vo ) = 8V and ( −Vo ) = −12 V , as shown in
Fig. 3-6.
3µ s
t
5µ s
V A = Vo = 12V
Vin = 20
vA
t
0
(Vin − Vo ) = 8V
vL
t
0
−Vo = −12V
∆∆iLL = 1 A
0.5 A
iL ,ripple
0.5
t
0
−−0.5
0.5 A
1.5
1.667 A
iL
0
0.667A
0.5
I L = I 0 = 1.167 A
I L = I o = 1A
t
1.51.667 A
iin
I in = 0.6 A
0.5
I in = 0.7 A
0.667A
0
© Copyright Ned Mohan 2007
65t
© Copyright Ned Mohan 2007
66
BOOST CONVERTER SWITCHING ANALYSIS IN DC STEADY STATE
Simulation Results
16
12
iL
iL
8
Vo
C
vL
4
0
p
q
Vin
C
vL
Vin
p
q
(a)
Vo
(b)
-4
Figure 3-7 Boost dc-dc converter.
-8
450us
I(C1)
455us
460us
I(L1) V(L1:1,L1:2)
465us
470us
475us
480us
485us
490us
495us
500us
Time
© Copyright Ned Mohan 2007
67
© Copyright Ned Mohan 2007
68
Boost converter: operation and waveforms
Example 3-4 In a Boost converter of Fig. 3-8a, the inductor current has ∆iL = 2 A . It
is operating in dc steady state under the following conditions: Vin = 5V , Vo = 12V ,
Po = 11W , and f s = 200 kHz . (a) Assuming ideal components, calculate L and draw the
q
t
0
vL = Vin
Vin
vA = 0
iL
vA
Vo
v A = Vin
Vo
t
0
A
vL
t
B
−(Vo − Vin )
(a)
t
0
iL
Vin
vL = Vin − Vo
IL
0
Vo
t
I diode (= I o )
idiode
v A = Vo
∆ iL =
∆iL
iL ,ripple
iL
waveforms as shown in Fig. 3-8c.
Solution
From Eq. 3-19, the duty-ratio D = 0.583 . With f s = 200 kHz , Ts = 5µ s and
(Vo > Vin )
Ton = DTs = 2.917 µ s .
Vin
0
q =1
Vo
1
=
Vin 1 − D
t
0
Vin
V − Vin
DTs = o
(1 − D )Ts
L
L
L=
q=0
(b)
The average inductor current is I L = I in = Pin ( = Po ) / Vin = 2.2 A , and iL = I L + iL,ripple . When
the transistor is on, the diode current is zero; otherwise idiode = iL . The average diode
Vo
I
1 Vo
Io = o =
Vin
1− D 1− D R
current is equal to the average output current:
iC (t ) idiode ,ripple (t ) = idiode − I o
I diode = I o = (1 − D ) I in = 0.917 A .
The capacitor current is iC = idiode − I o . When the transistor is on, the diode current is zero
and iC = − I o = −0.917 A . The capacitor current jumps to a value of 2.283 A and drops to
1 − 0.917 = 0.083 A .
(c)
Figure 3-8 Boost converter: operation and waveforms.
© Copyright Ned Mohan 2007
69
q
0
© Copyright Ned Mohan 2007
70
PSpice Modeling: C:\FirstCourse_PE_Book07\Boost.sch
t
3µ s
Vin
DTs = 7.29 µ H .
∆iL
I L = I in =
t
0
Using the
Vin I in = Vo I o
iC
(− I0 )
vL fluctuates between Vin = 5V and −(Vo − Vin ) = −7V .
conditions during the transistor on-time, from Eq. 3-21,
5µ s
vA
Vo = 12V
v A = Vin = 5V
t
0
vL
Vin = 5V
t
0
−(Vo − Vin ) = −7V
1A
∆iL = 2 A
iL ,ripple
t
0
−1 A
3.2 A
iin
0
I L = 2.2 A
1.2 A
idiode
3.2 A
1.2 A
t
I diode ( = I o ) = 0.917 A
0
t
2.283 A
iC
0.283 A
0
t
−0.917 A
© Copyright Ned Mohan 2007
Figure 3-9 Example 3-4.
71
© Copyright Ned Mohan 2007
72
Simulation Results
Boost converter: voltage transfer ratio
15
Vo
Vin
10
5
1
1− D
1
0
IL
0
DCM
I L ,crit
CCM
Figure 3-10 Boost converter: voltage transfer ratio.
-5
-10
-15
1.950ms
I(L1)
1.955ms
V(L1:1,L1:2)
1.960ms
1.965ms
1.970ms
1.975ms
1.980ms
1.985ms
1.990ms
1.995ms
2.000ms
Time
© Copyright Ned Mohan 2007
73
© Copyright Ned Mohan 2007
74
Buck-Boost converter: operation and waveforms
BUCK-BOOST CONVERTER ANALYSIS IN DC
STEADY STATE
q
v A = Vin + Vo
0
Vin
iin
vL = Vin
iL
t
DTs
Ts
vA
(Vin + Vo )
VA = Vo
Io
Vo
t
0
vL
A
Vin
t
0
A
iL
vL
vA
q
Vin
idiode
Io
Vo
(a)
vA
Vin
vL
vA = 0
Io
iL
iL , ripple
∆iL
t
iL
vL = −Vo
iL
Io
Vo
(b)
(a)
B
0
iin
Vin
Vo
−Vo
0
IL
idiode
I diode (= I o )
iC
t
( − I 0 0)
Figure 3-11 Buck-Boost dc-dc converter.
(c)
Figure 3-12 Buck-Boost converter: operation and waveforms.
iC (t ) idiode ,ripple (t )
© Copyright Ned Mohan 2007
t
t
0
(b)
75
© Copyright Ned Mohan 2007
Vo
D
=
Vin 1 − D
∆ iL =
Vin
V
DTs = o (1 − D )Ts
L
L
I L = I in + I o
Vin I in = Vo I o
V
D
I in = o I o =
Io
1− D
Vin
I L = I in + I o =
1
1 Vo
Io =
1− D
1− D R
76
q
0
Example 3-5 A Buck-Boost converter of 3-11b is operating in dc steady state under
the following conditions: Vin = 14V , Vo = 42V , Po = 21W , ∆iL = 1.8 A and f s = 200 kHz .
vA
Assuming ideal components, calculate L and draw the waveforms as shown in Fig. 312c.
Solution
VA = Vo = 42V
t
0
Vin = 14V
t
0
Fig. 3-13. The inductor voltage vL fluctuates between Vin = 14V and −Vo = −42V . Using
iL ,ripple
Eq. 3-28
V
L = in DTs = 29.17 µ H .
∆iL
−Vo = −42V
0.9 A
∆iL = 1.8 A
t
0
−0.9 A
I o = Po / Vo = 0.5 A .
2.9A
iL
Therefore,
I L = I in + I o = 2 A . When the transistor is on, the diode current is zero; otherwise idiode = iL .
0
The average diode current is equal to the average output current: I diode = I o = 0.5 A . The
idiode
1.1A I L = 2 A
2.9A
1.1A
capacitor current is iC = idiode − I o . When the transistor is on, the diode current is zero and
iC = − I o = −0.5 A .
5µ s
(Vin + Vo ) = 56V
vL
From Eq. 3-26, D = 0.75 . Ts = 1/ f s = 5µ s and Ton = DTs = 3.75µ s as shown in
The average input current is I in = Pin ( = Po ) / Vin = 1.5 A .
t
3.75µ s
t
I diode ( = I o ) = 0.5 A
t
0
The capacitor current jumps to a value of 2.4 A and drops to
2.4A
iC
1.1 − 0.5 = 0.6A .
0
0.6A
t
−0.5A
Figure 3-13 Example 3-5.
© Copyright Ned Mohan 2007
77
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Switching.sch
© Copyright Ned Mohan 2007
78
Simulation Results
20
10
0
-10
-20
-30
2.950ms
I(L1)
2.955ms
V(L1:1,L1:2)
2.960ms
2.965ms
2.970ms
2.975ms
2.980ms
2.985ms
2.990ms
2.995ms
3.000ms
Time
© Copyright Ned Mohan 2007
79
© Copyright Ned Mohan 2007
80
Buck-Boost converter: voltage transfer ratio
Other Buck-Boost Topologies
• SEPIC Converters (Single-Ended Primary Inductor Converters)
Vo
Vin
• Cuk Converters
D
1− D
0
DCM
IL
CCM
I L ,crit
Figure 3-14 Buck-Boost converter: voltage transfer ratio.
© Copyright Ned Mohan 2007
81
© Copyright Ned Mohan 2007
SEPIC Converters (Single-Ended Primary Inductor Converters)
iL
(a)
vC
vL 2
Vin
82
Cuk Converter
idiode
Vo
iL 2
(a)
(b) Vin
q =1
Vo
vL 2 = vC
vC
vL 2
(c) Vin
q=0
(b) Vin
Vo
vL 2 = −Vo
© Copyright Ned Mohan 2007
L1
C
L2
Vo
Io
vC
io
iin
Vo
(c)
Vin
q =1
Figure 3-15 SEPIC converter.
DVin = (1 − D )Vo
io
q
vC
vL 2
vC
Vin
q
vC
iL
iin
io
Vo
q=0
Figure 3-16 Cuk converter.
DI o = (1 − D ) I in
Vo
D
=
Vin 1 − D
83
© Copyright Ned Mohan 2007
I in
D
=
Io 1 − D
Vo
D
=
Vin 1 − D
84
WORST-CASE DESIGN
TOPOLOGY SELECTION
Criterion
Buck
Boost
Transistor Vˆ
Vin
Vo
(Vin + Vo )
Transistor Iˆ
Io
I in
I in + I o
DI o
DI in
D ( I in + I o )
DI o
DI in
D ( I in + I o )
(1 − D) I o
(1 − D) I in
(1 − D ) ( I in + I o )
I rms
Transistor
I avg
Transistor
Diode
Io
I in
I in + I o
Effect of L on C
significant
little
little
Pulsating Current
input
output
both
IL
The worst-case design should consider the ranges in which the input voltage and the
output load vary. As mentioned earlier, often converters above a few tens of watts are
designed to operate in CCM. To ensure CCM even under very light load conditions
would require prohibitively large inductance. Hence, the inductance value chosen is
Buck-Boost
often no larger than three times the critical inductance ( L < 3Lc ) , where, as discussed in
section 3-15, the critical inductance Lc is the value of the inductor that will make the
converter operate at the border of CCM and DCM at full-load.
© Copyright Ned Mohan 2007
85
SYNCHRONOUS-RECTIFIED BUCK CONVERTER FOR
VERY LOW OUTPUT VOLTAGES
q+
© Copyright Ned Mohan 2007
86
INTERLEAVING OF CONVERTERS
q−
q1
T+
iL
q+
Vin
T−
q−
0
DTs
vA
Vin
0
vA
Vo
t
Ts
t
iL
IL
0
(a)
iL 2
Vin
−
Vo
0
iL1
+
t
t =0
q1
(b)
q2
+
Vo
−
q2
t
0
(a)
(b)
Figure 3-18 Interleaving of converters.
Figure 3-17 Buck converter: synchronous rectified.
© Copyright Ned Mohan 2007
t
0
87
© Copyright Ned Mohan 2007
88
REGULATION OF DC-DC CONVERTERS BY PWM
DYNAMIC AVERAGE REPRESENTATION OF
CONVERTERS IN CCM
Vˆr
Vin
dc-dc
converter
topology
Vo
vr
0
controller
Vo , ref
d Ts
t
Ts
I vp
ivp
vc (t )
I cp
icp
vvp
1
q (t )
0
t
(b)
vc (t )
Figure 3-19 Regulation of output by PWM.
d (t ) =
vr (t )
© Copyright Ned Mohan 2007
89
q
Vo
1: d (t )
Vin
(a)
(b)
vc (t )
^
Vr
(c)
Vcp = DVvp
vcp (t ) = d (t ) vvp (t )
I vp = D I o
ivp (t ) = d (t ) icp (t )
© Copyright Ned Mohan 2007
90
Vin
vo
Vo
q
p
iL
vo
1: d (t )
1
A
A
q
⇓
iL
(b) Vin
iL
iL
vo
vcp
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Avg_CCM.sch
Average dynamic models of three converters
vL
vvp
Vcp
1: D
q (t )
r
(a) Vin
Vvp
Figure 3-20 Average dynamic model of a switching power-pole.
vc ( t )
Vˆ
iL
icp
vcp
(a)
ivp
⇓
⇓
iL
Vin
Vin
p
1: (1 − d (t ))
vo
1: d (t )
Figure 3-21 Average dynamic models: Buck (left), Boost (middle) and Buck-Boost (right).
© Copyright Ned Mohan 2007
91
© Copyright Ned Mohan 2007
92
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Switching_LoadTransient.sch
Simulation Results
40
20
0
-20
-40
0s
I(L1)
0.5ms
1.0ms
V(L1:1,L1:2)
1.5ms
2.0ms
2.5ms
3.0ms
3.5ms
4.0ms
4.5ms
5.0ms
Time
© Copyright Ned Mohan 2007
93
Buck
Vin
Vin
q
q − = (1 − q )
(a)
Boost
q =1
iL
q=0
q
q−
(b) iL = positive
Buck Boost
q − = 0( q = 1)
Vin
Vin
q − = 1( q = 0)
q
q =1
iL
q
q−
q − = (1 − q )
(a)
(c) iL = negative
Figure 3-23
Figure 3-22 Bi-directional power flow through a switching power-pole.
© Copyright Ned Mohan 2007
94
Average dynamic model of the switching power-pole with
bi-directional power flow
BI-DIRECTIONAL SWITCHING POWER-POLE
Buck Boost
© Copyright Ned Mohan 2007
95
q
(b)
iL
iL
Vin
1: d
(c)
Average dynamic model of the switching power-pole with bi-directional power
flow.
© Copyright Ned Mohan 2007
96
Critical Inductor Currents
and Load Resistances
DISCONTINUOUS-CONDUCTION MODE (DCM)
iL1
iL ,cri
iL
I L ,crit ,Buck =
iL 2
0
I L1
IL2
I L ,crit
Vin
D (1 − D )
2 Lf s
I L ,crit ,Boost = I L ,crit ,Buck -Boost =
t
Rcrit , Boost
Rcrit , Buck − Boost
© Copyright Ned Mohan 2007
97
© Copyright Ned Mohan 2007
Buck converter in DCM
Vin
0
t
Ts
IˆL
iL
0
Doff ,1
D
1
(a)
Doff ,2
t
Ts
98
Boost Converters in DCM
Vo
Vin
Vo
2 Lf s
(1 − D )
2 Lf s
=
D (1 − D ) 2
2 Lf s
=
(1 − D ) 2
Rcrit , Buck =
Figure 3-24 Inductor current at various loads; duty-ratio is kept constant.
vA
Vin
D
2 Lf s
vA
1
D
Vo
t
Ts
0
IL
0
DCM
I L,crit
IˆL
iL
Vo
Vin
Vin
1
CCM
0
(b)
Doff ,1
D
Doff ,2
1
Figure 3-25 Buck converter in DCM.
1
1− D
(a)
t
Ts
0
DCM
I L ,crit
CCM
IL
(b)
Figure 3-26 Boost converter in DCM.
© Copyright Ned Mohan 2007
99
© Copyright Ned Mohan 2007
100
Table 3-2 vk and ik
Buck-Boost converter in DCM
vA
Vin + Vo
Vo
Vin
Vo
0
t
Ts
IˆL
iL
0
Doff ,1
D
1
Doff ,2
(a)
t
Ts
Converter
vk
ik
Buck

2 Lf s iL 
1 −
 vo
 (Vin − vo )d 
d2
(Vin − v0 ) − diL
2 Lf s
Boost
 2 Lf s iL 
1 −
 (Vin − v0 )
Vin d 

d2
Vin − diL
2 Lf s
Buck-Boost
 2 Lf s iL 
1 −
 vo
Vin d 

d2
Vin − diL
2 Lf s
D
1− D
vk
ivp
0
DCM
CCM
I L, crit
icp
IL
(b)
vvp
Figure 3-27 Buck-Boost converter in DCM.
vcp
ik
icp
ivp
vk
vcp
ik
1: d (t )
vvp
(1 − d ) :1
(a) Buck and Buck-Boost
(b) Boost
Figure 3-28 Average representation of a switching power-pole valid in CCM and DCM.
© Copyright Ned Mohan 2007
101
© Copyright Ned Mohan 2007
102
OBJECTIVES OF FEEDBACK CONTROL
Chapter 4
4-1
Designing Feedback Controllers in Switch-Mode DC Power
Supplies
Vin
Objectives of Feedback Control
4-2
4-3
4-4
4-5
4-6
Review of the Linear Control Theory
Linearization of Various Transfer Function Blocks
Feedback Controller Design in Voltage-Mode Control
Peak-Current Mode Control
Feedback Controller Design in DCM
References
Problems
Appendix 4A Bode Plots of Transfer Functions
Appendix 4B Transfer Functions in CCM
Appendix 4C Derivation of Controller Transfer Functions
DC-DC
Converter
Vo
Controller
Vo*
Figure 4-1 Regulated dc power supply.
• zero steady state error
• fast response
• low overshoot
• low noise susceptibility.
© Copyright Ned Mohan 2007
103
© Copyright Ned Mohan 2007
104
REVIEW OF LINEAR CONTROL THEORY
k FBVo* +
The steps in designing the feedback controller:
∑
Pulse Width
Modulation
vc
Controller
−
Power Stage
and Load
d
vo
PWM-IC
• Linearize the system for small changes around the dc steady state operating point
k FB
• Design the feedback controller using linear control theory
Figure 4-2 Feedback control.
• Confirm and evaluate the system response by simulations for large disturbances
vo (t ) = Vo + vo (t )
d (t ) = D + d (t )
Small signal representation:
vc (t ) = Vc + vc (t )
k FB vo* ( s ) = 0+
∑
A
vc ( s )
Controller
PulseWidth
Modulator
−
GC ( s )
B
d ( s )
Power Stage
+
Output Filter
GPWM ( s )
vo ( s )
GPS ( s )
k FB
Figure 4-3 Small signal control system representation.
© Copyright Ned Mohan 2007
105
© Copyright Ned Mohan 2007
LINEARIZATION OF VARIOUS
TRANSFER FUNCTION BLOCKS
Loop Transfer Function:
o
Loop Gain Phase ()
Loop Gain Magnitude (dB)
GL ( s ) = GC ( s ) GPWM ( s )GPS ( s ) k FB
Linearizing the PWM Controller IC
Vˆr
vc
50
q (t )
f
fcc
0
0
vr
Gain Margin
(a)
-50
-100 0
10
10
1
10
2
10
3
10
vc ( s )
4
-90
-270
10
1
2
10
Frequency (Hz)
10
3
10
Phase Margin:
fc
− ( −1800 ) = φL
fc
0
t
Ts
(b)
Figure 4-5 PWM waveforms.
4
Figure 4-4 Definitions of crossover frequency, gain margin and phase margin.
φPM = φL
t
1
dTs
(c)
-180
vc (t )
vr
d ( s )
PWM IC
Phase Margin
0
q (t )
1
Vˆr
0
10
© Copyright Ned Mohan 2007
106
+ 1800
107
d (t ) =
vc ( t )
Vˆr
vc (t ) = Vc + vc (t )
d (t ) =
Vc (t ) vc (t )
+
Vˆr
Vˆr
N
N
GPWM ( s ) =
© Copyright Ned Mohan 2007D
d ( t )
d ( s ) 1
=
vc ( s ) Vˆr
108
Linearizing the Power Stage of DC-DC
Converters in CCM
Example 4-1 In PWM-ICs, there is usually a dc voltage offset in the ramp voltage,
and instead of as shown in Fig. 4-5b, a typical Valley-to-Peak value of the ramp signal is
defined. In the PWM-IC UC3824, this valley-to-peak value is 1.8 V. Calculate the
linearized transfer function associated with this PWM-IC.
vvp (t )
Solution
icp (t )
ivp (t )
d (t ) vcp (t )
1
vvp (t )
The dc offset in the ramp signal does not change its small signal transfer
function. Hence, the peak-to-valley voltage can be treated as Vˆr . Using Eq. 4-7
GPWM ( s ) =
1
1
=
=0.556
Vˆr 1.8
dV
vp
ivp (t )
1
dI
cp
(a )
D
icp (t )
vcp (t )
(b)
Figure 4-6 Linearizing the switching power-pole.
(4-8)
d (t ) = D + d (t )
vvp (t ) = Vvp + vvp (t )
vcp (t ) = Vcp + vcp (t )
ivp (t ) = I vp + ivp (t )
icp (t ) = I cp + icp (t )
© Copyright Ned Mohan 2007
109
iL
Vin
+
vvp
−
dV
in
+
vcp
r
−
−
1: d (t )
iL
+
−
+
vvp
−
−
(1 − d (t )) :1
−
Le
+
vo
veq
−
Buck
dV
o
dI
L
+
vo
vo Vin
=
d LC
−
(1 − D ) :1
ivp
iL
+
vvp
+
vcp
−
1: d (t )
r
−
(a)
1-1.1.1.1.1.1.1.1
© Copyright Ned Mohan 2007
+
Vin
d (Vin + Vo ) iL
−
+
vo
−
dI
L
Buck-Boost
r
R
vo
−
Le = L (Buck)
L
(Boost and Buck-Boost)
Le =
(1 − D ) 2
Figure 4-8 Small signal equivalent circuit for Buck, Boost and Buck-Boost converters.
vin = 0
Boost
+
1
sC
+
−
1: D
iL
vo
r
iL
vin = 0 dI
L
+
+
vcp
Vin
−
+
vo
110
Small signal equivalent circuit for Buck, Boost
and Buck-Boost converters
Linearizing single-switch converters
ivp
+
© Copyright Ned Mohan 2007
vin = 0
1 + srC
r 1
 1
s + s
+ +
RC
L

 LC
vo
Vin 
L 
=
1− s e 
2 
R
d (1 − D ) 
+
vo
−
1: D
(b)
1 + srC
 2
 1
r  1 
+ +
LeC  s + s 

 RC Le  LeC 

vo
Vin 
DL 
1− s e 
=
2 
R 
d (1 − D ) 
Figure 4-7 Linearizing single-switch converters in CCM.
111
(Buck)
2
© Copyright Ned Mohan 2007
1 + srC

 1
r  1 
LeC  s 2 + s 
+ +

RC
L
LeC 
e 


(Boost)
(Buck-Boost)
112
PSpice Modeling: C:\FirstCourse_PE_Book07\buck_conv_avg.sch
Using Computer Simulation to Obtain
the transfer function Bode Plots
Example 4-2 A Buck converter has the following parameters and is operating in
CCM: L = 100 µ H , C = 697 µ F , r = 0.1Ω , f s = 100 kHz , Vin = 30V , and Po = 36W .
The duty-ratio D is adjusted to regulate the output voltage Vo = 12V . Obtain both the
gain and the phase of the power stage GPS ( s ) for the frequencies ranging from 1 Hz to
100 kHz.
Ideal Transformer
duty-ratio D
d
Figure 4-9 PSpice Circuit model for a Buck converter.
© Copyright Ned Mohan 2007
113
© Copyright Ned Mohan 2007
114
Simulation Results
40
40
24.66dB
20
GPS ( s ) dB
0
0
SEL>>
-20
.
DB(V(V_out))
0d
SEL>>
-40
DB(V(V_out))
-0d
-50d
∠GPS ( s )
-100d
-50d
-150d
30Hz
P(V(V_out))
-100d
−1380
100Hz
300Hz
1.0KHz
3.0KHz
10KHz
30KHz
Frequency
-150d
1.0Hz
3.0Hz
P(V(V_out))
10Hz
30Hz
100Hz
300Hz
1.0KHz
3.0KHz
10KHz
30KHz
Figure 4-10 The gain and the phase of the power stage
100KHz
Frequency
© Copyright Ned Mohan 2007
115
© Copyright Ned Mohan 2007
116
FEEDBACK CONTROLLER DESIGN IN
VOLTAGE-MODE CONTROL
Gc ( s ) =
(1 + s / ωz )
kc
s
2
(1 + s / ω )
2
p
Example 4-3 Design the feedback controller for the Buck converter described in
Example 4-2. The PWM-IC is as described in Example 4-1. The output voltage-sensing
network in the feedback path has a gain k FB = 0.2 . The steady state error is required to
GC ( s )
GC ( s ) dB
be zero and the phase margin of the loop transfer function should be 600 at as high a
crossover frequency as possible.
50
1. The crossover frequency f c of the open-loop gain is as high as possible to result
in a fast response of the closed-loop system.
2. The phase angle of the open-loop transfer function has the specified phase
0
φboost
∠GC ( s )
-50
margin, typically 600 at the crossover frequency so that the response in the
closed-loop system settles quickly without oscillations.
0
−90-100
10Hz
30Hz
P(V(v_out)) -90
100Hz
3. The phase angle of the open-loop transfer function should not drop below −1800
at frequencies below the crossover frequency.
© Copyright Ned Mohan 2007
fc
300Hz
1.0KHz
fz
f
c
Frequency
3.0KHz
fp
10KHz
30KHz
100KHz
Figure 4-11 Bode plot of GC ( s ) in Eq. 4-18.
117
© Copyright Ned Mohan 2007
118
Step 2: Calculate the needed Phase Boost. The desired phase margin is specified as φ PM = 600 .
Step 1: Choose the Crossover Frequency. Choose f c to be slightly beyond the L-C
resonance frequency 1/(2π LC ) , which in this example is approximately 600 Hz.
Therefore, we will choose f c = 1 kHz . This ensures that the phase angle of the loop
remains greater than −180 at all frequencies.
0
The required phase boost φboost at the crossover frequency is calculated as follows, noting that
GPWM and k FB produce zero phase shift:
∠GL ( s )
fc
= ∠GPS ( s )
∠GL ( s )
fc
∠GC ( s )
fc
+ ∠GC ( s )
(from Eq. 4-2)
(4-19)
= −180o + φ PM
(from Eq. 4-3)
(4-20)
= −90o + φboost
(from Fig. 4-11)
(4-21)
fc
fc
Substituting Eqs. 4-20 and 4-21 into Eq. 4-19,
φboost = −90o + φ PM − ∠GPS ( s ) f
In Fig. 4-10, ∠GPS ( s )
c
(4-22)
−138 , substituting which in Eq. 4-22 yields the required phase boost
0
fc
φboost = 108 .
o
© Copyright Ned Mohan 2007
119
© Copyright Ned Mohan 2007
120
vo* ( s ) = 0 +
∑
A
vc ( s)
Controller
−
B
GC ( s )
GPWM ( s )
Step 3: Calculate the Controller Gain at the Crossover Frequency. From Eq. 4-2 at the
fc
= GC ( s )
fc
× GPWM ( s )
In Fig. 4-10, at f c = 1 kHz , GPS ( s )
fc
f c =1 kHz
× GPS ( s )
fc
× k FB = 1
the gain of the PWM block calculated in Example 4-1,
GC ( s ) f × 0.556
N × 17.1
N × 0.2
N =1
c
GPWM ( s )
fc
GPS ( s )
k
Gc ( s ) = c
s
(1 + s / ωz )
GPS ( s )
2
p
K boost =
(4-24)
ωp
ωz
φ 

K boost = tan  45o + boost 
4 

k FB
fc
fz =
fc
vo ( s )
2
(1 + s / ω )
or
GC ( s )
Power Stage
+
Output Filter
Figure 4-3 Small signal control system representation.
(4-23)
= 24.66 dB = 17.1 . Therefore in Eq. 4-23, using
d ( s )
k FB
crossover frequency f c
GL ( s )
PulseWidth
Modulator
= 0.5263
(4-25)
fc
K boost
k c = GC ( s )
© Copyright Ned Mohan 2007
121
f p = K boost f c
ωz
fc
K boost
© Copyright Ned Mohan 2007
122
Implementation of the controller by an op-amp
C2
R3
k
Gc ( s ) = c
s
(1 + s / ωz )
2
(1 + s / ω )
R2
C1
vo
In this numerical example with f c = 1 kHz , φboost = 108o , and GC ( s )
R1
2
p
C3
= 0.5263 , we can
calculate K boost = 3.078 in Eq. 4-27. Using Eqs. 4-27 through 4-30, f z = 324.9 Hz ,
f p = 3078 Hz , and kc = 349.1 . For the op-amp implementation, we will select
vc
vo*
fc
Figure 4-12 Implementation of the controller by an op-amp.
R1 = 100 k Ω . From Eq. 4-30, C2 = 3.0 nF , C1 = 25.6 nF , R2 = 19.1 k Ω , R3 = 11.8 k Ω ,
and C3 = 4.4 nF .
C2 = ωz /( kcω p R1 )
C1 = C2 (ω p / ωz − 1)
R2 = 1/(ωz C1 )
R3 = R1 /(ω p / ωz − 1)
C3 = 1/(ω p R3 )
© Copyright Ned Mohan 2007
123
© Copyright Ned Mohan 2007
124
PSpice Modeling: C:\FirstCourse_PE_Book07\buck_conv_avg_fb_ctrl_op.sch
PSpice model of the Buck converter with voltage-mode control
Figure 4-13 PSpice average model of the Buck converter with voltage-mode control.
12.2V
12.0V
11.8V
11.6V
0s
5ms
10ms
V(V_out)
Time
Figure 4-14 Response to a step-change in load.
© Copyright Ned Mohan 2007
125
© Copyright Ned Mohan 2007
126
PEAK-CURRENT MODE CONTROL
Simulation Results
12.1V
•
Peak-Current-Mode Control, and
•
Average-Current-Mode Control.
ivp
+
12.0V
Vin
iL
vvp
11.9V
−
+
+
vcp
vo
−
−
11.8V
Q
11.7V
0s
0.5ms
V(V_out)
1.0ms
1.5ms
2.0ms
2.5ms
3.0ms
3.5ms
4.0ms
4.5ms
5.0ms
5.5ms
6.0ms
S
Clock
R
−
+
Flip-flop
Time
Slope
Compensation
iL*
ic
Controller
vo*
Comparator
Figure 4-15 Peak current mode control.
© Copyright Ned Mohan 2007
127
© Copyright Ned Mohan 2007
128
Example 4-4 In this example, we will design a peak-current-mode controller for a
Buck-Boost converter that has the following parameters and operating conditions:
L = 100 µ H , C = 697 µ F , r = 0.01Ω , f s = 100 kHz , Vin = 30 V .
slope compensation
ic
iL*
Vo = 12 V . The phase margin required for the voltage loop is 600 . Assume that in the
iL
voltage feedback network, k FB = 1 .
0
Clock
t
Ts =
vo* ( s) = 0
+
∑
−
The output power
Po = 18 W in CCM and the duty-ratio D is adjusted to regulate the output voltage
iL* ( s )
Controller
t
1
fs
(a )
Peak Current
Mode
Controller
iL ( s )
Power Stage
vo ( s )
≈1
GC ( s )
(b)
Figure 4-16 Peak-current-mode control with slope compensation.
© Copyright Ned Mohan 2007
129
Figure 4-17 PSpice circuit for the Buck-Boost converter.
© Copyright Ned Mohan 2007
130
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Freq_Analysis.sch
20
0
GPS ( s ) dB
−29.33dB
-20
-40
DB(V(V_out)/I(L1))
0d
∠GPS ( s ) |deg
-50d
−900
SEL>>
-100d
1.0Hz
3.0Hz
P(V(V_out)/ I(L1))
10Hz
30Hz
.
100Hz
300Hz
1.0KHz
Frequency
f c = 5 kHz
3.0KHz
10KHz
30KHz
100KHz
Figure 4-18 Bode plot of vo / iL .
As shown in Fig. 4-18, the phase angle of the power-stage transfer function levels off at
approximately −900 at ~1kHz . The crossover frequency is chosen to be f c = 5 kHz , at
which in Fig. 4-18, ∠GPS ( s )
fc
−900 .
As explained in the Appendix on the
accompanying CD, the power-stage transfer function vo ( s ) / iL ( s ) of Buck-Boost
converters contains a right-half-plane zero in CCM. The crossover frequency is chosen
well below the frequency of the right-half-plane zero for reasons discussed in the
Appendix.
© Copyright Ned Mohan 2007
131
© Copyright Ned Mohan 2007
132
Simulation Results
Gc ( s ) =
kc
s
20
φ 

K boost = tan  45o + boost 
2 

fc
fz =
f p = K boost f c
K boost
(1 + s / ωz )
(1 + s / ω )
p
0
k c = ω z GC ( s )
fc
-20
At the crossover frequency, as shown in Fig. 4-18, the power stage transfer function has a
SEL>>
-40
gain GPS ( s )
DB(V(V_out)/I(L1))
0d
fc
= −29.33 dB . Therefore, at the crossover frequency, by definition, in Fig.
4-16b
-50d
GC ( s )
fc
GC ( s )
fc
× GPS ( s )
fc
=1
(4-37)
Hence,
-100d
1.0Hz
3.0Hz
P(V(V_out)/I(L1))
10Hz
30Hz
100Hz
300Hz
1.0KHz
3.0KHz
10KHz
30KHz
100KHz
Frequency
= 29.33 dB = 29.27
Using the equations above for
(4-38)
f c = 5 kHz , φboost 600 , and
GC ( s )
fc
= 29.27 ,
K boost = 3.732 in Eq. 4-32. Therefore, the parameters in the controller transfer function
of Eq. 4-31 are calculated as f z = 1340 Hz , f p = 18660 Hz , and kc = 246.4 × 103 .
© Copyright Ned Mohan 2007
133
© Copyright Ned Mohan 2007
134
C2
R2
vo
C1
R1
vo*
vc
Figure 4-19 Implementation of controller in Eq. 4-32 by an op-amp circuit.
R1 = 10 k Ω
C2 =
ωz
= 30 pF
ω p R1kc
C1 = C2 (ω p / ωz − 1) = 380 pF
R2 = 1/(ωz C1 ) = 315 k Ω
© Copyright Ned Mohan 2007
Figure 4-20 PSpice simulation diagram of the peak-current-mode control.
135
© Copyright Ned Mohan 2007
136
PSpice Modeling: C:\FirstCourse_PE_Book07\bboost_conv_curr_mode_ctrl_opamp.sch
12.04
vo (t)
12.00
vo (t)
11.96
11.92
2.50ms
2.75ms
AVGX(V(Vo),10u)
3.00ms
V(Vo)
Time
3.25ms
3.50ms
Figure 4-21 Peak current mode control: Output voltage waveform.
© Copyright Ned Mohan 2007
137
Simulation Results
© Copyright Ned Mohan 2007
138
FEEDBACK CONTROLLER DESIGN IN DCM
12.02V
12.00V
11.98V
11.96V
11.94V
11.92V
1.40ms
V(Vo)
1.45ms
1.50ms
1.55ms
1.60ms
1.65ms
1.70ms
1.75ms
1.80ms
1.85ms
1.90ms
Time
© Copyright Ned Mohan 2007
139
© Copyright Ned Mohan 2007
140
Simulation Results
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_CCM_DCM_Freq_Analysis.sch
80
40
CCM
DCM
0
SEL>>
-40
DB(V(V_out))
0d
CCM
DCM
-100d
-200d
1.0Hz
3.0Hz
P(V(V_out))
10Hz
30Hz
100Hz
300Hz
1.0KHz
3.0KHz
10KHz
30KHz
100KHz
Frequency
© Copyright Ned Mohan 2007
141
20 log10 T ( s )
0
142
4A-2 A Zero in a Transfer Function
APPENDIX 4A BODE PLOTS OF TRANSFER FUNCTIONS
WITH POLES AND ZEROS
T ( s ) = 1 + s / ωz
1
T (s) =
1 + s / ωp
4A-1 A Pole in a Transfer Function
© Copyright Ned Mohan 2007
20 log10 T ( s )
20
10
0
ωp
10
ωp
−10
ωz
10
10ω p
ωz
10ω z
log10 ω
log10 ω
−20
90
∠T ( s ) 45
0
0
∠T ( s )
−45
Fig. 4A-2 Gain and phase plots of a zero.
−90
Fig. 4A-1 Gain and phase plots of a pole.
© Copyright Ned Mohan 2007
143
© Copyright Ned Mohan 2007
144
4A-4 A Double Pole in a Transfer Function
4A-3 A Right-Hand-Plane (RHP) Zero in a Transfer Function
T ( s) = 1 −
s
T ( s) =
ωz
20 log10 T ( s )
2
ζ = 0 .0 5
ζ = 0 .2 5
ζ = 0 .5
0
10
ωz
10
ωz
10ω z
ζ
ζ
-2 0
log10 ω
= 0 .8 0
= 1 .0 0
-4 0
-6 0
-8 0
1 0
0
∠T ( s )
 s 
1+αs +  
 ωo 
2 0
20
0
1
1
1 0
2
1 0
3
1 0
4
1 0
5
0
ζ
−45
= 0 .0 5
ζ
ζ
-9 0
−90
ζ
= 0 .8 0
ζ
= 0 .2 5
= 0 .5
= 1 .0 0
-1 8 0
1 0
Fig. 4A-3 Gain and phase plots of a right-hand side zero.
© Copyright Ned Mohan 2007
Chapter 5
5-1
5-2
5-3
5-4
5-5
5-6
145
© Copyright Ned Mohan 2007
1
1 0
2
1 0
3
1 0
4
1 0
5
Fig.4A-4 Gain and phase plots of a double-pole.
146
Rectification of Utility Input Using Diode Rectifiers
Converter
Introduction
Distortion and Power Factor
Classifying the “Front-End” of Power Electronic Systems
Diode-Rectifier Bridge “Front-Ends”
Means to Avoid Transient Inrush Currents at Starting
Front-Ends with Bi-Directional Power Flow
References
Problems
© Copyright Ned Mohan 2007
Source
Load
Controller
Figure 5-1 Block diagram of power electronic systems.
147
© Copyright Ned Mohan 2007
148
Linear and
Nonlinear Loads
Linear Load
Non-linear Loads
vs
is
Vs
+
0
φ
−
(b)
0
t
φ1 / ω
t
( b)
T1
Is
(a )
Figure 5-3 Current drawn by power electronics equipment with diode-bridge front-end.
(a)
Figure 5-2 Voltage and current phasors in simple R-L circuit.
Total Harmonic Distortion: %THD = 100 x
P = Vs I s cos φ
Displacement Power Factor: DPF = cos φ1
P
= cos φ
Vs I s
P
Is =
Vs ⋅ PF
PF =
© Copyright Ned Mohan 2007
idistortion (= is − is1 )
is1
is
vs
Nonlinear
Loads
PF =
149
‰
I s1
( DPF ) =
Is
I distortion
I s1
DPF
1 + THD 2
Nonlinear loads reduce power factor
© Copyright Ned Mohan 2007
150
Obtaining Harmonic Components by Fourier Analysis
∞
∞
h =1
h =1
g (t ) = G0 + ∑ g h (t ) = G0 + ∑{ah cos( hωt ) + bh sin( hωt )}
1
G0 =
2π
ah =
bh =
1
π
1
π
Gh = Gh ∠φh
∫
2π
∫
2π
0
∫
2π
0
is
(a )
−I
g (t ) ⋅ d (ωt )
t
0
T1
is1
g (t ) cos( hωt )d (ωt ) h = 1,2,..., ∞
(b)
g (t )sin( hωt )d (ωt ) h = 1,2,..., ∞
(c)
4I / π
t
0
idistortion
0
I
I
t
0
−I
Gh =
ah2 + bh2
2
tan φh =
−bh
ah
Figure 5-4 Example 5-1.
∞
G = G02 + ∑ Gh2
© Copyright Ned Mohan 2007
h =1
151
© Copyright Ned Mohan 2007
152
Harmonic Guidelines
Harmonic Currents Lower Power Factor
Total
Harmonic
Odd Harmonic Order h
1
I SC / I1
0.9
11 ≤ h ≤ 17
17 ≤ h ≤ 23
23 ≤ h ≤ 35
35 ≤ h
Distortion(%)
5.0
< 20
4.0
2.0
1.5
0.6
0.3
0.8
20 − 50
7.0
3.5
2.5
1.0
0.5
8.0
0.7
50 − 100
10.0
4. 5
4 .0
1 .5
0 .7
12.0
PF
DPF 0.6
0.5
‰
‰
‰
0.4
0
50
100
150
200
250
300
%THD
‰
h < 11
Ratio of actual power factor to displacement power factor decreases with
increasing THD
© Copyright Ned Mohan 2007
100 − 1000
12.0
5. 5
5. 0
2.0
1 .0
15.0
> 1000
15.0
7 .0
6 .0
2. 5
1 .4
20.0
IEEE – 519
Limits on allowable harmonic currents drawn by loads of various relative magnitudes
Relative magnitude of load currents is based on Short Circuit Ratio (SCR)
SCR =
153
I sc
I s1
© Copyright Ned Mohan 2007
154
Types of Electric Drive Front-Ends
Short-Circuit Current: I sc
Zs
Zs
+
Where Isc is the short circuit current and Is1 is the fundamental
current of the load
I sc
+
Vs
Vs
−
−
(a)
(a )
( b)
Figure 5-7 Front-end of power electronics equipment.
(b)
Figure 5-6 (a) Utility supply; (b) short circuit current.
‰
‰
‰
© Copyright Ned Mohan 2007
155
© Copyright Ned Mohan 2007
(c)
Diode-bridge rectifiers
Switch-mode converters
Thyristor converter
156
Single-Phase, DiodeBridge Rectifier
idr
is
+
vs (t )
1
Ls
id
is
+
vd
−
1
+
3
Rs
Full-bridge diode rectifier with resistive load
Cd
−
Req
vs (t )
3
2
−
2
4
is
idr
+
vd
1
idr
+
vs
−
−
3
2
4
( b)
(a )
+
vd
vs
vd = v s
is , idr
idr
Rd
−
0
ωt
4
Figure 5-8 Full-bridge diode rectifier.
(a )
(b)
Fig. 5-9 Full-bridge diode rectifier with resistive load.
‰
Power levels up to several kW
‰
Current drawn from utility in short pulses
© Copyright Ned Mohan 2007
157
© Copyright Ned Mohan 2007
158
Peak-Charging Circuit
vd
Full-bridge diode rectifier with an inductive load where idr (t ) I dr (dc).
idr
is
1
+
vs
−
vs
idr
3
2
4
(a )
+
vd
−
is ( = I dr )
Ld
Rd
Rd
0
vd = vs
0
is ( = − I dr )
t1
idr
is
t2 t3
vs
ωt
is
ωt
Figure 5-11 Waveforms for the full-bridge diode rectifier with a dc-bus capacitor.
(b)
Fig. 5-10 Full-bridge diode rectifier with an inductive load where idr (t ) I dr (dc).
‰
© Copyright Ned Mohan 2007
159
© Copyright Ned Mohan 2007
Current pulses widen as Ls is increased
160
PSpice Modeling: C:\FirstCourse_PE_Book07\DBrect1ph.sch
200
vd
100
vs
is
0
-100
-200
115ms
V(Ls:1)
120ms
I(Ls)*3
125ms
V(R1:2,C1:2)
130ms
135ms
140ms
145ms
150ms
Time
Figure 5-12 Single-phase diode-bridge rectification for two values of Ls .
© Copyright Ned Mohan 2007
161
© Copyright Ned Mohan 2007
Simulation Results
162
Three-Phase, Diode- Bridge Rectifier
200
idr
100
−
−
0
−
va
vb
vc
+
Ls
+
Ls
+
Ls
1
3
−
5
vd
+
−
Cd
Req
−
−
4
6
(a)
va
vb
vc
+
Ls
1
ia
+
Ls
+
Ls
3
5
idr
P
4
6
2
2
N
(b)
-100
Figure 5-13 Three-phase diode bridge rectifier.
-200
0s
5ms
V(Ls:1)
10ms
I(Ls)*3
15ms
V(R1:2,C1:2)
20ms
25ms
30ms
35ms
40ms
45ms
50ms
Time
© Copyright Ned Mohan 2007
163
© Copyright Ned Mohan 2007
164
Voltage and Current Without Cd
va
vb
vc
vP
0
ia
t
120 o
60 o
ωt
ib
vN
0
(a)
vd
0
PSpice Modeling: C:\FirstCourse_PE_Book07\DBrect3_ph.sch
2VLL
ωt
ic
Vd
0
t
0
ωt
(b)
(c)
Figure 5-14 Waveforms in a three-phase rectifier (a constant idr ).
‰
vP follows whichever phase voltage is most positive at any moment
‰
vN follows whichever phase voltage is most negative at any moment
‰
Without Cd, phase currents flow for a full 120° duration
© Copyright Ned Mohan 2007
165
© Copyright Ned Mohan 2007
166
Simulation Results
200
vs
300
100
is
0
200
-100
-200
65ms
I(L1)*3
100
70ms
75ms
V(L1:1)
80ms
85ms
90ms
95ms
85ms
90ms
95ms
(a )
Time
200
vs
0
100
is
0
-100
-100
-200
60ms
I(L1)*5
-200
65ms
I(L1)*3
75ms
80ms
85ms
90ms
95ms
100ms
75ms
80ms
( b)
Figure 5-15 Effect of Ls variation (a) Ls = 0.1mH ; (b) Ls = 3 mH .
Time
© Copyright Ned Mohan 2007
70ms
V(L1:1)
Time
65ms
70ms
V(L1:1) V(Vd,R7:2)
167
© Copyright Ned Mohan 2007
168
Avoiding Large Inrush Currents
Chapter 6
(a )
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
Introduction
Single-Phase PFCs
Control of PFCs
Designing the Inner Average-Current-Control Loop
Designing the Outer Voltage Loop
Example of Single-Phase PFC Systems
Simulation Results
Feedforward of the Input Voltage
References
Problems
Appendix 6A Proving that Iˆ / Iˆ = 1/ 2
( b)
Figure 5-16 Means to avoid inrush current.
‰
Resistor limits inrush current at startup
‰
Resistor switched out during operation
Power-Factor-Correction (PFC) Circuits and Designing the
Feedback Controller
s ,3
Appendix 6B
© Copyright Ned Mohan 2007
169
L ,2
Deriving vd ( s ) / IˆL ~ ( s )
© Copyright Ned Mohan 2007
170
Implementation of PFC
Vd
iL (t )
+
† Use a boost dc-dc converter to shape the rectified current
id (t )
Ld
Cd
vs
id
iL
+
vs
vs
q (t )
−
vs
+
+ Ld
is
Vd
R
Cd
−
Vd >Vˆs
iL
−
0
is
d ( t ) =1 −
(b)
(a)
Figure 6-1 PFC circuit and waveforms.
+
id (t )
Ld
Cd
vs
−
+
vd
r
(1 − d )
1
(a)
R
0
1
−
0
+
−
vs
IˆL
iL
t
+
t1
(b)
∴ d (t )= 1 −
a f
Vs sin ω t
Vo
Figure 6-2 Average model and waveforms.
© Copyright Ned Mohan 2007
r
(1 − d )
1
171
vd 2 = −
R
0
1
−
0
+
−
IˆL
iL
t
+
t1
d (t )
(b)
t
Figure 6-2 Average model and waveforms.
id
Vo
Id
1
Vo
=
vs 1 − d ( t )
d (t )
t
Vˆs sin (ω t )
+
1 Vˆs ˆ 1 Vˆs ˆ
id =
IL −
I L cos 2ωt
2 Vd
2 Vd
Vd
iL (t )
vd
(a)
IˆL
−
+
vs
id 2 ( t )
id 2
vd
Id
−
Figure 6-3 Current division in the output stage.
 Iˆ Vˆ 
1 IˆL Vˆs
cos 2ωt ⋅ d (ωt ) = −  L s  sin 2ωt
∫
ω C 2 Vd
ω CVd 
4
Iˆ Vˆ
Vˆd 2 = L s
4ω C Vd
© Copyright Ned Mohan 2007
Vˆd 2
172
Example 6-1
Calculation of Vˆd 2
Derive id (t ) in Eq. 6-5 by equating input and output powers.
Solution Assume that vs =Vˆs sin ωt and is = Iˆs sin ωt .
Therefore, the input power
vd 2 ( t ) =
1 1
Pin (t ) = vs is = Vˆs Iˆs sin 2 ωt . Recognizing that sin 2 ωt = − cos 2ωt , the input power is
2 2
1
1
Pin (t ) = Vˆs Iˆs sin 2 ωt = Vˆs Iˆs − Vˆs Iˆs cos 2ωt . The output power po (t ) = Vd id . Equating
2
2
+
id 2
1 Vˆs Iˆs 1 Vˆs Iˆs
cos 2ωt
−
2 Vd
2 Vd
Id
id 2 ⋅ d (ωt )
id
pin (t ) = po (t ) ,
id =
1
ωC ∫
(6-6)
Id
vd
−
id 2 ( t )
Figure 6-3 Current division in the output stage.
As Eq. 6-5, Eq. 6-6 shows that the average current to the output stage consists of a dc
component I d and a component id 2 (t ) at the second-harmonic component.
vd 2 = −
 Iˆ Vˆ 
1 IˆL Vˆs
cos 2ωt ⋅ dt = −  L s  sin 2ωt
∫
ω CVd 
C 2 Vd
4
Vˆd 2
© Copyright Ned Mohan 2007
173
© Copyright Ned Mohan 2007
174
CONTROL OF PFCs
Example 6-2
Calculate Vˆd 2 at full-load and the nominal input voltage, for the
sin ω t
parameters and operating values of a PFC given in Table 6-1 on page
6-9. Ignore the capacitor ESR.
Solution
Vd*
Voltage
Controller
IˆL*
Assuming the PFC to be lossless, Vs I s = Po . Therefore, using the values given
iL* (t )
Current Loop
vc (t )
Current
Controller
q(t )
vr
P
in Table 6-1, IˆL = Iˆs = 2 o = 2.946 A . Vˆs = 2 × 120 = 169.7V . Therefore, From Eq.
Vs
6-9, the peak value of the second-harmonic voltage is
Iˆ Vˆ
Vˆd 2 = L s 6V .
4ω C Vd
vd
Power
Stage
iL
Figure 6-4 PFC control loops.
© Copyright Ned Mohan 2007
175
© Copyright Ned Mohan 2007
176
DESIGNING INNER AVERAGE-CURRENT-CONTROL LOOP
iL* (t)
Current
Controller
vc (t)
PWM
IC
d(t) Power
Stage
DESIGNING THE OUTER VOLTAGE LOOP
vd
Vd*
iL
IˆL*
Voltage
Controller
(a)
IˆL
Closed
Current
Loop
Power
Stage
vd
(a)
Current
Controller
iL*(s)+
∑
Gi (s)
vc (s)
PWM
IC
1
Vˆ
r
−
Power
Stage
d(s) Vd
sLd
Voltage
Controller
iL (s)
Gv ( s ) =
(b)
Figure 6-5 PFC current loop.
PWM-IC:
Power-Stage:
d ( s ) 1
=
vc ( s ) Vˆr
iL ( s ) Vd
=
d ( s ) sLd
k 1 + s / ωz
Controller: Gi ( s ) = c
s 1 + s / ωp
φ
phase boost
K boost = tan(45o + boost )
2
f ci
k c = ω z GC ( s )
fz =
f p = K boost f ci
K boost
© Copyright Ned Mohan 2007
(b)
kv
1 + s / ωcv
fc
177
=
s = j (2π ×120)
© Copyright Ned Mohan 2007
250V (dc)
250W
Switching Frequency, f s
100kHz
Output Filter capacitor, C
220 µ F
ESR of the Capacitor, r
100mΩ
Inductor, Ld
1mH
Full-Load Equivalent Resistance, R
250Ω
1
iL ( s )
1 Vˆs
R/2
2 Vd 1 + s ( R / 2)C
vd ( s )
=1
s = j (2π × f cv )
d2
© Copyright Ned Mohan 2007
178
Vˆr = 1
φPM = 600
Gi ( s ) =
60 Hz
Maximum Power Output
i ( s )
Design of the Current Loop
Table 6-1
Parameters and Operating Values
Nominal input ac source voltage, Vs ,rms 120V
Output Voltage, Vd
−
Gv ( s )
IˆL 2
Vˆ
EXAMPLE OF SINGLE-PHASE PFC SYSTEMS
Line frequency, f
+
∑
Power
Stage
Figure 6-6 Voltage control loop.
kv
R/2
1 Vˆs
1 + s / ωcv 2 Vd 1 + s ( R / 2)C
kv
1 + s / ωcv
vd* ( s ) = 0
*
L
Closed
Current
Loop
ωci = 2π × 104
k c 1 + s / ωz
s 1 + s / ωp
phase boost
kc = 4212
ωz = 1.68 × 104 rad / s
ω p = 2.34 × 105 rad / s
179
© Copyright Ned Mohan 2007
180
DESIGNING THE OUTER VOLTAGE LOOP
Gv ( s ) =
Gv ( s ) =
kv
1 + s / ωcv
kv
1 + s / ωcv
C1
In this example at full-load, the plant transfer function given by Eq. 6-15 has a pole at the
frequency of 36.36 rad/s (5.79 Hz). At full-load, Iˆ = 2.946 A , and in Eq. 6-8,
R1
in
L
Vˆd 2 = 6.029V . Based on the previous discussion, the second-harmonic component is
R1
R2
−
R1
out
limited to 1.5 percent of IˆL , such that IˆL 2 = 0.0442 A . Using these values, from Eq. 6-17
+
and 6-18, the parameters in the voltage controller transfer function of Eq. 6-16 are
calculated: kv = 0.0754 , and ωcv = 73.7 rad / s (11.73 Hz).
Figure 6-7 Op-amp circuit to implement transfer function Gv ( s ) .
This transfer function is
realized by an op-amp circuit shown in Fig. 6-7, where
R1 = 100 k Ω
R1 = 100 k Ω
R2 = 7.54 k Ω
R2 = 7.54 k Ω
C1 = 1.8 µ F
© Copyright Ned Mohan 2007
−
+
C1 = 1.8 µ F
181
© Copyright Ned Mohan 2007
PSpice Modeling: C:\FirstCourse_PE_Book07\pfc__Avg_opm.sch
182
Simulation Results
250
200
150
100
50
0
0s
V(R2:2)
20ms
I(L1)*50
40ms
60ms
80ms
100ms
120ms
140ms
160ms
180ms
200ms
Time
© Copyright Ned Mohan 2007
183
© Copyright Ned Mohan 2007
184
FEEDFORWARD OF THE INPUT VOLTAGE
Chapter 7
sin ω t
Vd*
Voltage
Controller
IˆL*
N
D
7-1
7-2
7-3
7-4
7-5
Current Loop
iL* (t )
vc (t )
Current
Controller
Vˆs
Vˆs ,nom
q(t )
vd
Power
Stage
iL
vr
Magnetic Circuit Concepts
Ampere-Turns and Flux
Inductance L
Faraday’s Law: Induced Voltage in a Coil due to Time-Rate of Change of Flux Linkage
Leakage and Magnetizing Inductances
Transformers
References
Problems
Figure 6-10 Feedforward of the input voltage.
© Copyright Ned Mohan 2007
185
186
AMPERE-TURNS AND FLUX
i
INDUCTANCE
λm = N φm = Lm i
φm = φ g = φ
Ag
W
d
i
i
Figure 7-1 Magnetic structure with air gap.
 N
× 
 Am



Hm
N
H m A m + H g A g = Ni
µm
A
A
φ ( m + g ) = Ni
Am µm Ag µo
N
N
ℜm
Am
φm
(a)
× (µm )
Bm
× ( Am )
φm
×(N )
λm
N2
Lm =
Am
µ m Am
(b)
Figure 7-2 Coil Inductance.
ℜg
Ni
φ=
ℜ
ℜ = ℜm + ℜ g
© Copyright Ned Mohan 2007
187
© Copyright Ned Mohan 2007
188
FARADAY’S LAW: INDUCED VOLTAGE IN A COIL
DUE TO TIME-RATE OF CHANGE OF FLUX LINKAGE
Energy Storage due to Magnetic Fields
1
Lm i 2 [ J ]
2
W=
φ (t )
i (t )
w=
+
e (t )
−
1 B2
[ J / m3 ]
2 µ
N
Figure 7-3 Voltage polarity and direction of flux and current.
e( t ) =
d
d
λ (t ) = N φ (t )
dt
dt
φ (t ) = φ (0) +
© Copyright Ned Mohan 2007
189
t
1
e(τ ) ⋅ dτ
N ∫0
© Copyright Ned Mohan 2007
LEAKAGE AND MAGNETIZING INDUCTANCES
190
TRANSFORMERS
φm
i
i
+
+
e
−
e
−
i1
φl
+
Figure 7-4 (a) Magnetic and leakage fluxes; (b) equivalent representation of magnetic and
leakage fluxes.
φm
+
+
Ll
di
dt
−
em (t )
−
Ll
R
+
Ll
e (t )
Lm
+
v(t )
−
+
e(t )
−
i (t )
+
em (t )
e2 = N 2
d φm
dt
e3 = N 3
d φm
dt
d φm e1
e
e
=
= 2 = 3
dt
N1 N 2 N 3
−
−
(a)
(b)
φm =
Figure 7-5 (a) Circuit representation;
(b) leakage inductance separated from the core.
© Copyright Ned Mohan 2007
d φm
dt
(b)
(a)
i (t )
e1 = N1
191
e1
N1
-
i2
φm
i3
N3
e3
N2
+
-
+ e2 -
Figure 7-6 Transformer with three windings.
⇒
φm =
1
1
1
e1dt =
e2 dt =
e3dt
N1 ∫
N2 ∫
N3 ∫
N1i1 + N 2i2 + N 3i3
ℜm
© Copyright Ned Mohan 2007
192
Transformer Equivalent Circuit
Chapter 8
i1
i1
i2
+
+
+
e2
e1
−
×
Lm1
e1
×
im1
×
×
×
+
e3
−
×
(a )
i2
+
e2
−
−
i3
i1′
−
i3
+
e3
−
Switch-Mode DC Power Supplies
8-1
Applications of Switch-Mode DC Power Supplies
8-2
Need for Electrical Isolation
8-3
8-4
8-5
8-6
8-7
8-8
Classification of Transformer-Isolated DC-DC Converters
Flyback Converters
Forward Converters
Full-Bridge Converters
Half-Bridge and Push-Pull Converters
Practical Considerations
References
Problems
(b )
Figure 7-7 Equivalent circuits of transformers: (a) ideal, and (b) actual.
© Copyright Ned Mohan 2007
193
194
SWITCH-MODE DC POWER SUPPLIES
input
rectifier
60Hz
ac
+
dc to HF ac
Vin
−
topology to convert
dc to dc with isolation
CLASSIFICATION
Output
Vo
HF transformer
Feedback
controller
•
Flyback converters derived from Buck-Boost dc-dc converters
•
Forward converter derived from Buck dc-dc converters
•
Full-Bridge and Half-Bridge converters derived from Buck dc-dc converters
Vo*
Figure 8-1 Block diagram of switch-mode dc power supplies.
• NEED FOR ELECTRICAL ISOLATION
© Copyright Ned Mohan 2007
195
© Copyright Ned Mohan 2007
196
FLYBACK CONVERTERS
+
Vin
−
iL
φm (t )
φm (0)
+
Vin
−
iin
0
iin
+
Vo
−
iout
+
Vo
−
(a )
+
iout
Vin
−
iout
N1
N2
∆φ p - p
DTs
Ts
Iˆin
Iin (0)
0
( b)
iin
φˆ
+
Vo
−
Iˆout
0
t
DTs
t
t
Figure 8-3 Flyback converter waveforms.
(c)
∆φ p − p =
Figure 8-2 Buck-Boost and the Flyback converters.
© Copyright Ned Mohan 2007
197
Vin
V
DTs = o (1 − D )Ts
N1
N2
Vo  N 2  D
⇒
=
Vin  N1  1 − D
© Copyright Ned Mohan 2007
198
PSpice Modeling: C:\FirstCourse_PE_Book07\flyback.sch
Example 8-1 In a Flyback converter shown in Fig. 8-2c, Vin = 48V , Vo = 5V ,
N1 / N 2 = 6 , and the magnetizing inductance Lm1 = 150µ H . This converter is operating
in equivalent CCM with a switching frequency f s = 200 kHz and supplying an output
load Po = 30W .
Assuming this converter to be lossless, calculate the waveforms
associated with it.
From Eq. 8-8, the duty-ratio D = 0.385 , where Ts = 5µ s . The average
Solution
currents are I in = 0.625 A and I out = 6 A . In Fig. 8-3, the rise in current during the oninterval DTs can be calculated as
V ( DTs )
Iˆin − I in (0) = in
= 0.616 A .
Lm1
From the waveforms of Fig. 8-3, the average input current can be calculated as follows:
I in =
Iˆin + I in (0)
D = 0.625 A ;
2
Iˆin + I in (0) = 3.247 A
From equations above, in Fig. 8-3, Iˆin = 1.93 A and I in (0) = 1.315 A . The output current
N
N
has a peak value Iˆout = Iˆin 1 = 11.58 A and I out (0) = I in (0) 1 = 7.89 A .
N2
N2
© Copyright Ned Mohan 2007
199
© Copyright Ned Mohan 2007
200
FORWARD CONVERTERS
Simulation Results
12A
10A
D3
+
iL
+
Vin
+
-
Vo
i1
Vin
+
v1
−
-
N2
D2
N3
i3
-
q (t )
8A
N1
q(t )
(a)
iL
D1
+
vA
−
+
Vo
-
(b)
Figure 8-4 Buck and Forward converters.
6A
vA
4A
( N 2 / N1 )Vin
( N 2 / N1 ) DVin
2A
0
0A
450us
I(S1)
455us
I(D1)
460us
465us
470us
475us
480us
485us
490us
495us
201
Ts
t
Figure 8-5 Forward converter operation.
500us
Time
© Copyright Ned Mohan 2007
DTs
N 
Vo =  2  DVin
 N1 
© Copyright Ned Mohan 2007
202
Example 8-2 In a Forward converter shown in Fig. 8-4b, Vin = 48V , Vo = 5V ,
D3
+
iL
+
Vin
+
-
Vo
i1
Vin
+
v1
−
-
N2
N3
i3
-
q (t )
N1
q(t )
(a)
N1 / N 2 = 3.5 , N1 / N 3 = 1 , and the magnetizing inductance Lm1 = 150µ H . This converter
iL
D1
D2
+
vA
−
is operating in equivalent CCM with a switching frequency f s = 200 kHz and supplying
+
an output load Po = 60W .
Vo
-
Assume the filter inductor current iL to be ripple-free.
Assuming this converter to be lossless, calculate the waveforms associated with it.
(b)
Solution
From Eq. 8-9, the duty-ratio D = 0.365 , where Ts = 5µ s . The average
currents are I in = 1.25 A and I out = 12 A . The voltage waveforms are shown in Fig. 8-7,
Figure 8-4 Buck and Forward converters.
where the output current reflected to the primary side is ( N 2 / N1 ) I out = 3.43 A . The peak
of the magnetizing current during the on-interval DTs can be calculated as
φm
∆I m =
0
Tdemag
DTs
t
Vin ( DTs )
= 0.5 A .
Lm1
During the transistor off-interval, this magnetizing current, flowing through the diode D3,
decreases and comes to zero after Tdemag = DTs = 1.825µ s , as shown in Fig. 8-7.
Ts
Fig. 8-6 Forward converter core flux.
© Copyright Ned Mohan 2007
203
© Copyright Ned Mohan 2007
204
PSpice Modeling: C:\FirstCourse_PE_Book07\forward.sch
vA
0
t
DTs
Ts
v1
48V
0
i1
3.43 A
t
−48V
3.93 A
0
t
i3
0.5 A
0
t
Tdemag
Figure 8-7 Waveforms in the Forward converter of Example 8-2.
© Copyright Ned Mohan 2007
205
© Copyright Ned Mohan 2007
Simulation Results
206
Two-Switch Forward Converters
5.0A
4.0A
+
3.0A
T1
D2
Vin
iL
DF
−
2.0A
Do
D1
T2
q (t )
1.0A
Figure 8-8 Two-switch Forward converter.
0A
0s
I(D_Pwr3)
2us
I(D_Pwr2)
4us
6us
8us
10us
12us
14us
16us
18us
20us
Time
© Copyright Ned Mohan 2007
207
© Copyright Ned Mohan 2007
208
FULL-BRIDGE CONVERTERS
PWM Control
T1
+
D1
T3
+
N2
vA
+
Vin
-
v1
−
T4
N1
−
N2
to T1 and T2
vc
Vo
-
T2
vr
+
iL
to T3 and T4
vr
T1 , T2
(a)
D2
on
Vin
v1
(−Vin )
DTs
vA
-
+
-
all
off
on
© Copyright Ned Mohan 2007
+
v1
-
+
v2 iL / 2 v A =iL0
-
+
v′2
+
Vo
-
iL / 2
-
Figure 8-10 Full-Bridge converter waveforms.
Phase-Shift Modulated (PSM)
T1 , T2
iL
Vo
-
Ts
•
all
off
on
+
+
N2
Vin
N1
+
v1
Pulse-Width Modulated (PWM), and
T3 , T4
iL
D1
i1
t
DTs
•
all
off
(b)
Figure 8-11 PWM-IC and control signals for transistors.
Figure 8-9 Full-Bridge converter.
0
vc
0
(a)
(b)
Figure 8-12 Full-Bridge: sub-circuits.
209
© Copyright Ned Mohan 2007
210
Example 8-3 In a Full-bridge converter shown in Fig. 8-9, Vin = 48V , Vo = 5V , and
N1 / N 2 = 6 .
v1
0
T1 , T2
inductance of L = 0.25µ H .
t
DTs
Ts / 2
T3 , T4
N2
Vin
N1
The filter inductor has an
Assuming this converter to be lossless, calculate the
waveforms associated with it.
Ts
vA
This converter is operating in CCM with a switching frequency
f s = 200 kHz and supplying an output load Po = 100W .
Solution
VA = Vo = 2
N2
DVin
N1
14. The peak-peak-ripple in the filter inductor current iL can be calculated from the
t
0
From Eq. 8-11, the duty-ratio D = 0.3125 , where Ts = 5µ s . The average
currents are I in = 2.083 A and I out = 20 A . The voltage waveforms are shown in Fig. 8voltage waveforms in Fig. 8-14
Figure 8-13 Full-Bridge converter waveforms.
∆I L , p − p =
( v A − Vo )( DTs )
= 18.75 A .
L
Therefore, iL waveform is as shown in Fig. 8-14, with a minimum of
N 
Vo
= 2 2  D
Vin
 N1 
I L , min = I out −
∆I L , p − p
2
= 10.625 A and a maximum of I L , max = I out +
∆I L , p − p
2
= 29.375 A .
Taking the transformer turns-ratio into account, the primary current i1 and the input
current iin ramp from 1.77 A to 4.896 A , and are zero when all the transistors are off.
© Copyright Ned Mohan 2007
211
© Copyright Ned Mohan 2007
212
PSpice Modeling: C:\FirstCourse_PE_Book07\fbsmps.sch
v1
48V
Ts / 2
0
DTs
vA
8V
t
VA = Vo
5V
0
iL
t
29.375 A
10.625 A
0
i1
t
4.896 A
1.77 A
0
t
iin
4.896 A
1.77 A
0
t
Figure 8-14 Waveforms of the Full-Bridge converter of Example 8-3.
© Copyright Ned Mohan 2007
213
© Copyright Ned Mohan 2007
Simulation Results
214
Half-Bridge and Push-Pull Converters
200V
100V
N1
+
Vin
0V
−
-100V
Vin+
2−
Vin
2
+
D1
T1
110us
115us
120us
125us
130us
135us
140us
145us
150us
iL
T2
+
-
VO
-
N1
−
N2
+
+
-
VO
vA
+
vA
iL
D1
N2
(a )
-200V
100us
105us
V(R1:2,D2:2)
N2
+
Vin
−
-
T1
T2
N1
N2
D2
D2
(b)
Figure 8-15 Half-Bridge and Push-Pull converters.
Time
© Copyright Ned Mohan 2007
215
© Copyright Ned Mohan 2007
216
BASICS OF MAGNETIC DESIGN
Chapter 9
9-1
9-2
9-3
9-4
9-5
9-6
9-7
Design of High-Frequency Inductors and Transformers
Introduction
Basics of Magnetic Design
Inductor and Transformer Construction
Area-Product Method
Design Example of an Inductor
Design Example of a Transformer for a Forward Converter
Thermal Considerations
References
Problems
•
•
The peak flux density Bmax in the magnetic core to limit core losses, and
The peak current density J max in the winding conductors to limit conduction
losses
© Copyright Ned Mohan 2007
217
218
AREA-PRODUCT METHOD
INDUCTOR AND TRANSFORMER CONSTRUCTION
Core Window Area Awindow
Acore
Acore
Awindow =
Awindow
Acond , y =
φ
Acond
Awindow
(a)
(b)
Awindow =
Figure 9-1 Cross-sections.
© Copyright Ned Mohan 2007
219
1
kw
∑( N
y
y
Acond , y )
I rms , y
J max
∑( N
I
y rms , y
y
)
k w J max
© Copyright Ned Mohan 2007
220
Core Cross-Sectional Area Acore
Acore =
Core Area-Product A
App( == AA
AAwindow
)
core
core window
φˆ
Bmax
φˆ =
inductor:
LIˆ
N
Acore =
LIˆ
NBmax
inductor:
Ap =
transformer:
Ap =
ˆ
LII
rms
k w J max Bmax
kconv ∑V y I y ,rms
k w Bmax J max f s
transformer:
Design Procedure Based on Area-Product Ap
v1
k V
φˆ = conv in
N1 f s
Acore =
inductor:
0
DTs
φ
kconvV y
Ts
(−Vin )
t
φ̂
0
N y f s Bmax
LIˆ
N=
Bmax Acore
Vin
transformer:
t
Figure 9-2 Waveforms in a transformer for a Forward converter.
© Copyright Ned Mohan 2007
221
DESIGN EXAMPLE OF AN INDUCTOR
Ny =
L
N2
ℜg
ℜg Ag
µo Acore
Ag =
N 2 µo Acore
L
kconvV y
Acore f s Bmax
© Copyright Ned Mohan 2007
222
From the Magnetics, Inc. catalog [2], we will select a P-type material, which has the
saturation flux density of 0.5T and is quite suitable for use at the switching frequency of
100kHz . A pot core 26×16, which is shown in Fig. 9-4 for a laboratory experiment, has
In this example, we will discuss the design of an inductor that has an inductance
L = 100 µ H . The worst-case current through the inductor is shown in Fig. 9-3, where the
the core Area Acore = 93.1 mm 2 and the window Area Awindow = 39 mm 2 . Therefore, we
average current I = 5.0 A , and the peak-peak ripple ∆I = 0.75 A at the switching
will select this core, which has an Area-Product Ap = 93.1 × 39 = 3631mm 4 .
frequency f s = 100 kHz . We will assume the following maximum values for the flux
density and the current density: Bmax = 0.25 T , and J max = 6.0 A / mm 2 (for larger cores,
N=
this is typically in a range of 3 to 4 A / mm 2 ). The window fill factor is assumed to be
k w = 0.5 .
100 µ × 5.375
23
0.25 × 93.1 × 10−6
iL
Winding wire cross sectional area Acond = Irms / Jmax = 5.0/6.0 = 0.83mm2 . We will use
five strands of American Wire Gauge AWG 25 wires [3], each with a cross-sectional area
of 0.16mm2 , in parallel.
∆I
∆I
Iˆ = I +
= 5.375 A
2
I rms = I 2 +
Ap =
I
t
Figure 9-3 Inductor current waveforms.
Ag =
1
∆I 2 5.0 A
12
100 × 10−6 × 5.375 × 5
× 1012 = 3587 mm 4
0.5 × 0.25 × 6 × 106
© Copyright Ned Mohan 2007
232 × 4π × 10−7 × 93.1 × 10−6
0.62 mm
100 µ
Figure 9-4 Pot core mounted on a plug-in board.
223
© Copyright Ned Mohan 2007
224
DESIGN EXAMPLE OF A TRANSFORMER FOR A FORWARD CONVERTER
The required electrical specifications for the transformer in a Forward converter are as
follows: f s = 100kHz and V1 = V2 = V3 = 30V . Assume the rms value of the current in
each winding to be 2.5 A . We will choose the following values for this design:
Bmax = 0.25T and J max = 5A/mm .
2
Ap =
kconv
k w f s Bmax J max
k w = 0.5
∑Vˆ I
y rms , y
9-7
Designs presented here do not include eddy current losses in the windings, which can be
very substantial due to proximity effects. These proximity losses in a conductor are due
to the high-frequency magnetic field generated by other conductors in close proximity.
To minimize these proximity losses suggests inductors with a single-layer construction.
In transformers, windings can be interleaved to minimize these losses, as described in
detail in [1]. Therefore, the area-product method discussed in this chapter is a good
starting point, but the designs must be evaluated for temperature rise due to additional
losses.
kconv = 0.5
= 1800 mm 4
y
For the pot core 22×13 [2], Acore = 63.9 mm2 , Awindow = 29.2 mm2 , and therefore
Acond ,1 =
I1,rms
J max
THERMAL CONSIDERATIONS
Ap =1866 mm4 .
2.5
=
= 0.5 mm 2
5
We will use three strands of AWG 25 wires [3], each with a cross-sectional area of
0.16mm2 , in parallel for each winding.
N1 =
0.5 × 30
10
( 63.9 × 10 ) × (100 × 103 ) × 0.25
−6
N1 = N 2 = N 3 = 10
© Copyright Ned Mohan 2007
225
© Copyright Ned Mohan 2007
226
HARD-SWITCHING IN SWITCHING POWER-POLES
Vin
Chapter 10
10-1
10-2
10-3
10-4
Soft-Switching In DC-DC Converters And Inverters For Induction
Heating And Compact Fluorescent Lamps
+
+
Vin
−
Introduction
Hard-Switching In the Switching Power-Poles
Soft-Switching In the Switching Power-Poles
Inverters for Induction Heating and Compact Fluorescent Lamps
References
Problems
RGG
iD
vDS
iD
0
vDS
−
iD
t fv
tri
0
t
tc , off
Vin I o
psw
t fi
trv
tc , on
Io
Vin
vDS
Io
Vin I o
psw
tc , on
tc , off
t
(b)
(a)
Figure 10-1 Hard switching in a power-pole.
Psw ∝ f s ( tc ( on ) + tc ( off ) )
227
© Copyright Ned Mohan 2007
228
Synchronous Buck Converter with ZVS
SOFT-SWITCHING IN SWITCHING POWER-POLES
q+
-
ZVS (zero voltage switching), and
ZCS (zero current switching)
0
T+
iL
q+
vA
Vin
Zero Voltage Switching (ZVS)
Vin
t
Ts
0
0
T−
q
DTs
q−
Vo
vA
−
Vo
t
IˆL
iL
IL
0
(a)
t =0
t
(b)
Figure 10-3 Synchronous-rectified Buck converter.
T+
(a)
q+
C+
q+
(b)
0
iL
t =0
Vin
Figure 10-2 ZVS in a MOSFET.
1
q−
T−
q−
1
C−
Vo
0
tdelay
(a)
© Copyright Ned Mohan 2007
229
(b)
Figure 10-4 Synchronous-rectified Buck converter with ZVS.
© Copyright Ned Mohan 2007
230
PSpice Modeling: C:\FirstCourse_PE_Book07\zvscv.sch
T+
+
q =0
Vin
T−
q− = 0
iC+
D+ +
_vC+
T+
+
q =0
C+
Vin
iC−
+
vC−
D _
C−
IˆL
−
(a)
T−
q−
IˆL
D−
(b)
Fig. 10-5 Transition in synchronous-rectified Buck converter with ZVS.
vC + + vC − = Vin
C
d
d
v + + C vC − = 0
dt C
dt
iC + + iC − = 0
iC + = −iC − =
© Copyright Ned Mohan 2007
iC + = −iC −
⇒
IˆL
2
231
© Copyright Ned Mohan 2007
232
Simulation Results
Phase-Shift Modulated (PSM) DC-DC Converter
3.0
vA
2.0
+
DA
+ TA+
Vd +
2−
ficticiousVin
0
1.0
Vd +
2−
0
A
TA−
DA−
TB+
iAB
TB−
−
DB+
+
B −
vB
LlT
vAB
DB−
iL
Da+
D+b
Da−
b
D−b
vAB a
Io
iAB
t
(a)
(b)
-1.0
0s
V(GA2)
V(GA1)
5us
I(L1)
10us
15us
20us
25us
30us
Figure 10-6 Phase-Shift Modulated (PSM) DC-DC Converter.
Time
© Copyright Ned Mohan 2007
233
© Copyright Ned Mohan 2007
234
Hybrid Topology
Q1
Q3
Q2
Q4
Chapter 11
Q5
+
Applications of Switch-Mode Power Electronics in Motor
Drives, Uninterruptible Power Supplies and Power Systems
+
Vin
Q6
11-1
11-2
11-3
11-4
Vo
−
−
uncontrolled full − bridge phase − modulated full − bridge
Introduction
Electric Motor Drives
Uninterruptible Power Supplies
Utility Applications
References
Problems
Figure 10-7 A superior hybrid topology to achieve ZVS down to no load [3-5].
R. Ayyanar, N. Mohan, “Zero voltage switching DC-DC converter,”
US patent 6,310,785, 2001.
© Copyright Ned Mohan 2007
235
236
DC MOTORS
Electric Drive
stator
magnets
Electric Source
(utility)
Power
Processing
Unit
fixed
form
adjustable
form
Motor
Load
rotor
winding
speed /
position
Sensors
Controller
Figure 11-2 Exploded view of a dc motor [Source: Electro-Craft Corporation].
input command
(speed/ position)
Figure 11-1 Block diagram of an electric drive system.
© Copyright Ned Mohan 2007
237
© Copyright Ned Mohan 2007
238
Operating Principles of DC Machines
DC-Machine Equivalent Circuit
ea =k ωm
va = ea + Ra i a + La
E
dia
dt
d ωm
1
=
(Tem −TL )
dt
J eq
Tem = k ia
ia =
T
Tem
kT
+
Ra
k
T
=
k
PPU
Va
E
−
La
+
−
ea = k Eωm
Figure 11-3 DC motor equivalent circuit.
© Copyright Ned Mohan 2007
239
© Copyright Ned Mohan 2007
240
PERMANENT-MAGNET AC MACHINES
Torque-Speed Characteristics
Ia =
Tem ( = TL )
kT
φ
ωm
ω m, rated
f
ωm =
Ea Va − Ra I a Va − Ra ( Tem / kT )
=
=
kE
kE
kE
b − axis
JJG
Br (t )
ib
constant at its rated value
Va1 > Va2 > Va3 > Va4
Va1 = rated
θm
N
Va
ia
S
Va2
Va3
Va4
θ m (t )
a − axis
a − axis
ic
( b)
c − axis
(a )
0
rated
(a )
0
Tem
ωm
Figure 11-5 Two-pole PMAC machine.
(b)
Figure 11-4 (a) Torque-Speed characteristics, and (b) Va versus ωm .
© Copyright Ned Mohan 2007
241
© Copyright Ned Mohan 2007
Ia =
Power
Processing
Utility
Control
input
Unit
Controller
ia
ib
ic
Sinusoidal
PMAC
Load
+
Position
sensor
kT , phase
Rs
∠00
PPU
θ m (t )
Va
Va
Ls
motor
Ema = k E , phaseωm ∠00
+
−
jωm Ls I a
Ia
Ema
(b)
−
(a)
Figure 11-7 Equivalent circuit diagram and the phasor diagram of PMAC (2 pole).
Figure 11-6 Block diagram of a PMAC machine.
© Copyright Ned Mohan 2007
Tem , phase
242
243
© Copyright Ned Mohan 2007
244
Induction Machines
PMAC Torque-Speed Characteristics
f1 > f 2 > f3 > f 4
ωm
b − axis
f1
f2
Va
ib
f3
2π / 3
0
ia
2π / 3
0
Tem
(a)
a − axis
2π / 3
f4
f =
(b)
ωm
2π
ic
Figure 11-8 Torque-speed characteristics and the voltage versus frequency in PMAC.
(b )
c − axis
(a )
Figure 11-9 (a) Three-phase stator; (b) squirrel-cage rotor.
© Copyright Ned Mohan 2007
245
Principles of Induction Motor Operation
−
−
−
va
© Copyright Ned Mohan 2007
246
Per-Phase Equivalent Circuit of Induction Machines
Vc
+
vb
vc
+
ib
vb
−
+
ia
I mc
I mb
Va
vc
+
+
ic
Vb
(a)
Vra′ = k Eω slip
+
−
Ia
− n− v +
a
+
I ma
PPU
(b)
Figure 11-10 Induction machine: applied voltages and magnetizing currents.
R′r
+
Ea′ = k Eω m ∠00
−
Lm
Va
I ma
−
I ma = I m ∠ − 90o ,
I mb = I m ∠ − 210o , and
ωsyn
ωsyn = 2π f
slip speed
© Copyright Ned Mohan 2007
o
ωslip = ωsyn − ωm
o
I ma
Ia
E′a Rr′ I ra
′
0
(a)
I mc = I m ∠ − 330o
2π f
=
p/2
Va
I′ra
(b )
Va = Ema = k Eω syn ∠0
Va =Vrms ∠0 , Vb =Vrms ∠−120 , and Vc =Vrms ∠− 240
o
I ra′ = I ra′ ∠00
Figure 11-11 Induction motor equivalent circuit and phasor diagram.
for a p-pole machine
slip frequency
f slip =
ωslip
f
ωsyn
247
© Copyright Ned Mohan 2007
248
UNINTERRUPTIBLE POWER SUPPLIES (UPS)
ωm
f1 > f 2 > f 3 > f 4
f1
f2
Va
f3
f4
0
Tem
(a)
0
(b)
f =
ωsyn
2π
Figure 11-12 Induction motors: Torque-speed characteristics and voltage vs. frequency.
© Copyright Ned Mohan 2007
249
Fig. 11-13 CBEMA curve.
© Copyright Ned Mohan 2007
250
UTILITY APPLICATIONS OF SWITCH-MODE
POWER ELECTRONICS
Rectifier
Inverter
Filter
Critical
Load
+
Energy
Storage
i
Vd
Figure 11-14 Block diagram of UPS.
vconv
vs
−
Figure 11-15 Interaction of the switch-mode converter with the ac utility system.
© Copyright Ned Mohan 2007
251
© Copyright Ned Mohan 2007
252
Chapter 12
I
jX
+
Vconv
Vconv
+
−
−
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
Vs
δ
Vs
jXI
Re
I
( b)
(a )
Figure 11-16 Per-phase equivalent circuit and the phasor diagram.
© Copyright Ned Mohan 2007
Synthesis of DC and Low-Frequency Sinusoidal AC Voltages for
Motor Drives and UPS
Introduction
Bi-Directional Switching Power-Pole as the Building Block
Converters for DC-Motor Drives
Synthesis of Low-Frequency AC
Single-Phase Inverters
Three-Phase Inverters
Multi-Level Inverters
Converters for Bi-Directional Power Flow
Matrix Converters
References
Problems
253
254
SWITCHING POWER-POLE AS THE BUILDING BLOCK
conv1
conv2
utility
Load
Buck
Buck Boost
controller
Vd
Vd
q
+
Vd
+
io
A
+
+
−
−
vo
B
ea
Vd
-
-
(a)
q − = (1 − q )
ac motor
dc motor
iA
A
(a)
vA
B
n
vB
C
q =1
q =1
iL
Figure 12-1 Voltage-link system.
Boost
q=0
q
q−
(b) iL = positive
Vd
q=0
q
q−
(c) iL = negative
Figure 12-3 Bi-directional power flow through a switching power-pole.
vC
(b)
Figure 12-2 Converters for dc and ac motor drives.
© Copyright Ned Mohan 2007
255
© Copyright Ned Mohan 2007
256
ida
+
iL
Vd
Vd
a
Vd
Vd
q=0
q =1
−
(c) q = 0
N
1: d a
(a)
(b)
−
Figure 12-5 switching-cycle averaged representation of the bi-directional power-pole.
Figure 12-4 Bidirectional Switching power-pole.
© Copyright Ned Mohan 2007
vaN
vaN
qa
(b) q = 1
(a)
ia
+
Vd
+
−
q
ida
ia
257
© Copyright Ned Mohan 2007
258
Pulse-Width-Modulation (PWM) of the Bi-Directional
Switching Power-Pole
vcntrl ,a
Vˆtri
+
vtri
vtri
0
qa
da
0
vaN
0
Vd
T
da s
2
Vd
t
−
a
+
vaN
vcntrl ,a
vtri
d aVd
Ts
2
t
ida
t
N
qa
(a)
−
ia
ia
ida
+
+
da v
aN
Vd
−
vcntrl ,a
−
1
Vˆtri
(b)
Figure 12-7 Switching power-pole and its duty-ratio control.
Figure 12-6 Waveforms for PWM in a switching power-pole.
© Copyright Ned Mohan 2007
259
© Copyright Ned Mohan 2007
260
DC-MOTOR DRIVES
a
+
+
Vh
a
fs
0
Vh
2 fs
3 fs
(a)
f1
fs
2 fs
k1 f s + k2 f1
Vd
3 fs
+
van
4 fs
4 fs
vo
+
−
vbn
−
( b)
+
n −
−
vbn
+
b
v
van = o
2
N
−
vbn = −
Vd
2
qb
− vo
−
n
qa
Figure 12-8 Harmonics in the output of a switching power-pole.
+
van
N
(a)
vo
2
Vd
2
(b)
Figure 12-9 Converter for dc-motor drive.
f h = k1 f s ± kN
2 f1
sidebands
© Copyright Ned Mohan 2007
261
ida
+
vo
−
idb
ia
vcntrl
ib
Vd
1: d a
vcntrl ,a
vcntrl ,b
k PWM
vo
Figure 12-11 Gain of the converter for dc drives.
−
vtri
262
io
id
+
vcntrl
© Copyright Ned Mohan 2007
1/ Vˆtri
1/ Vˆtri
1: d b
da
db
Figure 12-10 switching-cycle averaged representation of the converter for dc drives.
© Copyright Ned Mohan 2007
263
© Copyright Ned Mohan 2007
264
Vˆtri
vcntrl ,a
id
vcntrl ,b
0
t
Ts / 2
ida
qa , vaN
0
qb, vbN
+
ia
−
b
ib
vo
-
t
+
ea
−
Figure 12-13 Currents defined in the converter for dc-motor drives.
0
v0
io
idb
a
Vd
d aTs / 2
dc motor
+
t
d bTs / 2
v0
0
t
Figure 12-12 Switching voltage waveforms in a converter for dc drive.
© Copyright Ned Mohan 2007
265
© Copyright Ned Mohan 2007
Vˆtri = 1V
Example 12-3 continued
vcontrol , a = 0.84V
Example 12-3
+
Ra
vo
+
−
(a )
+
0
La
+
0 db / 2
vaN
vo ,ripple
ea
−
vcontrol , b = 0.16V
io ,ripple
io
266
da / 2
1
2
350V
1
0
t / Ts
vbN
0
−
(b)
350V
t / Ts
350V
vo
Fig. 12-14 Superposition of dc and ripple-frequency variables.
t / Ts
vo = 238V
t / Ts
0
vo ,ripple
0
112V
t / Ts
(−238)V
4.5A
io
io = 4 A
3.5 A
d a − db
= 0.34
2
0
4.5 A
id
t / Ts
3.5A
id = 2.72 A
t / Ts
0
© Copyright Ned Mohan 2007
267
© Copyright Ned Mohan 2007
Figure 12-15 Switching current waveforms in Example 12-3.
268
Single-Phase Inverters UNINTERRUPTIBLE POWER SUPPLIES (UPS)
Synthesis of Low-Frequency AC
id
id
vaN
Vd
0
Vd
vaN
vaN
0
+
0
−
vaN
ωt
qa
qb
Ts
ia
ia
+
+
vo
−
io
Critical
Load
ib
+
Vd
vo
−
−
da
io
Critical
Load
ib
1: d a
1: d b
(b)
( a)
Figure 12-17 Single-phase uninterruptible power supply.
Figure 12-16 Waveforms of a switching power-pole to synthesize low-frequency ac.
© Copyright Ned Mohan 2007
269
© Copyright Ned Mohan 2007
270
Vd
vaN
vo
vcom = 0.5Vd
vo
io
van
0
φ1
vbN
ω1t
Figure 12-19 Output voltage and current.
0
ωt
Figure 12-18 Switching-cycle averaged voltages in a single-phase UPS.
© Copyright Ned Mohan 2007
271
© Copyright Ned Mohan 2007
272
Three-Phase Inverters
Example 12-4
Vˆtri
+
vcntrl ,a
vcntrl ,b
0
−
0
n
c
qa , vaN
t
d aTs / 2
qa
N
qb
Vd
−
qc
qb, vbN
1: d a
(a )
0
v0
0
N
1: d c
1: d b
(b)
Figure 12-21 Three-phase converter.
t
d bTs / 2
v0
a
b
c
+
b
Vd
t
Ts / 2
a
t
Figure 12-20 Waveforms in the UPS of Example 12-4.
© Copyright Ned Mohan 2007
273
a
b
vbn
vcn
van
Vd
−
vaN
vcom
n
vcom
vcom
vcom
i
vbN
vcN
van
i
N
vaN
−
+
c
van
274
Sine PWM
Superposition -
+
© Copyright Ned Mohan 2007
Vd
2
n
i
vcom
0
vcom
Figure 12-23 switching-cycle averaged voltages due to Sine-PWM.
(b )
N
ωt
(a )
Figure 12-22 switching-cycle averaged output voltages in a three-phase converter.
© Copyright Ned Mohan 2007
275
© Copyright Ned Mohan 2007
276
PSpice Modeling: C:\FirstCourse_PE_Book07\PWMinv3.sch
Example 12-5
Vˆtri
0
vcntrl ,c
t
vaN
da
0
vcntrl ,a
vcntrl ,b
vaN
Ts
2
vbN
db
Ts
2
t
vbN
0
t
vcN
0
dc
Ts
2
Ts / 2
vcN
t
Figure 12-24 Switching waveforms in Example 12-5.
© Copyright Ned Mohan 2007
277
PSpice Modeling: C:\FirstCourse_PE_Book07\pwninv3ph_avg.sch
© Copyright Ned Mohan 2007
278
Simulation Results
20A
10A
0A
-10A
-20A
70ms
I(L3)
I(L2)
75ms
I(L1)
80ms
85ms
90ms
95ms
100ms
Time
© Copyright Ned Mohan 2007
279
© Copyright Ned Mohan 2007
280
SV-PWM
SV-PWM: Sector 1
Vd
vbN
v aN
v cN
Vd
Vd / 2
a
c
+
vaN
Vd
Vd
2
vcN
vaN (t )
−
t
0
−
N 1: d a (t )
(a )
0
vcN (t )
−
1: d c (t )
(b)
Figure 12-26 Waveforms in sector 1 of Fig. 12-25
t
t1
+
+
vbN
Figure 12-25 Three-phase voltages to be synthesized.
© Copyright Ned Mohan 2007
281
vctrl ,d
aNa
Vˆ
tri
vaN
1
Sine-PWM
0.5
282
Square-Wave (Six-Step) Operation
SV-PWM versus Sine-PWM
d aN =
© Copyright Ned Mohan 2007
SV-PWM
0
vbN 0
vk
vctrl0.5
, com+
, SV − PWM
Vd
0
0
vcN
0
vab
0
0
t
0 0
Figure 12-27 Duty-ratio d a in Sine-PWM and SV-PWM for the same phase output.
Vd
π
2π ωt
2π / 3
π /3
1.1Vd
5π / 3
ωt
ωt
4π / 3
vab1
π
2π
ωt
Figure 12-28 Square-wave (six-step) waveforms.
© Copyright Ned Mohan 2007
283
© Copyright Ned Mohan 2007
284
VOLTAGE-LINK STRUCTURE WITH
BI-DIRECTIONAL POWER FLOW
Three-Level Inverter
+
AC motor
i A (t ) + eA (t )−
va (t ) ia (t )
−
+
(a)
+
−
n
Vd
Sa+1
C1
Vd
P
Rectifier
Sa+2
P
0
a
S
b
+
c
−
a2
motoring
mode
regenerative
braking mode
vsa (t ) ia (t )
−
Ls
iA (t )
Leq
e (t )
+ A −
n
+
(b)
C2
Inverter
c
Sa−1
dc
b
a
−
Vd
A
da
db
C
B
dA
dB
dC
ac motor
−
I A1
I a1
Figure 12-29 Three-level Inverters.
(c )
Ls
+
Vsa1
+
−
−
Va1
V An1
Leq
+
+
EA
−
− sinusoidal
Figure 12-30 Voltage-link structure for bi-directional power flow.
© Copyright Ned Mohan 2007
285
© Copyright Ned Mohan 2007
286
Matrix Converter
va
ia
ia
va
vc
daA
vb
dbA
dcA
vA
daB
dbB
dcB
daC
vB
vC
dbC
vb
vc
(b )
Figure 12-31 Matrix Converter.
vB
iB
vC
daA
daB
daC
dbA
dbB
dbC
dcA
dcB
dcC
iC
ib
dcC
(a )
vA
iA
ic
Figure 12-32 Matrix Converter switching-cycled averaged representation.
© Copyright Ned Mohan 2007
287
© Copyright Ned Mohan 2007
288
va
vA
iA
ia
daA + Da
vb
vB
iB
daB + Da
vC
va
D a (t ) + D b (t ) + D c (t )
iC
daC + Da
vb
D c ( t )D a ( t )D b ( t )D c ( t )D ( t )D b ( t )
a
ib
0.5
dbA + Db
dbB + Db
dbC + Db
vc
t
vc
(a )
ic
dcA + Dc
dcB + Dc
ia
1.0
dcC + Dc
vA
iA
vB
iB
vC
iC
d aA + D a + ∆
d aB + D a + ∆
d aC + D a + ∆
d bA + D b + ∆
d bB + D b + ∆
d bC + D b + ∆
d cA + D c + ∆
d cB + D c + ∆
d cC + D c + ∆
ib
ic
(b)
Figure 12-34 Modification of common-mode offsets to provide current path.
Figure 12-33 Common-mode offsets to ensure the realizable range of duty-ratios.
© Copyright Ned Mohan 2007
289
© Copyright Ned Mohan 2007
Chapter 13
13-1
13-2
13-3
13-4
13-5
daA + dbA + dcA = 1
daA + dbA
daA
0
qcA
qbA
qaA
290
Thyristor Converters
Introduction
Thyristors (SCRs)
Single-Phase, Phase-Controlled Thyristor Converters
Three-Phase, Full-Bridge Thyristor Converters
Current-Link Systems
References
Problems
Figure 12-35 Generation of switching signals.
© Copyright Ned Mohan 2007
291
292
Thyristors (SCRs)
+
+
A
(a)
(b)
G
G
−
P
pn1
N
pn2
P
K
vd
vs
(a )
A
is
R
−
vd
Vd
pn3
0
N
α
( b)
K
is
ωt
α
vs
0
ωt
iG
0
Figure 13-1 Thyristors.
ωt
ωt = 0
Figure 13-2 A simple thyristor circuit with a resistive load.
© Copyright Ned Mohan 2007
293
+
vs
(a )
Ls
vd
R
id
−
is
−
vd
+
Vd
vs
0
α
(b)
0
0
is
iG
ωt = 0
vs
294
Single-Phase, Phase-Controlled Thyristor Converters
is
+
© Copyright Ned Mohan 2007
α
ωt
Ls
+
1
1
3
is +
vd
−
4
2
−
+
vd
Id
+
ea
−
3
vs
−
4
2
−
ωt
(a)
ωt
(b)
Figure 13-4 Full-Bridge, single-phase thyristor converter.
Figure 13-3 Thyristor circuit with a resistive load and a series inductance.
© Copyright Ned Mohan 2007
295
© Copyright Ned Mohan 2007
296
vd
Vd
0
π
− vs
iG
(α + π )
1,2
0
is1
is
ωt
vs
3,4
Vd
1,2
ωt
Id
0
ωt
− Id
0
α
3, 4
Rectifier
P = Vd I d = +
Vd
1, 2
0
180 o
150 o
90 o
α
Id
3, 4
Figure 13-5 Single-phase thyristor converter waveforms.
(a)
Inverter
P = Vd I d = −
(b)
Fig. 13-6 Effect of the delay angle α .
vd (t ) = vs (t ) and is (t ) = I d
α < ωt ≤ α + π
vd (t ) = −vs (t ) and is (t ) = − I d
α + π < ωt ≤ α + 2π
Vd =
1
π
α +π
2
4
Iˆs1 = I d
∫ Vˆ sin ωt ⋅ d (ωt ) = π Vˆ cosα
α
s
s
1
P = Vˆs Iˆs1 cos α
2
π
© Copyright Ned Mohan 2007
297
© Copyright Ned Mohan 2007
298
The Effect of Ls on Current Commutation
Example 13-1
Au = 2ω Ls I d
Draw the waveforms for the full-bridge thyristor converter of
Fig. 13-4b if it’s operating in an inverter mode with the delay angle α equal to 150 .
vd
0
Solution
1
Since α now equals 150 , in comparison to Fig. 13-5 the is waveform is
0
0
shifted by 150 with respect to vs waveform as shown in Fig. 13-7.
− vs
vs
0
α
2
i4
ωt
α
vd
ωt
vs
1,2
3,4
ωt
is1
is
Id
α u
−Id
ωt
(b)
φ1
Figure 13-8 Effect of Ls on Current Commutation.
Id
ωt
1,2
3, 4
1,2
α+u
α+u
∫ v d(ωt) = L α∫
α
ωt
L
ωt = 0
Figure 13-7 Single-phase thyristor converter in an inverter mode with α = 1500 .
© Copyright Ned Mohan 2007
iG
Id
−
i2
−Id
0
−vs
+
(a)
Vd
is
iG
Vd
0
i3
0
α
vd
0
4
3
i1
vs
is Ls
+
−
− vL +
299
∆Vd =
2
π
ω Ls I d
© Copyright Ned Mohan 2007
s
I
d
dis
d(ωt) = ωLs ∫ dis = ωLs (2Id )
dt
−Id
Vd =
2
π
Vs cos α −
2
π
ω Ls I d
300
PSpice Modeling: C:\FirstCourse_PE_Book07\Thyrect1ph.sch
Simulation Results
300
200
100
0
-100
-200
0s
V(Ld:1,SCR2:A)
5ms
I(Ls2)*5
10ms
15ms
20ms
25ms
30ms
Time
© Copyright Ned Mohan 2007
301
© Copyright Ned Mohan 2007
302
vPn
van
THREE-PHASE, FULL-BRIDGE THYRISTOR CONVERTERS
vcn
vbn
Aα
ωt
0
α
vNn
id
van
− +
n −
−
vbn
vcn
ia
van
− +
+
1
5
3
ia
ia
1
0
P
3
Ls
5
+
n
vd
+
4
+
2
6
−
(a)
4
6
2
−
Id
+
−
1
ib
vd
ωt
4
3
0
ωt
6
N
ic
0
6
5
5
2
(b)
ωt
Figure 13-10 Waveforms with Ls = 0 .
Figure 13-9 Three-phase Full-Bridge thyristor converter.
Vdo =
∆Vα =
© Copyright Ned Mohan 2007
1
4
303
© Copyright Ned Mohan 2007
π /6
1
3
Vˆ cos ωt ⋅ d (ωt ) = VˆLL
π / 3 −π∫/ 6 LL
π
α
1
3
Vˆ sin ωt ⋅ d (ωt ) = VˆLL (1 − cos α )
π / 3 ∫0 LL
π
Aα
304
Example 13-3
Three-phase thyristor converter of Fig. 13-9b is operating in its
Effect of Ls
inverter mode with α = 1500 . Draw waveforms similar to Fig. 13-10 for this operating
condition.
van
These waveforms for α = 1500 in the inverter mode are shown in Fig. 13-11.
Solution
+
v Nn
vcn
van
0
vbn
vcn
+
n
vbn
+
ia
P
4
ωt
Au =
6
5
vcn
vbn
Ls
6
N
i5
i1
0
ωt
u
( b)
3
3
ωt
α
Figure 13-12 Commutation of current from thyristor 5 to thyristor 1.
4
0
v Pn
ωt = 0
ωt
0
v Pn
0
5
1
1
ic
Ls
v Pn
Au
(a )
vPn
ib
vL
1
−
Id
ωt
α
van
Ls
+
α +u
∫
α
Id
vL d (ωt ) = ω Ls ∫ dis = ω Ls I d
∆Vu =
0
Au
3
= ω Ls I d
π /3 π
ωt
0
2
2
© Copyright Ned Mohan 2007
Figure 13-11 Waveforms in the inverter mode.
vPn
van
305
© Copyright Ned Mohan 2007
Current-Link Systems
vcn
vbn
306
Au
id
ωt
0
+
α
v Nn
u
ia
0
AC 1
1
4
ωt
−
vd 2
−
AC 2
Vd 1 =
Vd = Vdo − ∆Vα − ∆Vu
Vd 2
3 ˆ
3
VLL cos α − ω Ls I d
π
+
Figure 13-14 Block diagramof current-link systems.
Figure 13-13 Waveforms with Ls .
© Copyright Ned Mohan 2007
vd1
Ld
1
4
Vd =
Rd
π
307
3 ˆ
3
VLL1 cos α1 − ω Ls1 I d
π
π
3
3
= VˆLL 2 cos α 2 − ω Ls 2 I d
π
© Copyright Ned Mohan 2007
Id =
Vd 1 + Vd 2
Rd
π
308
INTRODUCTION
•
Chapter 14
14-1
14-2
14-3
14-4
14-5
14-6
14-7
Utility Applications of Power Electronics
Distributed Generation (DG)
-
Introduction
Power Semiconductor Devices and Their Capabilities
Categorizing Power Electronic Systems
Distributed Generation (DG) Applications
Power Electronic Loads
Power Quality Solutions
Transmission and Distribution (T&D) Applications
References
•
Power Electronic Loads - Adjustable Speed Drives
•
Power Quality Solutions
-
•
Problems
Dual Feeders
Uninterruptible Power Supplies
Dynamic Voltage Restorers
Transmission and Distribution (T&D)
-
© Copyright Ned Mohan 2007
Renewable Resources (Wind, Photovoltaic, etc.)
Fuel Cells and Micro-Turbines
Storage - Batteries, Super-conducting Magnetic Storage, Flywheels
High Voltage DC (HVDC) and HVDC-Light
Flexible AC Transmission (FACTS)
ƒ Shunt Compensation
ƒ Series Compensation
ƒ Static Phase Angle Control and Unified Power Flow Controllers
309
POWER SEMICONDUCTOR DEVICES
AND THEIR CAPABILITIES
310
CATEGORIZING POWER ELECTRONIC SYSTEMS
Thyristor
IGCT
IGBT
(a)
MOSFET
106
IGCT
Device current [A]
Power (VA)
108
Thyristor
Solid-State Switches
IGBT
104
102
MOSFET
101 102 103 104
Switching Frequency (Hz)
104
Traction
103
Automotive
Lighting
100
(b)
101
Figure 14-1 Power semiconductor devices.
102
103
104
Device blocking voltage [V]
(a)
© Copyright Ned Mohan 2007
Motor
Drive
Power
102 Supply
101
HVDC
FACTS
311
© Copyright Ned Mohan 2007
(b)
312
Converters as an Interface
Solid-State Switches
Converter
Source
Load
Controller
Figure 14-3 Back-to-back thyristors to act as a solid-state switch.
Figure 14-4 Power electronics interface.
© Copyright Ned Mohan 2007
313
Voltage-Link Systems
© Copyright Ned Mohan 2007
314
DISTRIBUTED GENERATION (DG) APPLICATIONS
+
AC1
−
AC2
Fig. 14-5 Block diagram of the voltage-link systems.
Current-Link Systems
Figure 14-7 Distributed utility structure of tomorrow [source: ABB].
AC1
AC2
Figure 14-6 Block diagram of the current-link systems.
© Copyright Ned Mohan 2007
315
© Copyright Ned Mohan 2007
316
Wind-Electric Systems
Wound rotor
Induction Generator
AC
Wind
Turbine
DC
DC
Generator-side
Converter
AC
Grid-side
Converter
Figure 14-8 Doubly-fed induction generators for wind-electric systems.
317
Figure 14-9 Wind-resource map of the United States [source: www.nrel.gov].
© Copyright Ned Mohan 2007
Photovoltaic (PV) Systems
Isolated
DC-DC
Converter
318
Fuel Cell Systems
PWM
Converter
Maximum Theoretical Voltage
Open 1.4 Circuit
Voltage
E=
1.2 -
Utility
1φ
Cell Voltage ( VC in Volts )
Max. Powerpoint Tracker
Figure 14-10 Photovoltaic systems.
Activation
Losses
- ∆gƒ
- 1200
2F
- 1000
1-
Ohmic
0.8 -
- 800
Losses
- 600
0.6 -
0.4 -
Cell Power
PC= VC x i
Mass
Transport
Losses
- 400
- 200
0.2 -
0 -|
0
Cell Power ( PC in mW )
© Copyright Ned Mohan 2007
|
500
|
|
1000
1500
Current Density ( i in mA/cm2 )
|
-0
2000
Figure 14-12 Fuel cell v-i relationship and cell power [source: www.NETL.DOE.gov].
Figure 14-11 A rooftop PV system [source: www.NREL.gov].
© Copyright Ned Mohan 2007
319
© Copyright Ned Mohan 2007
320
Energy Storage Systems
AC
Switch-mode
Converter
Utility
DC
DC
Flywheel
POWER ELECTRONIC LOADS
AC
Machine-side
Converter
Motor
Grid-side
Converter
Rectifier
Figure 14-13 Flywheel storage system.
Controller
Figure 14-14 Adjustable-speed drive.
Micro-Turbines
© Copyright Ned Mohan 2007
321
322
TRANSMISSION AND DISTRIBUTION (T&D) APPLICATIONS
POWER QUALITY SOLUTIONS
Dual Feeders
© Copyright Ned Mohan 2007
High Voltage DC (HVDC) Transmission
Feeder 1
Load
AC1
AC2
Feeder 2
Figure 14-15 Dual-feeders.
Uninterruptible Power Supplies
Rectifier
Inverter
Critical
Load
Filter
Energy
Storage
Figure 14-16 Uninterruptible power supplies.
Dynamic Voltage Restorers
−
vinj
+
+
vs
−
Power Electronic
Interface
Load
Figure 14-17 Dynamic voltage restorers.
© Copyright Ned Mohan 2007
323
© Copyright Ned Mohan 2007
324
HVDC Transmission System using Voltage-Link IGBT-based Converters
+
−
AC1
Flexible AC Transmission Systems (FACTS)
AC2
Figure 14-20 Block diagram HVDC transmission using a voltage-link-system.
E2∠−δ
E∠
1 0
jX
AC1
AC2
Figure 14-22 Power flow on a transmission line.
P=
© Copyright Ned Mohan 2007
325
Shunt-Connected Devices to Control the Bus Voltage Magnitude
E1 E2
sin δ
X
© Copyright Ned Mohan 2007
326
Series-Connected Devices to Control the Effective Series Reactance
jX
Utility
STATCOM
(a )
(b)
(c )
Figure 14-23 Shunt-connected devices for voltage control.
(a )
( b)
© Copyright Ned Mohan 2007
327
© Copyright Ned Mohan 2007
328
Unified Power Flow Controller (UPFC)
1. controlling the voltage magnitude E
2. changing the line reactance X, and/or
3. changing the power angle δ .
E1 + E3 = E2
sub-station
E1
I
-
E3
+
E2
E2
1
2
E1
Shunt
converter
E3
(b)
Series
converter
P2,Q2
Figure 14-26 UPFC combines many functions [source: Siemens].
P1,Q1
(a)
Figure 14-25 UPFC.
P1 = 3Re( E3 I * )
P2 = P1
Q1 = 3Im( E3 I * )
Q2 ≠ Q1
© Copyright Ned Mohan 2007
329
© Copyright Ned Mohan 2007
330