Motor Control
From Concept to Production
®
with Zynq -7000 AP SoC
Avnet Design Seminar
Course Objectives
During this course you will gain insight into:
● Avnet Zynq-7000 AP SoC / Analog Devices Intelligent Drives Kit
● Simulink® modeling for simulation and C / HDL code
generation, including a new prototype workflow targeting the
Xilinx Zynq-7000 All Programmable SoC
● Integrating Simulink models into Zynq-based motor control
using Xilinx Vivado® Design Suite
2
Moving from Simulink to Zynq
Simulation
Prototype
3
Production
Agenda
Topic
Introducing the Zynq®-7000 AP SoC Intelligent Drives Kit
Demo 1
Zynq IDK in Operation / Base Reference Design
Analog Devices High Performance Servo Solution
Prototype with Zynq Support Package from MathWorks ®
Demo 2
Code generation and execution on Zynq IDK
Deploy Simulink® FOC with Xilinx Vivado® Design Suite
Demo 3
Adding a custom controller to Base Reference Design
4
Motor Control
From Concept to Production
®
with Zynq -7000 AP SoC
Avnet Design Seminar
Agenda
Topic
Introducing the Zynq®-7000 AP SoC Intelligent Drives Kit
Demo 1
Zynq IDK in Operation / Base Reference Design
Analog Devices High Performance Servo Solution
Prototype with Zynq Support Package from MathWorks ®
Demo 2
Code generation and execution on Zynq IDK
Deploy Simulink® FOC with Xilinx Vivado® Design Suite
Demo 3
Adding a custom controller to Base Reference Design
6
Zynq-7000 Family Highlights
● Complete ARM®-based Processing
System
o
o
o
o
Dual ARM Cortex™-A9 MPCore™
L1, L2 Caches and On-Chip Memory
Fully Integrated Memory Controllers
I/O Peripherals (CAN, USB, Ethernet,
UART, …)
● Tightly Integrated Programmable Logic
o Used to extend Processing System
o Scalable density and performance
 30k – 440k LCs, 80 – 2,020 DSP Blocks
● Flexible Array of I/O
o Wide range of external multi standard I/O
o High performance integrated serial
transceivers
o Analog-to-Digital Converter inputs
Performance/power of an ASIC with the flexibility of an FPGA
Zynq Delivers Unprecedented Integration
DSP
DSP
● One scalable platform for all products
● Reduced BOM
● Higher reliability / better MTBF
● Lower PCB and assembly cost
8
uP
Zynq Delivers Unprecedented Performance
● Advanced algorithms require fast, deterministic processing
● Field Oriented Control (FOC) loops suffer sequential delay in MCU
● Scalable to any number of motors with no performance loss in Zynq
9
Zynq-7000 AP SoC / Analog Devices Intelligent Drives Kit
Analog Devices
Motor FMC
Avnet ZedBoard
(AD-FMCMOTCON1-EBZ)
(AES-Z7EV-7Z020-G)
● Features ZedBoard low-cost community baseboard
● Introducing ADI High Performance Servo Solution
● Leverages MathWorks® workflow for Zynq
● Xilinx solution for Motor Control and Industrial Networking
10
Zynq-7000 AP SoC / Analog Devices IDK Features
• Function
• Drive BDC, BLDC, PMSM, Stepper
motors up to 48V @ 18A
• ADI isolation for power and digital signals
• AD7401A isolated ΣΔ data converters
• XADC connection
• Dual Gigabit IEEE1588 Ethernet
• 8GB SD Card
•
Linaro®
Linux framework with Field
Oriented Controller from MathWorks
• Xilinx Vivado Design Edition voucher
• MathWorks Motor Control Design
Package (optional)
11
em.avnet.com/zynq7000idk
Base Kit
AES-ZIDK-ADI-G
$995
Analog Devices Dynamometer
● Push-button, digital control and measurement of a dynamic load to
test real-time Zynq motor control performance
● Analog Discovery™ USB oscilloscope for load signal capture and
control directly from MATLAB
em.avnet.com/zynq7000idk
Base Kit + Dynamometer
AES-ZIDK-ADI-DYNO-G
$1695
Dynamometer Block Diagram
Instrumentation
Control Toolbox
Analog Discovery
30 Pin Connector
Dynamometer Drive System
Current & Speed
Measurement
Integrated
Controller
3 Phase MOSFET
Bridge
G
Rigid Coupling
M
Zynq
Intelligent
Drives
Zynq
Intelligent
Platform
Drives
Kit
User Interface
(Keys + LCD)
Embedded Control Board
3-phase MOSFET bridge
adjusts generator load
User Interface to
change load
profiles and view
speed/current
Measure signals and control
load using Analog Discover
Module with MATLAB
13
ADI Base Reference Design – concept diagram
Processing System
Programmable Logic
Cortex™-A9
ΣΔ ADC
DMA
A
X
I
Motor
Controller
P
W
M
Isolation
User Space GUI
Application
AXI Interconnect
LINUX
Power
Inverters
Encoder
Interface
USB 2.0
AD-FMCMOTCON1
C code
HDL code
14
Motor Control
From Concept to Production
®
with Zynq -7000 AP SoC
Next Topic in the Series:
Analog Devices High Performance Servo Solution
Motor Control
From Concept to Production
®
with Zynq -7000 AP SoC
Avnet Design Seminar
Agenda
Topic
Introducing the Zynq®-7000 AP SoC Intelligent Drives Kit
Demo 1
Zynq IDK in Operation / Base Reference Design
Analog Devices High Performance Servo Solution
Prototype with Zynq Support Package from MathWorks ®
Demo 2
Code generation and execution on Zynq IDK
Deploy Simulink® FOC with Xilinx Vivado® Design Suite
Demo 3
Adding a custom controller to Base Reference Design
17
The World Leader in High Performance Signal Processing Solutions
Analog Devices
High Performance Servo Drive
Agenda
 ADI
High Performance Servo Drive
 Controller
Board
 Low Voltage Drive Board
 Signal Chain
 Dynamometer
 ADI
Reference Designs
 Support
Model - Online Customer Support Model
 Analog
Devices Wiki
 Analog Devices EngineerZone
 Zynq-7000
 Next
Steps
All Programmable SoC / ADI Intelligent Drives Kit
ADI High Performance Servo Drive
ADI High Performance Servo Drive
AD-FMCMOTCON1-EBZ

Complete drive system demonstrating efficient control of multiple motor types

Example reference designs showing how to use the control solution with Xilinx
FPGAs / SoCs and Simulink
21
• High quality power sources
• Reliable power, control, and feedback signals isolation
• Accurate measurement of motor current & voltage signals
• High speed interfaces for control signals to allow fast controller response
• Industrial Ethernet high speed interface
• Flexible control with FPGA/SoC interface
ADI High Performance Servo Drive
AD-FMCMOTCON1-EBZ
 Target
applications include
 Industrial servos and drives
 Manufacturing, assembly, and automation
 Medical diagnostic
 Surgical assist robotics
 Video surveillance and machine vision
 Power efficient drives for transportation
22
Hardware – Controller Board
ISOLATION
Analog Signals
Power
23
ISOLATION
Gb Industrial Ethernet
Interface

Compatible with all Xilinx
FPGA/SoC platforms with FMC Low
Pin Count (LPC) or High Pin Count
(HPC) connectors

Fully isolated control and feedback
signals

Current and voltage measurement
using isolated ADCs

Xilinx XADC interface

2 x Gbit Ethernet PHYs for high
speed industrial communication

Hall + Differential Hall + Encoder +
Resolver interfaces

FMC signals voltage adaptation
interface for seamless operation on
all FMC voltage levels
Hall + Differential Hall
+ Encoder + Resolver
Connectors
Digital Signals
RJ45
Connector
Position Sensors
Interfaces
(Hall + Encoder + RDC)
ISOLATION
Digital I/O Signals
DRIVE BOARD CONNECTOR
ISOLATION
Voltage
Translation
XADC Interface
ISOLATION
Voltage
Translation
Analog Signals
Voltage
Translation
Current & Voltage
Measurement
Voltage
Translation
FMC LPC / HPC
XADC
CONNECTOR
CONTROLLER BOARD
Hardware – Controller Board
24
Hardware – Low Voltage Drive Board
LOW VOLTAGE DRIVE BOARD
Digital Signals
Overcurrent & Reverse
Voltage Protection
Digital Signals
MOSFET Driver IC
Analog Signals
Current & Voltage
Analog Signals
Conditioning
Digital Signals
Digital Signals
25

Drives BLDC / PMSM / Brushed
DC / Stepper motors

Drives motors up to 48V @ 18A

Dynamic braking capability

Integrated over current and
reverse voltage protection

Current measurement using
isolated ADCs

PGAs to maximize the current
measurement input range

Bus voltage, phase currents and
total current analog feedback
signals

BEMF zero cross detection for
sensorless control of PMSM or
BLDC motors
Power
PWM
MOSFET
Bridge
Shunt
Resistors
MOTOR
CONNECTOR
DRIVE BOARD CONNECTOR
External
12V – 48V
Power
Supply
Current Measurement
ADCs
BEMF Detection for
Sensorless Control
Hardware – Low Voltage Drive Board
26
FMCMOTCON1 Signal Chain - ADC
 AD7401
Isolated Sigma-Delta Modulator
 Features

High performance isolated ADC

16-bit NMC

ENOB 13.3 bits

SNR 83dB

±2 LSB INL with 16-bit resolution

±250 mV differential analog input

−40°C to +125°C operating temperature range

5 kV rms, isolation rating (per UL 1577)

Maximum continuous working voltages

565 V pk-pk: ac voltage bipolar waveform

891 V: dc (CSA/VDE)

891 V pk-pk: ac voltage unipolar waveform
 Applications
27

Ideal for motor control and dc-to-ac inverters

Shunt resistor current feedback sensing

Isolated voltage measurement
FMCMOTCON1 Signal Chain - ADC
2
Signal Wires
 20
MHz clock input
 1 bit digital data stream output
 Digital
A
Filter for Data Reconstruction
SINC3 filter model and HDL implementation
are provided in the datasheet
 Typical filter output characteristics
 Output code: 16 bit
 Sampling rate: 78kHz
 The output code resolution and sampling rate can be controlled by
changing the filter’s model and decimation
 Polyphase interpolation filters are utilized to increase the sampling
rate of the system up to 10Msps of real data
28
FMCMOTCON1 Signal Chain
IAI,TISignal
BSignal
SignalChain
Chain
Vbus
Chain
Data
[0..15]
ΣΔ
ΣΔ
Data
Modulator
Modulator
Clock
Clock
20MHz
20MHz
SINC3 Filter
Clock
20MHz
Data
SINC3 Filter
[0..15] SINC3 Filter
RC LPF
LPF
RC
250mV
0+/.. 250mV
250mV
0+/.. 250mV
Data
Data
Amplifier
Amplifier
Power
AD8251
AD8251
+/-2.5V
0..5V
PGA
PGA
LOW VOLTAGE DRIVE IpBOARD
Power
+/-2.5V
0 .. 5V
GainSupply
0.1
Gain 11 // 22 // 44 // 88
0.05
Gain
RC Gain
LPF
0 .. 250mV ADA4084-2
Cutoff 76kHz
76kHz
Cutoff
AD7401
0 .. 250mV
ΣΔ
Modulator
ADA4084-2
ADA4084-2
12V – 48V
Amplifier
Cutoff 76kHz
Gain 0.05
Clock
Clock
20MHz
20MHz
Digital Signals
RC LPF
LPF
RC
Operational Amplifier
AD7401
AD7401
ΣΔ
ΣΔ
Digital Signals
DRIVE BOARD CONNECTOR
Signal
IAI,TIXADC
B XADC
SignalChain
Chain
XADC
XADC
XADC
ISOLATION
ISOLATION
ISOLATION
FPGA
FPGA
FPGA
AD7401
AD7401
ΣΔ
ΣΔ
Modulator
Modulator
VAUX_N
Multiplexer
Cutoff 76kHz
AD8137
Gain 0.1
Gain 1 / 2 / 4 / 8
Gain 1/6.5
Cutoff76kHz
76kHz
Cutoff
PWM
MOSFET
Bridge
Shunt
Resistors
LOW VOLTAGE DRIVE BOARD
Cutoff 100kHz
Digital Bitstream
Analog Isolation
Analog
VN
ADC Driver
Sallen Key, Cutoff 100KHz
Digital Signals
29
+/-250mV
250mV
+/Gain 1/1.85
Divider
LOW
LOW VOLTAGE
VOLTAGE DRIVE
DRIVE BOARD
BOARD
Current Measurement
Analog
AD8137
0 .. 1 V
VP
Digital Signals
Differential
Analog
0 .. 1AD8137
V Reconstruction Filter
Unipolar 0 .. 1 V
Differential
Reconstruction
Filter
Unipolar 0 .. 1 V
Multiplexer
ADCs
ADG759
Multiplexer
0
..
1
V
ADC
Driver
VN
Sallen Key, Cutoff 100KHz
Differential
ADC Driver
Reconstruction Filter
Unipolar
0 .. 1 V
VN
Sallen Key, Cutoff 100KHz
ADG759
VAUX_P
ADG759
VAUX_N
VAUX_N
VP
VP
Vbus
Shunt
Shunt
Resistor
Resistor
In
In
Resistive
Current & Voltage RC LPF
Ip Resistive
AD8207
AD8251
AD8630
RC
ADA4084-2
Ip
AD7401
ADA4084-2
AD8251
AD8207
LPF
RC LPF
LPF
ADA4084-2
RC LPF
0 .. 250mV RC
0 .. 5V 0 .. 5V
0..5V
0 .. 5V Difference
Signals
0 .. 250mV
.. 250mV
Shunt
Vbus
Analog
Signals
Amplifier 0 Analog
PGA
Amplifier
Divider
+/- 250mV
+/-100mV
Operational
Amplifier
+/-2.5V
+/-2.5V
+/-2.5V
Shunt
Amplifier
PGA
Difference
Amplifier
+/-125mV
ΣΔ
Amplifier
Resistor
In
Resistor
Conditioning
In
Cutoff 76kHz
0.05
Cutoff 100kHz
CutoffGain
76kHz
Gain
2/4/8
Gain 48.78
Gain1 /0.05
Modulator
0 .. 250mV
+/- 250mV
Digital Bitstream
Digital Bitstream
Analog
Analog Isolation
Isolation
VAUX_P
VAUX_P
Ip
RCLPF
LPF
RC
Overcurrent & Reverse
Modulator
Modulator
Voltage Protection
CONTROLLER BOARD
AD8207
AD8630
Difference Amplifier
Amplifier +/-100mV
+/-125mV
Difference
AD8207
Gain
20
Gain
48.78
Cutoff 100kHz
100kHz
Cutoff
0 .. 5V
Vbus XADC Signal Chain
MOSFET Driver IC
CONTROLLER
CONTROLLER BOARD
BOARD
+/-2.5V
0 .. 5V
MOTOR
CONNECTOR
SINC3Filter
Filter
SINC3
CONTROLLER
BOARD
External
AD7401
AD7401
ISOLATION
Data
Data
[0..15]
[0..15]
Data
Data
ISOLATION
ISOLATION
FPGA
LOW LOW
VOLTAGE
DRIVEDRIVE
BOARD
LOW VOLTAGE
VOLTAGE
DRIVE
BOARD
BOARD
CONTROLLER BOARD
BOARD
CONTROLLER
ISOLATION
ISOLATION
FPGA
FPGA
BEMF Detection for
Sensorless Control
Gain 20
Gain 1/1.85
Gain 1/6.5
Hardware - Dynamometer
Two BLDC motors connected by a rigid couple
in a dyno setup
 Electronically adjustable load
 Measurement and display of load motor phase
currents
 Measurement and display of load motor speed
and current
 External control using Analog Discovery™ USB
oscilloscope (not included) for load signal
capture and control directly from MATLAB

Analog Devices
Dynamometer
(AD-DYNO1-EBZ)
Instrumentation
Control Toolbox
Analog Discovery
30 Pin Connector
Dynamometer Drive System
Current & Speed
Measurement
Integrated
Controller
3 Phase MOSFET
Bridge
User Interface
(Keys + LCD)
30
Embedded Control Board
G
Rigid Coupling
M
Zynq Intelligent Drives
Platform
ADI Reference Designs
ADI Reference Designs
 Reference
Designs Contents
 ISE HDL Project
Control and monitoring through Chipscope
 Only manual control
 Monitoring of system important parameters
 Simple to synthetize / understand / utilize

 Vivado
HDL Project
Complex HDL blocks with AXI Lite and
AXI Streaming interfaces
 Infrastructure for Linux support
 Automatic controllers implemented in HDL
from Simulink models

 Linux
IIO Drivers
 Linux IIO Scope
 User-space application for monitoring and control
 IIO Server / Client
 Real time data acquisition and system control over TCP / UDP
 Simulink Controller Models
32
ADI Reference Design - Framework
33
ADI Reference Design – Linux IIO Drivers

The Linux Industrial I/O (IIO) subsystem is intended to provide support for
devices that, in some sense, are sampling data converters
 ADCs and DACs (like the AD7401A)
 Accelerometers, gyros, IMUs
 Capacitance-to-Digital converters (CDCs)
 Pressure, temperature, and light sensors, etc.
 RF Transceivers (like the AD9361)

Developed during 2009, committed Jan 2010, moved out of staging Nov
2011, now in all mainline Linux kernels

The IIO Divers for the motor control solution require the HDL cores to have
a specified register map

A DMA interface is set up for high speed data transfer using multiple
multiplexed data channels
34
IIO Scope for Real Time Data Visualization
 Runs

directly on Xilinx Zynq
HDMI monitor, USB Keyboard/Mouse
 Visualize

data:
Frequency

simple and complex FFT
Time Domain
 Constellation (I vs Q)

 Capture
data:
Save sequences to file
 Supports different formats

 Change
/ read back device
configuration
35
ADI Reference Design - Matlab IIO Client
 ADI
IIO Command Server
Runs on an embedded target
under Linux
 Manages real-time data exchange
over TCP or UDP between the
target and a remote client
 Data Exchange is based on a
simple communication protocol

 Matlab
IIO Client
Implements the communication
protocol with the IIO Server
 Based on the UDPReceiver /
UDPSender classes from the
Mathworks DSP toolbox
 Controls the embedded target
using specific commands
 Acquires real-time data from the
embedded target

36
Support Model - Online Customer
Support Model
ADI Servo Drive Support Model

ADI parts
 Datasheets & Documentation
 Design tools and models
 Evaluation kits, Symbols and Footprints
 Sample & Buy
PCB Schematics, Gerbers, BOM
 HDL
 Applications and Drivers for Linux and No-OS
 Simulink controller models
analog.com


Online support via EngineerZone
 Data Converters Community
 Interface and Isolation Community
 Power Management Community
 FPGA Reference Design Community
 Linux and Microcontroller Devices Drivers Community
wiki.analog.com
ez.analog.com
ADI Servo Drive Documentation on Wiki
39
Community Support On EngineerZone
40
Zynq-7000 AP SoC / ADI Intelligent Drives Kit

What’s included








41
Avnet ZedBoard 7020 baseboard
Xilinx Vivado™ Design Edition voucher
Analog Devices AD-FMCMOTCON1-EBZ
Module
8 GB SD card programmed with the ADI
Ubuntu Linux image including drivers and
applications software
HDL and software source code, reference
designs, full schematics and gerbers
Brushless DC motor: 24 V, 4000 RPM, Hall
sensors and 1250 CPR indexed encoder
MathWorks Motor Control Design Package
(optional)
Dynamometer dynamic load to test Zynq
motor control performance with interface to
MATLAB® (optional)
+
(optional)
Next Steps

Go ot wiki.analog.com/resources/eval/user-guides/ad-fmcmotcon1-ebz to
learn more about the Analog Devices High Performance Servo Drive and
download the hardware design files and reference designs

Go to ez.analog.com to get answers for any questions that you might have
related to the ADI High Performance Servo Drive hardware and reference
designs

Visit www.em.avnet.com/zynq7000idk to learn more about the Xilinx Zynq /
ADI Intelligent Drives Kit and purchase the kit

Visit mathworks.com/zidk to learn about MathWorks support for the Xilinx
Zynq / ADI Intelligent Drives Kit and for more information about the
MathWorks workflow for Xilinx Zynq-7000 All-Programmable SoCs

Visit www.zedboard.com to view the entire Zynq Motor Control Seminar
42
Zynq Intelligent Drives Kit = Full Prototype Platform
● Flexible development platform for high performance
motor control applications on Zynq-7000 AP SoC
● Analog Devices isolated precision signal chain
● ADI Base Reference Design with Desktop Linux UI
● Leverages MathWorks
workflow for Zynq
43
ADI Base Reference Design – concept diagram
Processing System
Programmable Logic
Cortex™-A9
ΣΔ ADC
DMA
A
X
I
Field
Oriented
Controller
P
W
M
Isolation
User Space GUI
Application
AXI Interconnect
LINUX
Power
Inverters
Encoder
Interface
USB 2.0
AD-FMCMOTCON1
C code
HDL code
44
ADI Base Reference Design – detailed diagram
Processing System
Programmable Logic
Cortex™-A9
DMA
A
X
I
ADC
ΣΔ ADC
(Ia, Ib, Vbus)
User Application
UART
DMA
DMA
Ethernet
Your
Field
Custom
Oriented
Controller
Controller
A
X
I
P
W
M
Encoder
(Position,Speed)
Power
Inverters
Encoder
Interface
AD-FMCMOTCON1
USB 2.0
DMA
C code
A
X
I
Isolation
IIO Scope
AXI Interconnect
Desktop
LINUX
A
X
I
HDMI
HDL code
45
Moving from Simulink to Zynq
Simulation
Prototype
Production
Zynq Intelligent
Drives Kit
Base Reference
Design
46
Motor Control
From Concept to Production
®
with Zynq -7000 AP SoC
Next Topic in the Series:
Prototype with Zynq Support Package from MathWorks ®
Demo 2
Code generation and execution on Zynq IDK
Agenda
Topic
Introducing the Zynq®-7000 AP SoC Intelligent Drives Kit
Demo 1
Zynq IDK in Operation / Base Reference Design
Analog Devices High Performance Servo Solution
Prototype with Zynq Support Package from MathWorks ®
Demo 2
Code generation and execution on Zynq IDK
Deploy Simulink® FOC with Xilinx Vivado® Design Suite
Demo 3
Adding a custom controller to Base Reference Design
48
MathWorks Landing Page
www.mathworks.com/avnetmotor
49
Moving from Simulink to Zynq
Simulation
Prototype
Production
Zynq Intelligent
Drives Kit
Base Reference
Design
50
Some components of a production application
Production
ARM
Algorithm
C
Linux
Driver
System
Code
AXI Bus
AXI
Interface
Algorithm
HDL
IP1
IP2
IP3
Programmable Logic
Motor
51
System
From simulation to production
Production
Simulation
Simulink
Algorithm
Model
ARM
Embedded Coder
Algorithm
C
Linux
Driver
System
Code
AXI Bus
Algorithm
Model
AXI
Interface
HDL Coder
Algorithm
HDL
IP1
IP2
IP3
Programmable Logic
Motor
Model
Motor
52
System
From simulation to prototype to production
Simulation
Prototype
Simulink
ARM
Algorithm
Model
Algorithm
Model
Embedded Coder
HDL Coder
ARM
Algorithm
C
Vivado
Algorithm
C
Linux
Driver
Linux
Driver
AXI Bus
AXI Bus
AXI
Interface
AXI
Interface
Algorithm
HDL
Algorithm
HDL
Prog. Logic
Motor
Model
Production
Vivado
53
IP1
IP2
IP3
Programmable Logic
Motor
Motor
System
Code
System
DEMO1: Simulate Six-step Controller
54

Specify tests and
simulate response
with continuous time
solver

Model motor and
load with fidelity to
capture dynamics of
interest

Model control loop
C/HDL components
How do I get from simulation to prototype?
Processing System
Programmable Logic
Motor FMC Card
Algorithm HDL
PWM
Six-Step
Specification
Model
Commutation
Velocity Estimate
Open-source
LINUX
AXI-lite
Algorithm C
Velocity Control
Specification
Model
Hall
Period
Ethernet
55
Isolation
Cortex™-A9
Inverter
Module
Hall
Interface
Generate a bitstream for programmable logic
Programmable Logic
AXI-lite
Algorithm HDL
Specification Model
Zynq Support Package enables you to…
 Generate bitstream consisting of algorithmic HDL code from models
and interfaces to FPGA pins and AXI-Bus
56
Generate an executable for ARM
Processing System
Cortex™-A9
AXI-lite
Algorithm C
Specification Model
Zynq Support Package enables
you to…
 Generate ARM executable
consisting of algorithmic C code
from models and interfaces to
AXI-Bus
Open-source
LINUX

Algorithm C code executes in the
user space of Linux

AXI4-Lite SW driver is
automatically created and
inserted
57
Generate an executable for ARM
Processing System
Cortex™-A9
AXI-lite
Algorithm C
Specification Model
Open-source
LINUX
Ethernet
Zynq Support Package enables
you to…
 Generate ARM executable
consisting of algorithmic C code
from models and interfaces to
AXI-Bus
 Provides data interface between
Simulink and ARM executable via
Ethernet
58
DEMO2: Prototype on Zynq with interactive tests
Switches and scopes in Simulink model act as an
interface to generated executable running on ARM
Algorithm C
Specification Model
Algorithm HDL
Specification Model
Algorithm
C
60
Motor FMC Card
Isolation

Inverter
Module
Hall
Interface
Simulation Phase
● Models designed for simulation
● Algorithm, stimulus, and analysis run in Simulink
● Motor and plant peripherals are simulated
61
Prototype Phase
● Models designed for code generation
● Test bench stimulus and analysis run in Simulink
● Simulink algorithm is converted to code and runs on Zynq
● Interface to hardware motor and plant peripherals
62
How can models help you prototype on Zynq?
Simulation
Prototype
Simulink
ARM
Algorithm
Model
Embedded Coder
Zynq Support Package
Algorithm
C
Linux
Driver
● Automates integrating
generated C code with an
ARM “parent project”
AXI Bus
Algorithm
Model
AXI
Interface
HDL Coder
Algorithm
HDL
Prog. Logic
Motor
Model
● Automates wrapping
generated HDL code into an
IP Core and integrating it
with “parent project” for
programmable logic
● Provides a data interface
Motor
between Simulink and ARM
63
Algorithmic code is reused in production
Simulation
Prototype
Simulink
ARM
Algorithm
Model
Embedded Coder
Algorithm
C
Production
Algorithm
C
Linux
Driver
AXI Bus
Algorithm
Model
AXI
Interface
HDL Coder
Algorithm
HDL
Prog. Logic
Motor
Model
Motor
Algorithm
HDL
Generate C and HDL for algorithms
Algorithm C Specification Model
Generates C code for the algorithm
(i.e. function call) that you can integrate
into your production project
Algorithm HDL Specification Model
Generates HDL code for the algorithm
(i.e. entity) that you can integrate into your
production project
65
How can models help you design a controller for Zynq?
● Simulate on your desktop
o Model controller and plant system dynamics
o Design and debug components at control loop fidelity
o Assemble and verify components at implementation fidelity
● Prototype on hardware
o Generate HDL code and build bitstream
o Generate C code and build ARM executable
o Collect hardware results and verify against simulation
● Generate C/HDL code for production
o Generate and review HDL code report
o Generate and review C code report
o Integrate generated code with production environment
66
Motor Control
From Concept to Production
®
with Zynq -7000 AP SoC
Next Topic in the Series:
Deploy Simulink® FOC with Xilinx Vivado® Design Suite
Demo 3
Adding a custom controller to Base Reference Design
Motor Control
From Concept to Production
®
with Zynq -7000 AP SoC
Avnet Design Seminar
Agenda
Topic
Introducing the Zynq®-7000 AP SoC Intelligent Drives Kit
Demo 1
Zynq IDK in Operation / Base Reference Design
Analog Devices High Performance Servo Solution
Prototype with Zynq Support Package from MathWorks ®
Demo 2
Code generation and execution on Zynq IDK
Deploy Simulink® FOC with Xilinx Vivado® Design Suite
Demo 3
Adding a custom controller to Base Reference Design
69
Let’s Take Breath … What Have We Done?
Processing System
Programmable Logic
Motor FMC Card
Algorithm HDL
PWM
Six-Step
Specification
Model
Commutation
Velocity Estimate
Open-source
LINUX
AXI-lite
Algorithm C
Velocity Control
Specification
Model
Hall
Period
Ethernet
70
Isolation
Cortex™-A9
Inverter
Module
Hall
Interface
Automation Comes at a Cost …
● Automated prototyping locks the tool flow and BSP
Simulation
Prototype
Production
● Production deployment requires flexible tool flows
71
Algorithmic Code is Reused in Production
Production
Simulation
Simulink
Algorithm
Model
ARM
Embedded Coder
Algorithm
C
Linux
Driver
System
Code
AXI Bus
Algorithm
Model
AXI
Interface
HDL Coder
Algorithm
HDL
IP1
IP2
IP3
Programmable Logic
Motor
Model
Motor
72
System
Vivado Design Suite Accelerates Productivity
Comprehensive SoC Design Software
•
IP and System-centric Integration
•
Fast, Hierarchical and Deterministic Closure
Industry standard constraint languages
•
IP-XACT for IP packaging & integration
•
TCL scripting to automate all details
•
XDC / SDC constraints language
Tight integration with Xilinx SDK
•
Embedded software development and debug
73
Parallel Development on Zynq AP SoC
SDK
Vivado
Hardware Development
• Standard FPGA development
Software Development
• Standard ARM processor
development
• Design/debug using Vivado
• Design/debug using Xilinx SDK or
other standard SW over JTAG
• Load Programmable Logic via
JTAG without PS during
development phase
• Programmable Logic need not be
programmed
74
Vivado IP Packager
Enabling Reuse and Delivering Fully Functional IP Subsystems
IP Packager
 Source (C, RTL, IP)
 Simulation models
 Documentation
 Example Designs
 Test bench
Standardized IP-XACT
IP Subsystem
Xilinx IP
3rd Party IP
User IP
 Uses multiple plug-and-play forms of IP to
implement functional subsystem
 Includes software drivers and API
 Accelerates integration and productivity
Vivado IP Integrator
● Accelerates hardware design
productivity through design reuse
o Graphical IP assembly
o Correct-by-construction
o System centric
● Generates IP subsystems
o Supports multiple plug-and-play
IP formats
o Generates software drivers and
APIs
● Board and silicon aware
o Built in support for Xilinx
development baseboards
Page 76
Vivado IP Catalog - Standardized IP-XACT
Subsystems
Xilinx
3rd Party
User
Demo: FOC Simulink Controller in WebView
77
ADI Base Reference Design – detailed diagram
Processing System
Programmable Logic
Cortex™-A9
DMA
A
X
I
ADC
ΣΔ ADC
(Ia, Ib, Vbus)
Algorithm C
UART
DMA
DMA
Ethernet
Field
Algorithm
Oriented
HDL
Controller
A
X
I
P
W
M
Encoder
(Position,Speed)
Power
Inverters
Encoder
Interface
AD-FMCMOTCON1
USB 2.0
DMA
C code
A
X
I
Isolation
IIO Scope
AXI Interconnect
Desktop
LINUX
A
X
I
HDMI
HDL code
78
MathWorks HDL Peripheral with AXI-Lite Interface
AXI Interconnect
Programmable Logic
AXI-Lite Wrapper
Algorithm
HDL
● Generate HDL code with AXI-Lite interface
● Includes algorithm plus AXI-Lite register logic
● Integrate within Vivado top-level project
79
Add HDL Code as AXI-Lite IP in Vivado Design Suite
IP Packager
Vivado IP Integrator
PL bitstream (.bit)
AXI Interconnect
HDL Code
Vivado Project
80
Programmable Logic
AXI-Lite Wrapper
Algorithm
HDL
Add C Code in Xilinx Software Development Kit
SD Card
Xilinx SDK
PL bitstream
Boot.bin
FSBL + U-Boot
User Space Application
.ELF
Root File
System
DeviceTree (.dtb)
Processing System
LINUX
User Application
Linux Kernel
AXI Interconnect
C Code
Boot
SD
Card
81
LINUX
Algorithm C
User Space
Application
UIO
Driver
Interconnect
AXI
AXIInterconnect
SW / HW Integration of Simulink model in Zynq
AXI-Lite Wrapper
Algorithm
HDL
● Reuse MathWorks generic UIO driver or provide custom
peripheral driver
● Automated build processes are possible with MATLAB
and TCL scripting
82
Agenda
Topic
Introducing the Zynq®-7000 AP SoC Intelligent Drives Kit
Demo 1
Zynq IDK in Operation / Base Reference Design
Analog Devices High Performance Servo Solution
Prototype with Zynq Support Package from MathWorks ®
Demo 2
Code generation and execution on Zynq IDK
Deploy Simulink® FOC with Xilinx Vivado® Design Suite
Demo 3
Adding a custom controller to Base Reference Design
83
Demo 3: Deploying to Zynq with Vivado
● Adding a custom HDL module to Base Reference Design
84
Adding SW to the ADI Base Reference Design
Processing System
Programmable Logic
Cortex™-A9
DMA
A
X
I
ADC
ΣΔ ADC
(Ia, Ib, Vbus)
User Application
UART
A
X
I
DMA
Ethernet
A
X
I
P
W
M
Encoder
(Position,Speed)
Power
Inverters
Encoder
Interface
AD-FMCMOTCON1
USB 2.0
DMA
C code
Field
Oriented
Controller
Isolation
IIO Scope
AXI Interconnect
Desktop
LINUX
A
X
I
HDMI
HDL code
85
LINUX
Algorithm C
UIO
Driver
User Space
Application
Interconnect
AXI
AXIInterconnect
Adding SW to the ADI Base Reference Design
AXI-Lite Wrapper
Algorithm
HDL
● Add custom C code application
● Use MathWorks generic UIO or a custom driver
● Update Device Tree
86
What You’ve Seen Today
● Zynq Intelligent Drives Kit is flexible development platform for
high performance motor control applications
● Analog Devices production grade Linux reference design with
FMCMOTCON1 high performance servo module
● The MathWorks Zynq workflow enables rapid prototype on the
Xilinx Zynq®-7000 All Programmable SoC
● Deploying Simulink models into Zynq-based motor control
using Xilinx Vivado® Design Suite
87
Next Steps
Purchase the Zynq Intelligent Drives Kit
with MathWorks Motor Control Design
Package
o em.avnet.com/zynq7000idk
Download Analog Devices Reference
Designs
o wiki.analog.com
o Full C/HDL/Linux source
Explore Zynq Support Packages and
Simulink Motor Control Models
o www.mathworks.com/zidk
88
Motor Control Design Package from MathWorks
Includes
MATLAB,
Simulink and
10 products
● Complete turnkey solution for motor control algorithm
development, including C and HDL code generation and target
support for the Zynq-7000 AP SoC.
● Order with the Zynq Intelligent Drives Kit
● AES-ZIDK-ADI-DYNO-G-MATW-ANUL
89
$19,215 USD
THANK YOU!
90