Allegro Quick‐Place Utility
g
y
Pre‐Placement
Pre
Placement Strategy
Strategy
‐Venkata Ramanan
Effective Date: 01OCT2009
1 | Infinera Confidential & Proprietary
PPT‐INFN‐01‐001‐1009‐01
Objective
•
•
•
•
•
•
•
Scope of this Presentation
Scope
of this Presentation
T diti
Traditional Placement Method
l Pl
t M th d
Disadvantages of Existing Method Introducing QuickPlace Tool
Functionality
Limitations and FAQs
Limitations and FAQs
S
Summary
2 | Infinera Confidential & Proprietary
Scope Of This Presentation
Scope Of This Presentation
• This
This presentation lists the current method of pre‐
presentation lists the current method of pre
placement on PCB designs
placement on PCB designs
• Explains the pitfalls and drawbacks
E l i th itf ll
dd
b k
• Introduces the new QuickPlace Tool developed at Infinera
• Explains the Functionality and the Rational
• This tool will be used by PCB Designers and Board level This tool will be used by PCB Designers and Board level
Engineers
3 | Infinera Confidential & Proprietary
Traditional Placement Method
Traditional Placement Method
• Cadence
Cadence Allegro Provides a Quick place tool which will Allegro Provides a Quick place tool which will
place all the components to any side of the PCB outline
place all the components to any side of the PCB outline
4 | Infinera Confidential & Proprietary
Disadvantages of Existing Method
Disadvantages of Existing Method
• A
A typical large scale design at Infinera has multiple typical large scale design at Infinera has multiple
Hierarchy and numerous sub‐designs
Hierarchy and numerous sub
designs
• It is quite common to have more than 150 pages of It is quite common to have more than 150 pages of
schematics
• Any given component on a particular page has an Any given component on a particular page has an
underlying requirement to be placed near its circuitry
underlying requirement to be placed near its circuitry
• This requirement drives the Engineer to group them by This requirement drives the Engineer to group them by
pages and by connectivity
pages and by connectivity
• It is highly impractical to assign ROOM property to all It is highly impractical to assign ROOM property to all
circuitry in all the pages
circuitry in all the pages
5 | Infinera Confidential & Proprietary
Disadvantages of Existing Method cont
Disadvantages of Existing Method ‐
• A
A typical large scale PCB layout starts by placing all the typical large scale PCB layout starts by placing all the
components on the side of the board outline
• Then either with the help of a hard copy of schematic or by using Concept the components are grouped by page by i C
t th
t
db
b
page
• For a component count of 5000 plus this could take days For a component count of 5000 plus this could take days
before this initial grouping is done
• After placing them there is no easy way to track or review a group of components from a the same circuitry from f
f
h
f
schematic to Layout
schematic to Layout
• It is difficult to identify the parent page of a given set of It is difficult to identify the parent page of a given set of
components
p
6 | Infinera Confidential & Proprietary
Introducing QuickPlace Tool
Introducing QuickPlace Tool
• By
By Using the Skill language a QuickPlace tool has been Using the Skill language a QuickPlace tool has been
developed in Infinera
developed in Infinera
• This will expedite the Initial Placement grouping and Thi ill
dit th I iti l Pl
t
i
d
will cut‐down days of work to minutes
ill t d
d
f
kt
i t
• This tool also will provide an interface similar to the Concept HDL’s Hierarchical View • This will help in highlighting a particular Page/Hierarchy or a single component on the Layout with respect to the Parent Schematic
7 | Infinera Confidential & Proprietary
Functionality
• The
The QuickPlace tool will place all QuickPlace tool will place all
the components with respect to
the components with respect to its top hierarchy then its page
its top hierarchy, then its page
• The components inside the Th
t i id th
pages are sorted by their size
t d b th i i
• This tool does not care about the logical page number assigned by Concept HDL
8 | Infinera Confidential & Proprietary
Functionality
• The
The Hierarchy browser will list Hierarchy browser will list
all the pages/hierarchies and
all the pages/hierarchies and their underlying
their underlying pages/components
• By selecting them the respective B
l ti th
th
ti
components/Pages will be t /P
ill b
hi hli ht d
highlighted
9 | Infinera Confidential & Proprietary
Functionality
• This
This hierarchy hierarchy
view in the
view in the layout is similar
layout is similar to that of in the
to that of in the schematic. schematic
• It helps in It h l i
efficient cross ffi i t
probing
bi
10 | Infinera Confidential & Proprietary
Functionality
• Selecting
Selecting a logical a logical
page under a
page under a Hierarchy will
Hierarchy will highlight all the
highlight all the components in that
components in that page. page
11 | Infinera Confidential & Proprietary
Functionality
• Selecting
Selecting a single a single
component will make
component will make the allegro to zoom in
the allegro to zoom in to that particular
to that particular component
12 | Infinera Confidential & Proprietary
Limitations and FAQ
Limitations and FAQ
• The
The Pages listed under the hierarchy are logical page Pages listed under the hierarchy are logical page
numbers not the physical
numbers not the physical
• Hierarchical page names are not the same as that Hi
hi l
t th
th t
viewed in the HDL, But it is easy to identify.
i
d i th HDL B t it i
t id tif
• The Pages are sorted by the amount of components in them not the same sequence as that of the schematic
13 | Infinera Confidential & Proprietary
FAQ
• What is the Rational?
What is the Rational?
– In
In a large scale PCB layout after the initial netin , the layout engineer a large scale PCB layout after the initial netin the layout engineer
spends a considerable amount of time just grouping the components together w.r.to their page. This can lead to days of productive time spent on just grouping. This tool eliminates that initial time spent
j t
i Thi t l li i t th t i iti l ti
t
• Why ?
Wh ?
– B
By using the inbuilt quick‐place there is no way to track a particular i
h i b il
i k l
h
i
k
i l
component or a group of components to its parent schematic page
component or a group of components to its parent schematic page
– These are very much manual process and not efficient
y
p
• How Quick is this Tool?
How Quick is this Tool?
– It can place/group a 9000+ components w.r.to hierarchy and underlying p
/g p
p
y
y g
pages under 80 seconds
14 | Infinera Confidential & Proprietary
FAQ
• Who will use this?
Who will use this?
– A
A Layout engineer for initial quick place
Layout engineer for initial quick place
– Layout Engineer/Board Engineer to quickly review components that should Layout Engineer/Board Engineer to quickly review components that should
be placed w.r.to their parent schematic locations
• How this tool is developed?
p
– This tool is developed at Infinera and coded in Cadence Skill language
– Skill is similar to Lisp and C.
– This tool will work only under Cadence Allegro
• What it is Not
– This is not a solution for everything, still the layout engineer and the board engineer should review the placement and relative locations
engineer should review the placement and relative locations
15 | Infinera Confidential & Proprietary
Summary
• This
This is another set of tool that would help engineers to is another set of tool that would help engineers to
manage the layout in an efficient manner
manage the layout in an efficient manner
• Your comments and suggestions are Welcome
– Regards
– Venkata Ramanan
16 | Infinera Confidential & Proprietary