Student involved
Advisor
Project Name
Design Name
Design Password
Project ID #
Run #
Area used
Technology
# of parts received
# of parts tested
# of parts functional
Equipment
Keliu Shu
Dr. Edgar Sanchez-Sinencio
2-GHz monolithic fractional-N frequency synthesizer
PLL_SHU_TAMU
keliu1990
63359
T1AA-AB (Submitted Oct 26, 2001, Received Jan 29, 2002)
4 square mm
TSMC 0.35um CMOS, code SCN4ME_SUBM
40
4
3
1) Loop filter -- HP89410A vector signal analyzer (DC ~ 10MHz)
2) Prescaler – Agilent E4432B 250kHz ~ 3GHz series signal
generator and Agilent Infiniium 500 MHz Oscilloscope
3) PLL -- Agilent 33250A 80MHz function / arbitrary waveform
generator, Rohde & Schwarz FSEB30 20Hz ~ 7GHz Spectrum
analyzer
Chip Test Report:
1) The testing of prescaler and loop filter has been finished. The measured maximum
operating frequency of the prescaler is less than originally simulated. This is partly
due to the process variation, because the simulation with new spice parameter differs
pretty much from the old one.
2) The testing results of loop filter agrees well with simulated results, considering the
capacitance per area increases by 10% compared with old runs.
3) The testing of whole PLL is still going on.
4) As I mention on the report to MOSIS, the RF input pad without ESD is easy to be
damaged during testing.
Original proposal attached:
Frequency synthesizer in TSMC 0.35um CMOS
A Research/Educational Proposal
Analog and Mixed-Signal Center
Department of Electrical Engineering
Texas A&M University
College Station, TX, 77840
1. Goals of the Projects
Frequency synthesizers are widely used as local oscillators for frequency translation in
wireless communication systems. With the advance of process and communication
technology, wireless communications are pushed to ever-high frequencies. DCS1800 and
DECT standards use about 2GHz. Wireless LAN standard 802.11b uses 2.4GHz RF
spectrum and both IEEE 802.11a and HiperLAN use 5GHz frequency range.
With the evolution from 2G to 3G mobile communications, the backward compatibility is
a big concern. A transceiver that meets multi-standard challenges the design of the local
oscillator, i.e., the frequency synthesizer. This project involves the design of a sigmadelta PLL-based 2-GHz frequency synthesizer for DCS1800, DECT and UMTS.
One of the main difficulties in designing the several GHz transceivers is to design the
PLL-based frequency synthesizer. In the frequency synthesizer, two blocks are running at
the highest frequencies, i.e., the VCO and the prescaler. For the VCO, we are more
concerned about its phase noise requirement. For the prescaler, we are concerned its
upper limit of operation frequency.
This proposal addresses the above problem and wants to achieve the following goals:
• Design of frequency synthesizer for multi-standard transceiver.
• Investigate the relationship between sigma-delta quantization noise and PLL phase
noise and provide design guidelines.
• Improved phase switching prescaler, which makes it much simpler and reliable.
• Fully integrated VCO.
2. Background of the Applicants
Keliu Shu is currently a Ph.D. Student at the Analog and Mixed-Signal Center of Texas
A&M University. He received the BS and MS degrees in electrical engineering with
special area of analog and digital IC design before he joined the Ph.D. program in fall
1998. He worked as an intern at Texas Instruments during May to Dec. 2000. He has
been working on RF circuits, especially PLL-based frequency synthesizer since his Ph.D.
study.
3. Project Descriptions
Fractional-N frequency synthesis has several advantages over integer-N frequency
synthesis. First, its frequency resolution is lower than the reference frequency. Second,
With higher reference frequency and lower N, the in-band phase noise is lower. Third,
Faster frequency switching speed and reduced phase noise contributed by VCO can be
achieved because of wider loop-bandwidth. The disadvantage of fractional-N frequency
synthesis is "fractional spurs" in the output due the periodical change of modulus control
signal.
The principle drawback of fractional-N synthesis is the existence of "fractional spurs" at
the output. There are several techniques to reduce the fractional spurs, such as phase
interpolation and Wheatly random jittering. However, device mismatches limit the
accuracy of these cancellations. Sigma-delta modulation is used to realize fractional-N
synthesis with spurious-free output with simplicity and reduced cost.
The conventional prescaler uses a synchronous divide-by-4/5 counter as the first stage.
The 3 flip-flops used in this stage work at the highest input frequency and consume much
power. More importantly, compared with divide-by-2 logic this stage can only work at
much lower input frequency. Phase switching technique was first proposed in to tackle
this problem. In the phase switching prescaler, only one divide-by-2 FF works at the
highest input frequency, so a prescaler with the same speed as an asynchronous divider
can be obtained. Compared to another newly developed technique, ILFD, the phase
switching technique doesn't have the disadvantage of small input bandwidth, sensitive to
process variation and non-programmable.
Although the traditional phase switching prescaler has the above pros over other
approaches, it may suffer from glitches. These glitches can cause the following counter to
miscount. Various efforts have been made to remove the glitches in the literature. One
approach uses a long rise time MUX control signal, but it's not robust. The other uses
feedback from MUX, but it reduces the operation speed. The third approach uses a
synchronizing flip-flop (SFF) to retime MUX control signal. The fourth approach a
retiming circuit, which increases the circuit complexity and costs more power. An
improved phase switching technique is proposed. By changing the switching direction, an
inherently glitch-free phase switching is achieved without any additional circuit for
retiming or synchronization. The phase switching is made between the 45° spaced output
phases to further reduce the power consumption and improve the robustness of circuit
operation.
Due to the high output frequency of this frequency synthesizer, large-scale process like
1.2µm or 0.5µm will limit the VCO and prescaler operation speed due to low f T . Thus,
the access to a small-scale process such as 0.35µm would allow us to obtain a
competitive performance of the frequency synthesizer. Another goal of this project is to
demonstrate that CMOS process can be used to design high-frequency low-noise
frequency synthesizers. Currently, most of high-frequency low-noise frequency
synthesizers are fabricated using bipolar or Bi-CMOS technology, or with discrete VCOs
and prescalers.
3.1 Simulation and Layout Plans
First, the system level design is carried by using MatlabTM and Spectre HDLTM. The goal
is to decide system design parameters, and obtain the specifications of the different
blocks in the PLL. In the system level simulation we have tried to include possible nonidealities caused by the process variation, like the mismatch, etc.
The transistor level design will be simulated using Spectre (a CADENCETM tool). This
will be done using SPICE model parameters provided by MOSIS for the 0.35µm
technology. At this stage, the difference between required specifications and simulated
results should be justified. Monte Carlo simulation is also required to ensure that the
design is robust enough to meet the specifications under normal manufacturing process
variations. This will provide us with an estimated distribution of the values so the most
important specifications as a function of the statistically varying device model
parameters.
Next, a layout of the final design will be created using the Virtuoso Environment of
CADENCETM. Good layout techniques such as common-centroid and symmetric
arrangements and dummy transistors should be used for better matching. The LVS
(Layout vs. Schematic) check tool of CADENCETM will be used to ensure that both the
extracted layout and the schematic are matched. In this stage we should perform postlayout simulation of the design using the extracted layout including the parasitic rather
than the circuit schematic used in the first stage. This will give us a prediction of the
effect of the parasitic on the performance of the design.
The estimated chip area is around 2 ×2mm 2 .
3.2 Test Plans
The test includes the operation frequency of the improved prescaler and its residue phase
noise, the phase noise of the integrated VCO and the whole synthesizer. Process and
design parameters affecting the performance of the synthesizer will be identified.
Student(s) involved
Keliu Shu:
Frequency synthesizer
Professor(s) involved
Dr. Edgar Sanchez-Sinencio