SIM UNIVERSITY
SCHOOL OF SCIENCE AND TECHNOLOGY
DESIGN A SIMPLE PIANO
USING FPGA
STUDENT
: J0706297
SUPERVISOR
: MR MAK LIN SENG
PROJECT CODE : JUL2010/ENG/061
A project report submitted to SIM University
in partial fulfilment of the requirements for the degree of
Bachelor of Electronics Engineering
May 2011
Lim Zheng Yong
J0706297
Design A Simple Piano Using FPGA
ABSTRACT
Musical instruments have always been the essential tools for composing enchanting
music and songs. As electronics technologies evolved over the decades, electronics
invention has beginning to replace conventional analogue instrument. Musical
instruments are so complex and that many alternations are possible.
The purpose of this project is to design a simple piano that can produce the basic musical
notes through FPGA. FPGA (Field Programmable Gated Array) is one of the advanced yet
sophisticated technologies. The behaviour of the FPGA can be defined by hardware
description language (HDL). The two most common HDLs are VHDL and Verilog.
This project, which is called the Simple Piano, has both software and hardware
involvement. The essential equipments needed for the digital piano are keyboard, speaker,
Xilinx Spartan-3AN board and the ISE programmer.
This report describes the architecture of the digital piano by looking into the design and
implementation of each individual module such as UART module, PS2 module, map
module, UCF module and sound module.
This report also explains the planning, software testing, hardware testing and debugging of
the digital piano. The entire design is written in VHDL code and simulated on Xilinx ISE
Design Suite 10.1 and ISE simulator.
This report finalises on the summary, recommendations for future work and development
for the project.
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Design A Simple Piano Using FPGA
ACKNOWLEDGEMENT
First of all, I would like to thank my family and my partner for encouraging me to further
my studies to a Bachelor’s Degree level despite enduring financial difficulties and
missing a lot of my love and time dedicating to them.
I would like to express my sincere gratitude to the project supervisor, Mr Mak Lin Seng
for his invaluable advice and guidance throughout the project. He has always been
approachable and kind. He is clear about the project objective and advises on the project
requirements.
I would like to thanks my department head Mr Yeo Eng Choon, and my senior engineer
Mr Henry Foo, for allowing me to take early time off and extended leaves for my studies
and examinations.
I would also like to extent my gratitude to the AVNET field engineer, Mr Felix.
Finally, I would like to thanks those who have given comments for this project.
Thank you.
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TABLE OF CONTENTS
ABSTRACT ............................................................................................................................................ i
ACKNOWLEDGEMENT .................................................................................................................... ii
TABLE OF CONTENTS..................................................................................................................... iii
LIST OF FIGURES ............................................................................................................................. iv
LIST OF TABLES ................................................................................................................................ v
1
INTRODUCTION........................................................................................................................ 1
1.1
1.2
1.3
1.4
BACKGROUND AND MOTIVATION ................................................................................... 1
OBJECTIVES OF THE PROJECT ........................................................................................... 1
PROJECT SCOPE..................................................................................................................... 2
REPORT ORGANIZATION .................................................................................................... 2
REVIEW OF THEORY AND PREVIOUS WORK ................................................................. 3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
OVERVIEW OF A MUSICAL PIANO .................................................................................... 4
FPGA IMPLEMENTATION .................................................................................................... 5
ADVANTAGES OF FPGA ...................................................................................................... 6
MUSICAL NOTES AND TONES............................................................................................ 7
OVERVIEW OF APPROACH AND METHOD ...................................................................... 7
REVIEW OF FPGA DEVELOPMENT KIT SELECTION ..................................................... 8
OVERVIEW OF VHDL AND VERILOG ............................................................................. 12
PROJECT PLANNING............................................................................................................. 13
4
HARDWARE AND MEMORY REQUIREMENTS .............................................................. 16
2
4.1
4.2
4.3
HARDWARE DESIGN AND DEVELOPMENT .................................................................. 16
PS2 KEYBOARD ................................................................................................................... 19
SPEAKER ............................................................................................................................... 23
DESIGN IMPLEMENTATION ENVIRONMENT ............................................................... 24
5.1
5.2
5.3
5.4
5.5
5.6
5.7
FPGA....................................................................................................................................... 24
XILINX ISE SOFTWARE ...................................................................................................... 24
MODELSIM STUDENT EDITION v10.0a............................................................................ 24
HDL LANGUAGE.................................................................................................................. 25
PLANAHEAD ........................................................................................................................ 25
iMPACT .................................................................................................................................. 25
FSM ......................................................................................................................................... 25
DESIGN IMPLEMENTATION ............................................................................................... 27
6.1
6.2
6.3
6.4
6.5
6.6
6.7
SIMPLE PIANO OVERVIEW ............................................................................................... 28
XILINX SPARTAN3AN CONFIGURATION MODE .......................................................... 29
UART SYSTEM .................................................................................................................... 29
PS2 MODULE ........................................................................................................................ 29
SOUND MODULE ................................................................................................................. 31
TOP MODULE ....................................................................................................................... 31
COMPILING AND TARGETING OF VHDL CODE ........................................................... 31
CONCLUSIONS AND RECOMMENDATIONS ................................................................... 34
5
6
7
7.1 CONCLUSIONS ....................................................................................................................... 34
7.2 RECOMMENDATIONS .......................................................................................................... 34
8
REFLECTION ........................................................................................................................... 35
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REFERENCES .................................................................................................................................... 37
GLOSSARY......................................................................................................................................... 40
APPENDIX A: SOURCE CODE....................................................................................................... 42
A.1 UART.vhd................................................................................................................................... 42
A.2 TONE.vhd................................................................................................................................... 45
A.3 SPEAKER.vhd ........................................................................................................................... 46
A.4 UART.ucf .................................................................................................................................... 48
APPENDIX E: SIMPLE PIANO PROJECT ................................................................................... 50
LIST OF FIGURES
Figure2.1: Basic tone of music ..................................................................................................................... 4
Figure2.2: Typical electronic board for musical instrument .................................................................... 4
Figure2.3: Simplified version of FPGA internal architecture .................................................................. 6
Figure2.4: Musical notes and frequencies .................................................................................................. 7
Figure2.5: Altera DE2 Development board ................................................................................................ 8
Figure2.6: Spartan 3AN Starter Development Kit .................................................................................... 9
Figure2.7: Cyclone II FPGA Starter Development Kit ............................................................................10
Figure3.1: Gantt chart ................................................................................................................................15
Figure4.1: Programmable logic design process ........................................................................................16
Figure4.2: Xilinx ISE programming platform ..........................................................................................17
Figure4.3: Timing simulation .....................................................................................................................18
Figure4.4: Programming of bit file into FPGA ........................................................................................19
Figure4.5: A PS2 keyboard .........................................................................................................................19
Figure4.6: Timing diagram of a PS2 port .................................................................................................20
Figure4.7: PS2 signals .................................................................................................................................20
Figure4.8: Scan code of the PS2 keyboard ................................................................................................21
Figure4.9: 8-bit ASCII code with parity ....................................................................................................21
Figure4.10: Double side stereo speaker .....................................................................................................23
Figure4.11: Stereo Miniature Jack ............................................................................................................23
Figure5.1: Examples of Mealy and Moore output ....................................................................................25
Figure5.2: Examples of an FSM .................................................................................................................26
Figure6.1: Block diagram of the simple piano system ..............................................................................27
Figure6.2: Simple Piano Setup ...................................................................................................................28
Figure6.3: J26 configuration ......................................................................................................................29
Figure6.4: Transmission of a byte ..............................................................................................................29
Figure6.5: Timing diagram of a PS2 port .................................................................................................30
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Figure6.6: ASMD chart of the PS2 port ....................................................................................................30
Figure6.7: Block diagram of Sound module ..............................................................................................31
Figure6.8: ISE design properties ................................................................................................................32
Figure6. 9: ISE summary ............................................................................................................................32
Figure6. 10: Generation of programming file ...........................................................................................33
Figure6. 11: iMPACT program succeeded ................................................................................................33
LIST OF TABLES
Table2.1: Comparison of various platforms .............................................................................................. 6
Table2.2: Comparison of Input Devices ....................................................................................................12
Table2.3: Comparison of VHDL and Verilog ...........................................................................................12
Table3.1: Project Task List.........................................................................................................................14
Table4.1: ASCII codes.................................................................................................................................22
Table4.2: Digital Outputs to Stereo Minijack ...........................................................................................24
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1
INTRODUCTION
1.1
BACKGROUND AND MOTIVATION
Over the years, digital hardware has experienced drastic expansion and improvement. In
this modern era, transistors in a single chip have evolved to become faster, smaller,
cheaper and even more capable. Field Programmable Gate Array is a special form of a
Very Large Scale Integrated Circuit (VLSI) consisting of Logic Blocks, Input / OutputBlocks, and Routing Channels. All elements of the FPGA are freely programmable by the
user and any logical problem can be easily detected. This feature yields the main
advantage of an FPGA over other forms of VLSIs.
The abilities to reprogram and parallel sequential processing are the great advantages of
FPGAs compared to CPUs, DSPs or other Microcontrollers of VLSI architecture.
Therefore, it is possible to compute massive numbers of instructions in parallel within
one clock cycle on an FPGA. The FPGAs on the other hand are capable 75 of processing
e.g. 10 000 calculations in parallel on one single small board. In order to fully utilise the
ability, it is crucial to implement an algorithm that processes as many parallel instructions
as possible.
For this project, an FPGA prototyping board is used as a platform to design a simple
digital piano. The sound quality and variability of the musical piano can be calculated
and reduplicated using formulas. The decoder will take in the input of a serial bitstream
and output a serial I2C interface for driving a DAC (Digital-to-Analogue) converter. The
DAC converter will drive the headphones or speaker to produce basic musical tones. In
addition, the using of FPGA allows customization of hardware. This is a cost effective
way of creating a digital piano prototype.
1.2
OBJECTIVES OF THE PROJECT
The main objective of the project is to design a functional musical piano system that
could be simulated on a FPGA board.
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Design A Simple Piano Using FPGA
In this project, the types of FPGA prototyping board available in the market are looked
into so as to select the appropriate one for the design of a musical piano.
The academic goal of this project is to develop skills in research, design, programming,
analysis and testing.
1.3
PROJECT SCOPE
The list of tasks needed to achieve the objective of this project is as follows:

Literature review on musical piano and FPGA.

Familiarize with the Spartan 3AN development kit and VHDL coding.

Implement the architecture and function of the simple piano on Spartan 3AN
development board with VHDL coding.

Testing and simulation to determine correct functionality of the musical piano
design using Xilinx ISE simulator.

1.4
Writing the final report.
REPORT ORGANIZATION
This report is organized into 9 chapters.
Chapter 1 provides a background and motivation of the project, objective, project scope
and report outline.
Chapter 2 gives an overview of musical alarm.
Chapter 3 describes the project planning.
Chapter 4 describes the hardware and memory requirements.
Chapter 5 describes the design implementation environment.
Chapter 6 describes the design implementation using VHDL.
Chapter 7 elaborates the simulation, testing, debugging and results.
Finally, Chapter 8 concludes this project with summaries, conclusion, suggested future
works and reflection.
Glossary explains on the abbreviations and terms.
Appendix A consists of the source code and ucf files.
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Appendix B shows picture of the Spartan 3AN starter kit.
Appendix C shows picture of the musical piano project.
2
REVIEW OF THEORY AND PREVIOUS WORK
First of all, an overview of the musical piano characteristics is presented. Next, the
approach, method and design are discussed.
Field Programmable Gate Array is a special form of a Very Large Scale Integrated
Circuit consisting of Logic Blocks, Input / Output-Blocks, and Routing Channels. All
elements of the FPGA are freely programmable by the user and any logical problem can
be easily detected. This feature yields the main advantage of an FPGA over other forms
of VLSIs.
The abilities to reprogram and parallel sequential processing are the great advantages of
FPGAs compared to CPUs, DSPs or other Microcontrollers of VLSI architecture.
Therefore, it is possible to compute massive numbers of instructions in parallel within
one clock cycle on an FPGA. The FPGAs on the other hand are capable75 of processing
e.g. 10 000 calculations in parallel on one single small board. In order to fully utilise the
ability, it is crucial to implement an algorithm that processes as many parallel instructions
as possible.
FPGA is widely used in many fields throughout engineering development. The FPGA
can be programmed as many times as desired. The desired digital function can be
compiled on a computer system using the software supplied by the FPGA vendor. In
order to create a musical piano that allows modification for future designs, the technology
of FPGA Xilinx SPARTAN-3AN kit board is used. It also has the capabilities to carry
out the characteristics necessary for the musical piano design.
A comparison between the different programming languages as well as the evaluation of
different FPGA development kit is being presented.
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2.1
OVERVIEW OF A MUSICAL PIANO
In order to design a musical piano using FPGA, a basic understanding of the structure of
music is required. A piece of music is made up of many structural elements as shown in
Figure2.1. Depending on the desired result of the music tone to be produced, different
aspects of these structures will need to be modelled.
Figure2.1: Basic tone of music
FPGA technology makes a real-time solution of a complete body model of a musical
instrument possible. There are many similarities between the concepts developed in
music and those that are applied in computer science. In order to design a musical piano,
it required mapping of various constructs of music into a programming language
instructions as shown in Figure 2.2. And by executing these instructions, it will decode
and produced the desired musical effect. With detailed and carefully planned mapping, it
can even produce a musical song.
Figure2.2: Typical electronic board for musical instrument
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Design A Simple Piano Using FPGA
The electronic board of a typical electronic musical instrument is made up of two main
functional blocks. The first block includes a sound generation chip together with a ROM.
PCM samples are stored and to be used in sound synthesis. The second block is
composed of a microprocessor, storage memory and a set of I/O peripherals. Upon
depressing a keyboard or push button, an electrical signal is sent to the internal sound
generation devices. By modifying some global parameters in the programming code, the
characteristics of the musical sound can be modified.
2.2
FPGA IMPLEMENTATION
FPGA are two-dimensional arrays of logic blocks and flip-flops with an electrically
programmable interconnection between logic blocks. What makes FPGA different from a
custom IC is that these interconnections consist of electrically programmable switches.
Integrated circuit fabrication technology is used to form metal interconnections between
logic blocks in the case of an IC whereas an FPGA uses multiple level low fan in gates,
which gives it a more compact design compared to an implementation with two-level
AND-OR logic. Customization and configuration are the abilities that make FPGA stand
out among its competitors. Logic block of an FPGA can be configured in such a way that
it can provide functionality as simple as that of transistor or as complex as that of a
microprocessor. It can used to implement different combinations of combinational and
sequential logic functions. Logic blocks of an FPGA can be implemented by any of the
following:
1. Transistor pairs.
2. Combinational gates like basic NAND gates or XOR gates.
3. N-input Lookup tables.
4. Multiplexers.
5. Wide fan in And-OR structure.
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Design A Simple Piano Using FPGA
Routing in FPGA’s consists of wire segments of varying lengths that can be
interconnected via electrically programmable switches. Density of logic block used in an
FPGA depends on length and number of wire segments used for routing.
Figure2.3: Simplified version of FPGA internal architecture
2.3
ADVANTAGES OF FPGA
FPGA’s have many advantages over other platforms. They are flexible, easily
customizable and provide a low cost option. Table 1 shows the comparison of FPGA with
other important platforms in market today.
Table2.1: Comparison of various platforms
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2.4
MUSICAL NOTES AND TONES
The most basic construct of music is the notes, which is an audible sound at a specific
frequency. Figure2.3 shows the full spectrum of musical notes and its correspondence
frequencies.
Figure2.4: Musical notes and frequencies
As the formula, “Frequency = 1 / Time”, so the clock rate and bit rate will affect the
corresponding output of the digital piano. In this project, the musical tones being
experienced are: “Do”, “Re”, “Mi”, “Fa”, “Sol”, “La”, “Si” and “Do”. The correspondence
frequencies used are “524Hz”, “588Hz”, “660Hz”, “698Hz”, “784Hz”, “880Hz”, “988Hz”
and “1048Hz”.
In Xilinx SPARTAN-3AN board, the clock frequency is 50MHz which is equivalent to
20ns. In order to generate a “Do” of “524Hz” which is 1.908ms, the FPGA has to delay
the time by 95400times in order to produce a digitalized sound of “Do”.
2.5
OVERVIEW OF APPROACH AND METHOD
The approach, method and designs of the simple piano are as follows:
1. The device needs to have a constant power supply.
2. The device must be able to detect the key entered correctly.
3. The output tone should be similar to that of a piano.
4. The sound of the buzzer must be loud.
5. The device must be user-friendly.
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2.6
REVIEW OF FPGA DEVELOPMENT KIT SELECTION
The selection of the appropriate FPGA development is an essential task. In this project,
three FPGA development kits were considered. Each of them has some differences in
their features. But they have sufficient logic, memory and the required I/O to meet the
simple piano design implementation. The decision making is based on cost and I/O
features.
It is decided to use Xilinx Spartan 3AN kit as it has got a miniature stereo
audio jack at a low cost
The few choices of FPGA development kits are as follows:
1. Altera DE2 – Development and Education Board
2. Spartan 3AN Starter Development Kit
3. Altera Cyclone II FPGA Starter Development Kit
Altera DE2 – Development and Education Board
Altera's DE2 board is a ready-to-teach platform ideal on logic design illustration. It
provides a wide range of I/Os and applicable from simple tasks and illustrating
fundamental concepts, to challenging designs requiring more advanced knowledge.
Figure2.5: Altera DE2 Development board
The Altera DE2 Development board is a popular academic choice of FPGA board which
is suited for a wide range of illustrations of concepts. Also its vast number of I/Os and
features makes it a popular development projects commercially.
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Xilinx Spartan 3AN Starter Development Kit
Xilinx is a major solution provider in FPGA and CPLD development requirements and
the Spartan 3AN Starter Development Kit is a fine example of its packaged solution with
both performance and cost efficiency which makes it an ideal prototype development
platform with ease of use.
Figure2.6: Spartan 3AN Starter Development Kit
The Spartan 3AN Starter Development Kit provides a lost cost prototyping development
solution to developers of Telecom, Datacom, Servers and many more.
Altera Cyclone II FPGA Starter Development Kit
The Cyclone II FPGA Starter Development Kit is Altera’s low cost evaluation kit for
hardware designers to prototype complex evaluation. The development board includes an
Altera Cyclone II 2C20 FPGA and comes preconfigured with a hardware reference
design stored in flash memory. Hardware designers can use the development board as a
platform to prototype complex embedded systems. The Development Kit provides the
user with an integrated control environment that includes a software controller in C++, a
USB command controller, a multi-port SRAM/SDRAM/flash memory controller, and
demonstration circuitry specified in Verilog code. These features enable users to
implement and test designs without the need to implement complex application
programming interfaces (APIs), host control software, or SRAM/SDRAM/flash memory
controllers
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Figure2.7: Cyclone II FPGA Starter Development Kit
Comparison of FPGA Development Boards
A quick comparison of the above evaluated FPGA Development Kits in Table-1 reveals
that the Spartan 3AN Starter Kit is ideal for the musical piano requirements.
Although all other FPGA solutions are also capable of fulfilling our design requirements
(Standard PS/2 Keyboard input, 15-pin VGA output etc), the Spartan 3A Starter
Development Kit provides the most features like high speed/capacity 32M x16 DDR2
SDRAM, additional RS-232 port, Rotary/push button, on board crystal oscillator etc,
making it the most ideal investment on the added features at the lowest cost.
Xilinx ISE Design Suite for the writing of the HDL codes and Xilinx iMPACT for upload
of the compile instructions to the FPGA board via the JTAG USB interface.
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Feature
Altera DE2 –
Development and
Education Board
Xilinx Spartan 3AN
Starter Development
Kit
Altera Cyclone II
FPGA Starter
Development Kit
FPGA
 Cyclone II
EP2C35F672C6 with
EPCS16 16-Mbit
serial configuration
device
 Spartan-3AN
(XC3S700A-FG484)
 Platform Flash
(XCF04S-VOG20C)
 Cyclone II Starter
Development
Board
 Cyclone II
EP2C20F484C7N
device
I/O Devices
 Built-in USBBlasterTM cable for
FPGA configuration
 10/100 Ethernet
 RS232
 Video Out (VGA 10bit DAC)
 Video In
(NTSC/PAL/Multiformat)
 USB 2.0 (type A and
type B)
 PS/2 mouse or
keyboard port
 Line In/Out,
Microphone In (24bit Audio CODEC)
 Expansion headers
(76 signal pins)
 Infrared port
 Ethernet 10/100 PHY
 JTAG USB
download port
 Two 9-pin RS-232
serial port
 PS/2-style
mouse/keyboard port
 15-pin VGA
connector capable of
4,096 colors
 One FX2 100-pin and
two 6-pin expansion
connectors
 20 user I/O available
on standard header
pins
 Stereo mini-jack for
PWM audio
 4-channel D/A
converter
 2-channel A/D
converter
 Signal amplifier
 VGA, RS-232,
and PS/2 ports
 Two 40-pin
expansion ports
 SD/MMC socket
 24-bit
coder/decoder
(CODEC)
Memory
 8-MBytes SDRAM,
512K SRAM, 4MBytes Flash
 SD memory card slot
 4 Mbit Platform
Flash PROM
 32M x 16 DDR2
SDRAM
 32 Mbit parallel
Flash
 2-16 Mbit SPI Flash
devices
 8-Mb SDRAM
 512-Kb SRAM
 4-Mb flash
Displays
 16 x 2 LCD display
 16 character, 2-Line
LCD
 16 character, 2Line LCD
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 Eight 7-segment
displays
Switches and  18 toggle switches
LEDs
 18 red LEDs
 9 green LEDs
 4 debounced
pushbutton switches
 4 slider switches
 4 push-button
switches
 Rotary/push button
function switch
 8 individual LED
outputs
 10 switches and
four push buttons
 4 7-segment
displays
 10 red and 8 green
LEDs
Clocks
 50 MHz crystal for
FPGA clock input
 27 MHz crystal for
video applications
 External SMA clock
input
 50 MHz crystal
oscillator on-board
 Open slot for
optional userinstalled clock
 SMA connector
(external clock
input)
Cost
 USD 269.00
 USD 199.00
 USD 199.00
Table2.2: Comparison of Input Devices
2.7
OVERVIEW OF VHDL AND VERILOG
Table 2.3 showed a comparison of VDHL and Verilog language.
VHDL
1. Data types are defined by user.
Verilog
1. Data types are defined by Verilog instead
of the user.
2. Procedures and functions may be put in 2. No packages in Verilog. Procedures and
a package for sharing in any design unit
functions used within a model must be
that need them.
defined in the module.
3. Has a library for managing a number of 3. Has no concept of library.
designs.
4. Similar to Ada or Pascal.
4. Similar to C or C++.
5. A wordy language.
5. A language that provide brevity.
Table2.3: Comparison of VHDL and Verilog
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3
PROJECT PLANNING
This chapter describes the project planning. Tools such as CPA (Critical Path Analysis)
and Gantt Project are used to aid in the project planning, time management and selfdisciplining.
The project plan is divided into the following stages:
1. Project Planning
2. Literature Review
3. Learning hardware description language
4. Learning hardware features and software tool of the prototyping board
5. Design Implementation
6. Simulation and Verification
7. Testing and Troubleshooting
8. Final Report, Poster and Presentation
From the Gantt chart as shown in Figure 3.1, a substantial amount of time is required to
learning the coding language.
The most challenging portion of the project is to be the coding. A significant amount of
time is also spends on testing and debugging each individual modules.
A considerable amount of time is spent on the preparation of the final report and
presentation.
Overall, the project was able to meet deadline.
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No
1
2
3
4
5
6
7
8
Task
Design simple piano using FPGA
Project Planning and Management
Literature Review and initial work
Board selection, speaker selection, keyboard
selection and material purchases
Proposal Report
Learning of programming language and
development kit
Learning VHDL coding
Familiarisation with the functions of the Spartan
3AN board
Familiarisation with Xilinx ISE tools and lSim
Familiarisation of FSM
Preparation and submission of Interim report
Research and Study
Research and Study of digital piano architecture
Research and Study of hardware for digital piano
Design Implementation
Design FSM of digital piano
Design Architecture of digital piano
Design and write VHDL Coding
Simulation, Testing and Debugging
Run simulation, verification, testing and debugging
Preparation of Final Report, Poster and Oral
presentation
Final Report writing
Poster Preparation
Oral presentation Preparation
Table3.1: Project Task List
14
Start
1 Jul 10
5 Aug 10
6 Aug 10
End
16 May 11
5 Aug 10
20 Aug 10
20 Aug 10
20 Aug 10
21Aug 10
31 Aug 10
1 Sep 10
10 Oct 10
1 Sep 10
5 Sep 10
6 Sep 10
8 Sep 10
9 Sep 10
8 Oct 10
11 Oct 10
11 Oct 10
26 Oct 10
15 Nov 10
4 Jan 11
19 Jan 11
19 Jan 11
27 Jan 11
10 Feb 11
1 Mar 11
7 Oct 10
10 Oct 10
18 Oct 10
25 Oct 10
14 Nov 10
3 Jan 11
18 Jan 11
28 Feb 11
26 Jan 11
9 Feb 11
24 Feb 11
17 May 11
1 Mar 11
18 Mar 11
19 Mar 11
7 May 11
17 May 11
6 May11
16 May 11
04 Jun 11
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Figure3.1: Gantt chart
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4
HARDWARE AND MEMORY REQUIREMENTS
The hardware components required for the digital musical piano are as follows:
1. Xilinx Spartan-3AN FPGA starter kit
2. Standard PS2 keyboard
3. Speaker
4. ModelSim PE Student Edition v10.0a
The Spartan XC3S700AN-FG484 device and the Spartan-3AN board give a number of
options for storage elements. The storage element that will be used in this project is
XC3S700’s block RAM.
4.1
HARDWARE DESIGN AND DEVELOPMENT
The process of creating digital logic is similar to that of an embedded software
development process. A description of the hardware's structure and behaviour is written
in a high-level hardware description language namely VHDL or Verilog. Prior to
execution, the source code is then compiled and downloaded onto the FPGA. Although
schematic diagram can be used for design entry programming, but due to the complex
designs and the ease of the language-based tools, it has been obliterate over the times.
The overall process of hardware development for programmable logic is shown in Figure
4.1 and described in the paragraphs that follow.
Figure4.1: Programmable logic design process
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At the design entry phase, programmer must have a clear idea of the program flow. All of
the input signals are processed in parallel, inside each signal is a series of macro cells and
interconnections routed toward their destination output port. Therefore, the statements of
a hardware description language create structures, all of which are processed
simultaneously. Figure 4.2 shows the Xilinx ISE programming platform used for
implementing the design.
Figure4.2: Xilinx ISE programming platform
In a typical design, after each programming is completed, the next step is to perform
periods of functional simulation. This is where a simulator comes in place. In this project,
the simulator software being used is the ModelSim Student Edition v10.0a. It is used to
execute the design and verify that the results produced are according to the programmer’s
requirement. This step is to ensure the programmer that the logic and timing is
functionally correct before processing onto the next stage of development. This is a good
practice as compared to simulating an integrated full scale design entry. As the design
entry gets more complex, the troubleshooting process will be much more difficult and
time consuming. Figure 4.3 shows the timing simulation of a design.
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Figure4.3: Timing simulation
Once the correct representation of the hardware exists, compilation can be done. This
hardware compilation comprises of two parts. This first part is called synthesis and the
result is a representation called a netlist. The netlist generated is device independent, so
its contents do not depend on the particulars of the FPGA or CPLD. Normally it is stored
in a standard format called the Electronic Design Interchange Format (EDIF).
The second part in the translation process is called place & route. This step involves
mapping the logical structures described in the netlist onto actual macrocells,
interconnections, and input and output ports. This process is similar to the development
of a printed circuit board, and it may likewise allow for either automatic or manual layout
optimizations. The output result of the place & route process is a bitstream. This name is
used generically, despite the fact that each CPLD or FPGA (or family) has its own,
usually proprietary, bitstream format. The bitstream is the binary data that must be
downloaded into the FPGA chip in order to execute the particular hardware design.
Figure 4.4 shows the successful downloading of the bit file onto the FPGA.
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Figure4.4: Programming of bit file into FPGA
4.2
PS2 KEYBOARD
As the project is to design a simple piano, the user should be able to play the piano using
the keyboard. Most of the keypads and keyboards available in the market are using either
an USB interface or a PS-2 interface. The method is to use a PS2 keyboard and its UART
(Universal Asynchronous Receiver and Transmitter) capability to communicate with the
Xilinx Spartan-3AN board PS2 port. This is also a criterion taken into account while
choosing the FPGA Processing unit for this project. A PS-2 interface keyboard, instead of
an USB interface keyboard, proved to be the best option since most of the major FPGA
boards are compatible with it.
Figure4.5: A PS2 keyboard
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The original 83-key XT keyboard is a unidirectional device. Two-way communication
was introduced with the 84-key AT keyboard. This is then followed by the enhanced
101-key or 102-key multi-functional (MFII) keyboard. The enhanced keyboard has a
separate numeric keypad, separate cursor control keys and a set of 12 function keys.
In this project, the PS2 multi-function keyboard is used.
The PS2 port includes connection for power as well as the data and clock lines. The
basic timing diagram of transmitting a packet from a PS2 device to a host is shown in
Figure 4.6. The data and clock signals are labelled as ps2d and ps2c respectively.
Figure4.6: Timing diagram of a PS2 port
Figure 4.7 showed the PS2 signals. Pin 1 is used for serial data and pin 5 is used for
synchronising clock. Pin 4 is used for power and pin 3 used for signal ground.
Figure4.7: PS2 signals
A PS2 keyboard is comprised of:
1. A matrix of keys
2. An embedded microcontroller
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The function of the embedded microcontroller is to monitor the activities of the keys and
transmits scan code accordingly. The scan code of the PS2 keyboard is shown in Figure
4.8.
Figure4.8: Scan code of the PS2 keyboard
The basic design approach is to translate the scan code into the corresponding ASCII
(American Standard Code for Information Interchange) code words. The corresponding
character or digits can be displayed via computer screens.
In ASCII, each individual character is represented by a 7 bit code, b0-b6. The eighth bit
(b7) is used for parity checking. Figure 4.9 illustrates the 8-bit ASCII code with parity.
ASCII code
b7
b6
b5
b4
b3
b2
b1
b0
Parity
Figure4.9: 8-bit ASCII code with parity
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Using a 7-bit code, 128 (27) different characters may be represented. Table 4.1 lists the
ASCII codes.
Key
Make Code
ASCII Code
(hexadecimal)
(hexadecimal)
Key
Make Code
ASCII Code
(hexadecimal)
(hexadecimal)
A
1C
41
0
45
30
B
32
42
1
16
31
C
21
43
2
1E
32
D
23
44
3
26
33
E
24
45
4
25
34
F
2B
46
5
2E
35
G
34
47
6
36
36
H
33
48
7
3D
37
I
43
49
8
3E
38
J
3B
4A
9
46
39
K
42
4B
`
0E
60
L
4B
4C
-
4E
2D
M
3A
4D
=
55
3D
N
31
4E
\
5D
5C
O
44
4F
BKSP
66
08
P
4D
50
SPACE
29
20
Q
15
51
ENTER
5A
0D
R
2D
52
F1
05
81
S
1B
53
F2
06
82
T
2C
54
F3
04
83
U
3C
55
F4
0C
84
V
2A
56
F5
03
85
W
1D
57
F6
0B
86
X
22
58
F7
83
87
Y
35
59
F8
0A
88
Z
1A
5A
F9
01
89
F10
09
8A
F11
78
8B
F12
07
8C
Table4.1: ASCII codes
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4.3
SPEAKER
Figure4.10: Double side stereo speaker
The type of speaker selected for this project is tiny in size but the sound is impressive as
it deliver a loud sound. The speaker uses a 3.5mm stereophonic jack. By using this
speaker, we can drive it directly from the FPGA. The speaker can be recharged when it
is connected to a USB port of a computer system. The speaker used in this project is a
double stereo speaker. Figure 4.10 showed the type of USB speaker used in the project.
Figure4.11: Stereo Miniature Jack
The Xilinx Spartan-3AN board includes a miniature stereo audio jack plug, as shown in
Figure 4.11. The jack plug is located in the upper right hand corner of the board. The port
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provides simple audio tones to an attached set of headphones or to amplified speakers.
The audio device must use a 3.5mm audio jack and a stereo connector is highly
recommended. A monophonic connector will function, but with the following limitation
shown in Table 4.2
Signal Name
FPGA Pins
Stereo Jack
Mono Jack
AUD_L
Y10
Left-side audio
Audio Channel
AUD_R
V10
Right-side audio
Drive to High-Z
Table4.2: Digital Outputs to Stereo Minijack
5
DESIGN IMPLEMENTATION ENVIRONMENT
This chapter discussed on the design implementation environment language and method
used in this project.
5.1
FPGA
The Spartan-3AN development board is chosen as it has the appropriate features at a
competitive price to meet the design implementation.
5.2
XILINX ISE SOFTWARE
The design tool for the Spartan-3AN board is Xilinx ISE 10.1.
The Xilinx ISE
(Integrated Software Environment) controls all aspects of the development flow. This
software will support the programmer through the logic design process. It offers features
such as design entry, synthesis, simulation, implementation and data downloading.
5.3
MODELSIM STUDENT EDITION v10.0a
ModelSim, manufactured by Mentor Graphics Cooperation, is the simulation
environment used for this project. It is a very useful tool that is used for debugging and
analyzing the design through viewing waveforms, time measurement and running
simulation. A ModelSim simulation project consists of the library definition and a
collection of HDL files. Alternatively, writing a test bench in the ISE editor can be used
to simulate the timing waveform.
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5.4
HDL LANGUAGE
The behaviour of the FPGA can be defined using hardware description language (HDL).
The two commonly used HDLs are Verilog and VHDL. For a newbie doing FPGA
programming, VHDL is chosen for this project as it is easier to learn.
5.5
PLANAHEAD
PlanAhead is a tool that is useful in initial pin assignments, perform floor-planning,
exploring compile options to improve performance, perform design rule checks and
analyze implementation results.
5.6
iMPACT
iMPACT is a programming tool used to download a bit stream to FPGA through several
parallel cables including the Platform Cable USB. iMPACT can create bit files, System
ACE files, PROM files, and SVF/XSVF files. The SVF/XSVF files can be played back
without having to recreate the chain. iMPACT supports several configuration modes such
as boundary scan, slave serial, select map and desktop.
5.7
FSM
FSM (finite state machine) is used to control the operation of the system. An FSM
consists of a state register, next state logic and output logic. An FSM is known as Moore
machine if the output is only a function of state. If the output is a function of state and
external input, the FSM is known as Mealy machine. Figure 5.1 shows the block diagram
of an FSM of Mealy and Moore output.
Figure5.1: Examples of Mealy and Moore output
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An FSM can be specified by a state diagram or ASM (algorithmic state machine chart).
The two representations provide the same information. As the state machine needs to be
represented in a digital circuit, each state is represented by an encoding style. The FSM
representation is more compact and better for simple applications. The ASM chart
representation is somewhat like a flowchart and is more descriptive for applications with
complex transition conditions and actions. Figure 5.2 shows an example of both state
diagram and ASM.
Figure5.2: Examples of an FSM
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6
DESIGN IMPLEMENTATION
This section will describe the functionality, design and implementation of the simple
piano.
SIMPLE PIANO SYSTEM
Sound
Module
Speaker
Map
Module
PS2 Keyboard
PS2
Module
Memory
Module
FIFOPS2
Module
Figure6.1: Block diagram of the simple piano system
There are two phases in the implementation of simple piano using FPGA namely:

Design Phase

Debug and Verification Phase
The Design Phase involved entry, simulation and implementation.
The Debug and Verification Phase involved validate the design and debugging.
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6.1
SIMPLE PIANO OVERVIEW
In order to produce basic music tone, the frequency of the tone must be calculated based
on the clock frequency of the board. Other than this, the simple piano is comprised of the
following components. Figure 6.2 shows the setup for this project.
Figure6.2: Simple Piano Setup
PS2 Keyboard – The user will interface with the simple piano system through a PS2
keyboard. The PS2 keyboard is used to played different tone according to each button is
pressed.
Spartan3AN Xilinx Board – The FPGA board is used to simulate a piano. In the project,
it will be using the PS2 port, the USB download cable and the audio jack port.
USB powered speakers – The musical tone will be amplified by the FPGA board before
being played through the speakers. The sound produced are stereo instead of monophonic.
The main component of the simple piano system is the Spartan 3AN development board
that acts as the brain for the whole system.
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6.2
XILINX SPARTAN3AN CONFIGURATION MODE
M2, M1 and M0 jumpers are placed as shown in Figure 6.2. This puts the FPGA in
Master Serial configuration mode. After that, user can create the PROM file (.MCS)
using IMPACT to store the whole program image in XCF04S Flash serial PROM. In this
way, user will not need to download the program to FPGA chip every time power is on.
Figure6.3: J26 configuration
6.3
UART SYSTEM
Universal asynchronous receiver and transmitter (UART) is a circuit that sends parallel
data through a serial line. Because the voltage level defined in RS-232 is different from
that of FPGA I/O, a voltage converter chip is needed between a serial port and an
FPGA’s IO pins.
Figure6.4: Transmission of a byte
The serial line is ‘1’ when it is idle. The transmission starts with a start bit, which is ‘0’,
followed by data bits and an optional parity bit, and ends with stop bits, which are ‘1’.
The transmission with 8 data bits, no parity, and 1 stop bit is shown in Figure 6.4. The
LSB of the data word is transmitted first.
6.4
PS2 MODULE
The PS2 port is introduced in IBM’s Personal System/2 personnel computers. It is a
widely supported interface for a keyboard and a mouse to communicate with the host.
The PS2 port contains two wires, one for data communications and the other for clock
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information. The information transmit is a 11-bit packet that contains a start bit, stop bit,
odd parity bit and 8-bit of data. Figure 6.5 shows the timing diagram of a PS2 port.
Figure6.5: Timing diagram of a PS2 port
The PS2 port includes connections for power, which is a 5V power supply. The power is
supplied by the host and the data is transmitted in a serial stream. The data is named as
ps2d and the clock is named as ps2c. The design of a PS2 is similar to an UART.
Therefore in this project, falling edge of the PS2D will be used as a reference point to
retrieve data. The ASMD chart shown in Figure 6.6 shows the flow of the HDL coding.
Figure6.6: ASMD chart of the PS2 port
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6.5
SOUND MODULE
The sound module is responsible for producing the tone upon a button is depressed.
Based on the individual button pressed, it will then produce the tone accordingly. In this
project, the musical tones being experienced are: “Do”, “Re”, “Mi”, “Fa”, “Sol”, “La”,
“Si” and “Do”. The correspondence frequencies used are “524Hz”, “588Hz”, “660Hz”,
“698Hz”, “784Hz”, “880Hz”, “988Hz” and “1048Hz”. When the button ‘A’ is pressed, a
state will be received by the sound module and the speaker will sound. Figure 6.7
illustrates the block diagram of the Sound module.
Speaker
Button ‘A’ state
Sound Module
Figure6.7: Block diagram of Sound module
6.6
TOP MODULE
The Top module consists of all the different instances representing the PS2 module, Map
module and Sound module. All these instances are being wired up together. At this top
level module, the user inputs are assigned to the PS2 keyboard and the outputs are
assigned to the speaker.
6.7
COMPILING AND TARGETING OF VHDL CODE
The VHDL codes written for the various modules needed to be compiled and targeted to
the Spartan 3AN FPGA board. The Xilinx ISE design suite is used to compile and
download the codes to the FPGA board. First of all, the design properties of the project
are set according to the FPGA board used. Figure 6.8 shows how the design properties
are set for the project.
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Figure6.8: ISE design properties
The next step is to add the various modules to the project based on their hierarchy. Figure
6.9 shows how the various modules are added to the project navigator based on the
hierarchy. The figure also shows how to implement the design on to the board or simulate
by choosing the required option from the drop down menu.
Figure6. 9: ISE summary
After the implementation option is selected, the target board is connected to the PC via
the USB cable. The FPGA board also had the PS-2 keypad connected before being power
on. Once connected, the process of generating the programming file can begin. The top
level module of the hierarchy is selected and command to generate the programming file
is given. The project navigator then synthesizes, translates, maps, places and routes the
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design. The programming file is then generated after all the processes are finished. The
figure below shows the processes involved in the generation of the programming file.
Figure6. 10: Generation of programming file
After the successful generation of the programming file based on the design properties,
an ISE iMPACT window is opened which allows the user to download the generated
programming file on to the FPGA board. The launch wizard in the software performs a
boundary scan and automatically detects the attached board and shows the various
programmable sources on the board. In this project the program is directly targeted to the
Xilinx FPGA, xc3s700a. The rest of the devices are bypassed.
The xc3s700a is set and the target device and programmed. Successful programming will
show a ‘program succeeded’ prompt and the board will be ready to use with the codes
loaded. Figure 6.11 shows the successful programming of the FPGA board.
Figure6. 11: iMPACT program succeeded
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7
CONCLUSIONS AND RECOMMENDATIONS
7.1 CONCLUSIONS
This project is to design a simple piano using FPGA. This chapter summarizes and
concludes on the project in terms of project planning, design, testing and results. It also
lists the ideas for future works in terms of further software and hardware developments.
The objectives of the project set during the initial phase of the project are met. Xilinx
SPARTAN-3AN FPGA development board is purchased and researches has to be done
so that the project can be implemented. The developed prototype of the simple piano is
able to fulfil all the specifications stated in the project requirement. Hardware
programming language such as VHDL is learnt throughout the project. The simple piano
is able to produce the basic music tone of the piano such as “Do”, “Re”, “Mi”, “Fa”,
“Sol”, “La”, “Si” and “Do”. Overall, the simple piano is able to perform well.
7.2 RECOMMENDATIONS
There is still room for improvement for the simple piano project. Firstly, as the values of
the register are implemented on volatile memory, once it is power off, the data is lost. For
future development, one should look into storing the important data into non-volatile
memory (FLASH Memory) which is available on the Spartan 3AN board.
Secondly, the music melody for a particular song can be written and downloaded into the
FLASH memory. Upon a triggering a switch, the FPGA will be trigger to play the music
upon itself without pressing the keyboard. Due to the time constraints, I have done some
programming on this idea. However, it did not turns out to be successful and the
programming gets more and more complex.
Overall, the simple piano project is a challenging and fruitful experience.
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8
REFLECTION
As discussed in conclusion, the main objective of the project was met. I might have been
able to produce results on the Xilinx SPARTAN-3AN FPGA board but I have not
demonstrated the same results in simulated environment.
Nevertheless, I have also
learned the FPGA development environment. In reflection from an academic point of
view the projects objectives were successfully met. I have gained the following skills:

Research and literature review

Planning and project management

Studying of algorithm and Architecture

Learning Programming language, structure and tools

Design and implementation

Testing and evaluation

Problems solving

Writing technical report

Oral Presentation
Upon completion of this project, I have developed a great understanding on project
management and development.
developed.
I have explored on how a project is managed and
I am now familiar with all the development stages, from research and
planning to the design and implementation of the project. Armed with new skills and
knowledge, this experience has my spurred interests to a higher level to explore new
grounds by applying the new skills accordingly.
Every stage has been a great exposure for me to learn and grow. At the initial stage of
my work, I faced a lot of difficulties in sourcing for the algorithm and understanding it.
This is my first encounter with a FPGA development board and every component on
board is a new experience for me. Throughout this project I have gained basic knowledge
on some on board components and have tried to implement them. Hence, project plan
was rescheduled due to unforeseen problems. In addition, as I am new to the platform, I
needed some extra time to be familiarized with the platform, tools and language.
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The biggest challenge faced was managing time effectively with the heavy project work
load and my own personal work load. I have to be very discipline in all areas and learnt
that good time management plays an important role in planning and ensuring all tasks are
running as smoothly as scheduled. I have learnt to be able to manage stress level to a
minimum while facing all these challenges as a part time student and have grown to be
more self-reliant. In fact this experience has taught to me to handle both work and study
confidently.
During the project development, I encountered many problems and difficulties. Problem
solving skills is one of the critical skills that are essential to develop in order to keep the
project constantly moving. At times I have to resolve the problems independently which
in some scenario, I had to seek for the right resources and supports. In this aspect, I have
learned to be more resourceful and to work more independently as well.
The mistakes and problems encountered have helped me to identify my strengths and
weaknesses in term of technical skills and interpersonal skills. I have learnt from the
errors and will improve on the weaknesses identified.
In conclusion, this is a very fruitful practical hands-on experience to equip me with better
understanding and knowledge. Most importantly, being able to apply the knowledge and
professional skills that are relevant for future work and to succeed in today’s competitive
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REFERENCES
[1] Altera, University Program UP2 Education Kit, available online at
http://www.altera.com/literature/univ/upds.pdf
[2] Xilinx ISE Webpack, available online at
http://www.xilinx.com/ise/logic_design_prod/webpack.htm
[3] Quartus II, available online at
http://www.altera.com/products/software/products/quartus2/qtsindex.html
[4] Eprintcalenders, “piano keys”, available online at
http://www.eprintablecalendars.com/images/music/piano-keys.jpg
[5] First User Action FUSE Case study reference number: 26858, “ASIC for Electronic
musical keyboards. Increased competitiveness using VHDL methodology in design”
available online at
http://www.fuse-network.com/fuse/demonstration/363/26858/26858.pdf
[6] Wenzel, C, “Musical Notes”, available online at
http://www.techlib.com/reference/musical_note_frequencies.htm
[7] Pong P.Chu,”RTL Hardware Design Using VHDL, Coding for Efficiency, Portability,
and Scalability”, Wiley-Interscience, April 2006
[8] Stephen Brown and Zvonko Vranseic, “Fundamentals of Digital Logic with VHDL
Design”, McGraw Hill, January 2005
[9] Thomas L. Floyd, “Digital Fundamentals”, Prentice-Hall, December 1997
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[10] Wikipedia, “piano keys frequencies”, available online at
http://en.wikipedia.org/wiki/Piano_key_frequencies
[11] Quick Logic Corporation, “packages”, available online at
http://www.quicklogic.com/
[12]Xilinx, “Xilinx Training”, available online at
http://www.xilinx.com/training/index.htm
[13] Atmel Corporation, “Field Programmable Gate Array”, available online at
http://www.atmel.com/products/FPGA/default.asp?family_id=623
[14]Lattice Semiconductor Corporation, “Field Programmable Gate Array,” available
online at http://www.latticesemi.com/products/fpga/index.cfm?source=topnav
[15] Florian Pfeiffle and Rolf Bader,”Real-Time Physical Modeling of a complete Banjo
geometry using FPGA hardware technology”, available online at
http:www.systmuwi.de/FPGA_Papers.html
[16] Frontiers in Education Clearing House, “The Musical CPU”, available online at
http://www.fie-conference.org/fie2007/papers/1181.pdf
[17] Xilinx, “Spartan-3A/3AN FPGA Starter Kit Board User Guide”, UG334 (v1.1), June
19, 2008
[18] PONG P. CHU, “FPGA prototyping by Verilog Examples: Xilinx Spartan-3
Version”, Wiley, 2008
[19] Xilinx, “ISE In-Depth Tutorial”, UG695 (v11.2) June 24, 2009
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[20] Xilinx, “Spartan-3 Generation Configuration User Guide”, UG332 (v1.6), October
26, 2009
[21] Xilinx, “Using Block RAM in Spartan-3 FPGAs”, XAPP463 (v1.1.2), July 23, 2003
[22] Xilinx, Product Details Spartan-3AN Starter Kit Product Brief
[23] Xilinx, Recorded E-Learning Course, available online at
http://www.xilinx.com/training/index.htm
[24] FPGA4fun forum, available online http://www.fpga4fun.com/MusicBox2.html
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GLOSSARY
ASCII (American Standard Code for Information Interchange) is a 7 bit code used to
represent alphanumeric characters.
ASM algorithmic state machine chart
CPA Critical Path Analysis
FIFO First In First Out
Flash memory is a non-volatile memory that can be electrically erased and reprogrammed.
FPGA Field-programmable gate array
FSM finite state machine
HDL hardware description language
ISE integrated software environment
ISIM ISE waveform Simulator
Instantiation is the creation of a real instance such as defining a particular object within
a class, giving it a name and locating it in some physical place.
LSB Least Significant Bit
Microcontroller is a small computer on a single chip that contains a processor, memory
and peripherals.
MSB Most Significant Bit
Non-volatile memory is a computer memory that can retain stored information even
when not powered.
RAM Random Access Memory is a volatile memory as it loses stored data when the
power is turned off.
USB Universal Serial Bus; an external serial bus standard.
UUT Unit under test
Scan code is a special 8-bit code generated by the keyboard encoder.
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SRAM (Static Random Access Memory) is characterized by flip-flop storage cells that
are implemented in integrated circuits with several MOS transistors (MOSFETs). Data is
lost when the memory is not powered.
Stereophonic sound is the reproduction of sound using two or more independent audio
channels.
Verilog Verilog is a hardware description language (HDL) used to model electronic
systems.
VHDL VHDL is design entry language for field programmable gate array (FPGA).
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APPENDIX A: SOURCE CODE
A.1
UART.vhd
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UART is
port (
clk, reset: in std_logic;
ps2d, ps2c: in std_logic;
spkout: out STD_LOGIC;
spkout2: out STD_LOGIC
);
end UART;
-- key data, key clock
architecture Behavioral of UART is
type statetype is (idle, dps, load);
constant BRK: std_logic_vector(7 downto 0):="11110000"; --F0 break code
signal state_reg, state_next: statetype;
signal filter_reg, filter_next: std_logic_vector(7 downto 0);
signal f_ps2c_reg, f_ps2c_next: std_logic;
signal b_reg, b_next, c_reg, c_next: std_logic_vector(10 downto 0);
signal n_reg, n_next: unsigned(3 downto 0);
signal fall_edge: std_logic;
signal dout: std_logic_vector(7 downto 0);
signal ouch: integer range 0 to 16777215;
signal high1: integer range 0 to 16777215;
signal count: integer;
signal rx_done_tick: std_logic;
component tone
Port ( index : in std_logic_vector(7 downto 0);
high : out integer range 0 to 16777215;
tone0 : out integer range 0 to 16777215);
end component;
component speaker
Port ( clk1 : in std_logic;
tone1 : in integer range 0 to 16777215;
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--std_logic;
Lim Zheng Yong
J0706297
Design A Simple Piano Using FPGA
stereo : in integer range 0 to 16777215;
spks : out std_logic;
spks2 : out STD_LOGIC);
end component;
begin
--filter and falling edge tick generation for ps2c
process (clk, reset)
begin
if reset='1' then
filter_reg <= (others => '0');
f_ps2c_reg <= '0';
elsif (clk'event and clk = '1') then
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end if;
end process;
filter_next <= ps2c & filter_reg(7 downto 1);
f_ps2c_next <= '1' when filter_reg = "11111111" else
'0' when filter_reg = "00000000" else
f_ps2c_reg;
fall_edge <= f_ps2c_reg and (not f_ps2c_next);
--fsmd to extract the 8-bit data
--registers
process (clk, reset)
begin
if reset = '1' then
state_reg <= idle;
n_reg <= (others => '0');
b_reg <= (others => '0');
c_reg <= (others => '0');
elsif (clk'event and clk = '1') then
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
c_reg <= c_next;
end if;
end process;
--next state logic
--process(state_reg, n_reg, b_reg, fall_edge, rx_en, ps2d)
process(state_reg, n_reg, b_reg, fall_edge, ps2d, c_reg)
begin
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Lim Zheng Yong
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Design A Simple Piano Using FPGA
rx_done_tick <= '0';
state_next <= state_reg;
n_next <= n_reg;
b_next <= b_reg;
c_next <= c_reg;
case state_reg is
when idle =>
--if fall_edge = '1' and rx_en = '1' then
if fall_edge = '1' then
-- shift in start bit
b_next <= ps2d & b_reg(10 downto 1);
c_next <= (others => '0');
n_next <= "1001";
--1001
state_next <= dps;
end if;
when dps => --8 data + 1 parity + 1 stop
if fall_edge = '1' then
b_next <= ps2d & b_reg(10 downto 1);
if n_reg = 0 then
state_next <= load;
else
n_next <= n_reg - 1;
end if;
end if;
when load =>
-- 1 extra clock to complete the last shift
state_next <= idle;
rx_done_tick <= '1';
end case;
end process;
--output
u1: tone port map(index=>dout,tone0=>ouch,high=>high1);
u2: speaker port
map(clk1=>clk,tone1=>ouch,spks=>spkout,stereo=>high1,spks2=>spkout2);
dout <= b_reg(8 downto 1); -- data bits
end Behavioral;
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Design A Simple Piano Using FPGA
A.2
TONE.vhd
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tone is
Port ( index : in STD_LOGIC_VECTOR (7 downto 0);
high : out integer range 0 to 16777215;
--STD_LOGIC;
tone0 : out integer range 0 to 16777215
);
end tone;
architecture Behavioral of tone is
begin
search :process(index)
begin
case index is
when "00010101" => tone0<=95400;high<=95400;
= 'Do'
when "00011101" => tone0<=85030;high<=85030;
'W' = 'Re'
when "00100100" => tone0<=75755;high<=75755;
= 'Mi'
when "00101101" => tone0<=71600;high<=71600;
= 'Fa'
when "00101100" => tone0<=63775;high<=63775;
= 'Sol'
when "00110101" => tone0<=56818;high<=56818;
= 'La'
when "00111100" => tone0<=50607;high<=50607;
= 'Si'
when "01000011" => tone0<=47710;high<=47710;
= 'Do'
when others => tone0<=0;high<=0;
other keyboard = No sound
end case;
end process;
end Behavioral;
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--Keyboard 'Q'
--Keyboard
--Keyboard 'E'
--Keyboard 'R'
--Keyboard 'T'
--Keyboard 'Y'
--Keyboard 'U'
--Keyboard 'I'
--Any
Lim Zheng Yong
J0706297
Design A Simple Piano Using FPGA
A.3
SPEAKER.vhd
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity speaker is
Port ( clk1 : in STD_LOGIC;
tone1 : in integer range 0 to 16777215;
stereo : in integer range 0 to 16777215;
spks : out STD_LOGIC;
spks2 : out STD_LOGIC);
end speaker;
architecture Behavioral of speaker is
signal preclk,fullspks:std_logic;
signal preclk2,fullspks2:std_logic;
signal timeout: integer;
signal timeout2: integer;
begin
--Left Channel
pulse1:process(clk1)
variable count:integer range 0 to 8;
begin
if clk1'event and clk1='1' then count:=count+1;
if count=2 then preclk<='1';
elsif count=4 then preclk<='0';count:=0;
end if;
end if;
end process pulse1;
genspks:process(preclk,tone1)
variable count11:integer range 0 to 16777215;
begin
if preclk'event and preclk='1' then
if count11<tone1 then
count11:=count11+1;
fullspks<='1';
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--30624
Lim Zheng Yong
J0706297
Design A Simple Piano Using FPGA
else count11:=0;
fullspks<='0';
end if;
end if;
end process;
delaysps:process(fullspks)
variable count2 :std_logic:='0';
begin
if fullspks'event and fullspks='1' then count2:=not count2;
if count2='1' then
spks<='1';
else
spks<='0';
end if;
end if;
end process;
--Right Channel
pulse2:process(clk1)
variable count3:integer range 0 to 8;
begin
if clk1'event and clk1='1' then count3:=count3+1;
if count3=2 then preclk2<='1';
elsif count3=4 then preclk2<='0';count3:=0;
end if;
end if;
end process pulse2;
genspks2:process(preclk2,stereo)
variable count22:integer range 0 to 16777215;
begin
if preclk2'event and preclk2='1' then
if count22<stereo then
count22:=count22+1;
fullspks2<='1';
else count22:=0;
fullspks2<='0';
end if;
end if;
end process;
delaysps2:process(fullspks2)
variable count4 :std_logic:='0';
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--30624
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Design A Simple Piano Using FPGA
begin
if fullspks2'event and fullspks2='1' then count4:=not count4;
if count4='1' then spks2<='1';
else
spks2<='0';
end if;
end if;
end process;
end Behavioral;
A.4
UART.ucf
---------------------------------------------------------------------------------NET "spkout" LOC = Y10;
#NET "high1" LOC = V10;
NET "spkout" IOSTANDARD = "LVCMOS33";
NET "spkout" DRIVE = 8;
NET "spkout" SLEW = SLOW;
#NET "high1" IOSTANDARD = "LVCMOS33";
#NET "high1" DRIVE = 8;
#NET "high1" SLEW = SLOW;
NET "clk" LOC = E12;
NET "ps2c" LOC = W12;
NET "ps2c" IOSTANDARD = "LVCMOS33";
NET "ps2d" LOC = V11;
NET "ps2d" IOSTANDARD = "LVCMOS33";
NET "reset" LOC = T14;
NET "reset" IOSTANDARD = "LVCMOS33";
NET "spkout2" SLEW = SLOW;
NET "spkout2" LOC = V10;
NET "spkout2" IOSTANDARD = "LVCMOS33";
NET "spkout2" DRIVE = 8;
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Lim Zheng Yong
J0706297
Design A Simple Piano Using FPGA
APPENDIX D: SPARTAN3AN STARTER KIT
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Lim Zheng Yong
J0706297
Design A Simple Piano Using FPGA
APPENDIX E: SIMPLE PIANO PROJECT
Spartan 3AN board
Laptop installed with
ISE software
Speaker
PS2 Keyboard
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