Department of Electrical Engineering and Electronics, UMIST
Third Year Project Report
Investigation and Comparison of the UMIST
p-MOS process with n-MOS
Baris Sanli
Supervisor: Dr Jan Evans-Freeman
A report submitted in partial fulfilment of the requirement of the degree of B.Eng. in
Electronic Engineering.
8 May 2001
1
Acknowledgement
I would like to thank following people for their help to my project and me. My mum for
supporting me all the time, my sponsors Turkish Educational Consulate for their support,
my supervisor Dr. Jan Freeman for helping generously even in her busy times, Mal
McGowan for his beautiful jokes and his enormous helps. Dr Christopher Darkin for
helping me last year during my personal problems. 3rd year student Desmond Lay, for
exchanging his ideas and sharing his fabrication data with me during the long fabrication
hours.
08/05/2001-Manchester
Baris Sanli
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Abstract
The MOSFET technology is the underlying technology of today’s electronic
world. As UK’s leading teaching institute UMIST has one of the few
cleanrooms open to undergraduate students for familiarisation with today’s
technology. The dominant technology at UMIST D16 cleanroom is pMOS.
This project first investigated pMOS process and fabricated a pMOS device
and then a new challenge, fabricating a nMOS device was tried and
problems with NMOS technology was investigated. The modelling of the
test data are carried out. Further suggestions are given at the conclusion
chapter.
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Investigation and Comparison of the UMIST 1
Supervisor: Dr Jan Evans-Freeman............................................................................ 1
Abstract ............................................................................................................................... 3
Introduction ......................................................................................................................... 7
Introduction ..................................................................................................................... 7
Manufacturing: ............................................................................................................ 8
Testing: ....................................................................................................................... 8
Modelling: ................................................................................................................... 8
Approach to the problem: ............................................................................................... 8
Tools: .............................................................................................................................. 9
Background Information ................................................................................................... 10
DEVICE INFORMATION ........................................................................................... 10
JK FLIP-FLOP .......................................................................................................... 10
NAND GATE ........................................................................................................... 11
MOSFET TRANSISTORS ....................................................................................... 12
p-channel MOSFET (pMOS) .................................................................................... 15
n-channel MOSFET (nMOS) .................................................................................... 16
MOS Capacitor ......................................................................................................... 16
MOSFET Equations .................................................................................................. 17
PROCESS INFORMATION ........................................................................................ 19
BULK SEMICONDUCTOR GROWTH.................................................................. 19
Manufacturing and Testing ............................................................................................... 27
Introduction ................................................................................................................... 27
pMOS Manufacturing ................................................................................................... 27
Cleaning .................................................................................................................... 28
The UMIST pMOS Process ...................................................................................... 29
nMOS Manufacturing ................................................................................................... 30
Wet Oxidation ........................................................................................................... 30
Photoresist Coating ................................................................................................... 31
Mask 1 ....................................................................................................................... 31
Phosphorus Diffusion................................................................................................ 32
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Mask 2 ....................................................................................................................... 32
Gate Oxide (Thin oxide) Growth .............................................................................. 32
Mask 3 – Contact Holes and Gate Oxide Etching .................................................... 33
Metallisation ............................................................................................................. 33
Mask 4 ....................................................................................................................... 34
Testing........................................................................................................................... 34
Analysing the Data and Simulation .................................................................................. 36
Introduction ................................................................................................................... 36
pMOS Device and Spice Model: .................................................................................. 36
Threshold Voltage Parameter (VTO)........................................................................ 37
Transconductance Parameter: ................................................................................... 38
PMOS Spice Model ...................................................................................................... 40
nMOS Data Analysing .................................................................................................. 43
nMOS Results ........................................................................................................... 43
A Possible Theory: .................................................................................................... 44
Diffusion Problem and More reasons ....................................................................... 45
nMOS Spice Model................................................................................................... 47
Spice notation for nMOS: ......................................................................................... 47
Inverter Example ....................................................................................................... 48
Conclusion .................................................................................................................... 48
Conclusion ........................................................................................................................ 50
Results:.......................................................................................................................... 50
Comment:...................................................................................................................... 51
Further Suggestions: ..................................................................................................... 52
Appendix 1 ........................................................................................................................ 53
Feasibility Report .............................................................................................................. 53
Appendix 2 ........................................................................................................................ 54
Photos of nMOS fabrication ............................................................................................. 54
Appendix 3 ........................................................................................................................ 55
Excel Spreadsheets............................................................................................................ 55
Appendix 4 ........................................................................................................................ 56
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Masks ................................................................................................................................ 56
References ......................................................................................................................... 57
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Introduction
The revolution of the transistor changed the course of the humanity. Television,
radio and computers are the most important fruits of this area. The information is
widespread and easily accessible to individuals.
In this revolution, the invention of the Metal Oxide Silicon (MOS) Field Effect
Transistor (FET) has the biggest effect. pMOS technology is followed by nMOS
technology and afterward CMOS (complementary MOS) dominated the whole
technology. CMOS is the combination of these two technologies.
This project will examine the UMIST pMOS and nMOS processes. If possible a
comparison will be made. Because pMOS process is the only technology in UMIST D16
cleanroom facilities, nMOS technology will be a new challenge.
Lots of flavours are blended in this project, from theoretical work to practical
work, semiconductor manufacturing to software simulation and device operation to
possible fault detection. Combining all these required lots of working and thinking.
Introduction
This project is done in order to compare the pMOS and nMOS technologies at UMIST.
To achieve this goal several milestones are defined and proceeded.
1) Manufacturing a pMOS device
2) Testing the pMOS device
3) Modelling the pMOS device
4) Manufacturing an nMOS device
5) Testing the nMOS device
6) Modelling the nMOS device
7) Comparing the models
As a matter of fact these milestones can be grouped into three parts.
a) Manufacturing
b) Testing
c) Modelling
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Manufacturing:
Manufacturing is the basis for this project. The first aim is to manufacture a
pMOS device. This will be helpful for understanding semiconductor fabrication. Also
experience gained will be used for nMOS fabrication. In short pMOS fabrication is the
learning process and nMOS fabrication is the test for learning.
Testing:
This part is the bridge between real word to mathematical word. The behaviour of
the device is tested and the help of this test result will lead to a mathematical (or spice)
model.
Modelling:
Modelling is the key point in efficient and fast design. If a good model is
obtained, the problems can be detected on computer simulations. Fabrication is a lengthy
and relatively expensive process where simulation is cheap and fast. Instead of
fabricating the actual device and facing with the mistakes after fabrication, a model will
save lots of time and money.
Approach to the problem:
Manufacturing process takes lots of time. When two kinds of chips are needed,
manufacturing becomes twice as long. So, testing and modelling must be fast and cost
effective.
The fastest way to model a MOSFET transistor is through the data from the I-V
and C-V plots. First of all I-V test is done and if the device is working it is packaged for
C-V testing. Instead of testing all the components on the chip, only the transistors are
tested for project aims. Resistors, capacitors are not very useful for defining the
characteristics of pMOS or nMOS technology. The transistors are tested for two Spice
parameters. They are VTO and KP.
So by cutting the test time and simplifying the transistor model, in a short time
more points are covered, hence the model is powerful.
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Tools:
Numerous tools are used for this topic. Hardware tools were used for
manufacturing and testing, software tools were used for extraction of required values
from test data and simulation. Hence hardware devices are manufactured and software
models derived.
The broadness of this project is a unique chance to combine lots of things learned in three
years.
Hardware,
software,
device
operation,
semiconductor
manufacturing,
mathematical modelling, theory and practice. As a result the project is a reflection of
electronic engineering.
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Background Information
The fabrication and modelling of a device requires a good knowledge on both device
operation and device manufacturing. Former is essential for testing and latter is crucial
for device properties and avoiding mistakes. Hence I divided this chapter into 2 parts.
1) Information about Device
2) Information about Process
The information will be degrading from higher level to lower level. So device
information will begin by JK Flip-Flop and end with Gate Oxide, which is the very
important part of the whole operation.
DEVICE INFORMATION
JK FLIP-FLOP
flip-flops are the most common digital data storage device with shift registers.i RS flipflop is the basic internal circuit used in most of these devices. Although a project title and
masks claim that the device manufactured is a JK, it is actually a very simple RS flipflop.
S-R flip flop:
RS flip-flop has alternative names like latch , Set-Reset flip-flop, binary, bistable and
Eccles-Jordan bistable element.1
Principles of Operation:
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Because this is a basic flip-flop, it doesn't require clock signal. So there are two inputs
and two outputs. Traditionally inputs are named as Set and Reset where outputs are called
Q and Q' (Q NOT). RS flip-flops can be made up of NAND or NOR gates. The flip-flop
used in the project consists of two NAND gates.
The NAND flip-flop circuit operates (or stores the data intact) while both inputs are logic
1. The application of 0 to the set input after the inputs were 1, changes Q to logic high
(logic 1), and Q' to 0. So the flip-flop is in a state called "Set State”. An application of a
momentary 0 to reset input after set input returns 1, will result with a Q=0 and Q'=1.
Important thing is, if both inputs face the 0 (logic low) value, both outputs Q and Q' will
go logic 1. This condition is avoided in normal flip-flop operation. 2
NAND GATE
Nand gate is the brick of complex design along with Nor gate. Theoretically all other
gates can be derived from these two, however in practice cost, speed and power
dissipation are the important factors for preference of gate selection.
Nand gate is identical to And gate except the output is inverted. So it has the opposite
operation of And gate. If any of the inputs are 0 the output will be 1. Only condition to
satisfy a logic 0 at the output will be logic 1 applied to all inputs. Number of inputs can
be in the range of 2 to 8. In the project the number of inputs are 2 per NAND gate.
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NAND gates are advantageous because they are easily manufactured. If the device is
manufactured with only pMOS or only nMOS technology, number of transistors will be
number of inputs plus 1.
The output-circuit options are open-collector, tristate and special output-expander circuits
to increase fan-outii.
The difference between pMOS and nMOS NAND gates are, in former the inputs are
applied to pull-up part and pull-down transistor is grounded, where the latter has the
opposite configuration.
Delay time for this gate is smaller for the nMOS version where pMOS version is 1.5 to 4
times slower. This is because of the different carriers in the MOS transistors.
MOSFET TRANSISTORS
MOSFET is the abbreviation for Metal-Oxide-Semiconductor Field Effect Transistor.
The first three words are the layers from top to bottom the transistor made up of. The last
three are a clue for the operation of the device.
Basic concept of the FET has been known since the 1930s but realisation of a practical
device was achieved only in 1960s. After the late 1970s MOS version of the FET devices
has been extremely popular. When compared with Bipolar Junction Transistors (BJTs),
MOS devices are simpler, they occupy less area on the wafer and manufacturing process
is relatively simple. Also, implementation of digital logic of memory circuits with just
MOSFETs (no resistors or diodes are needed), make them extremely usefuliii. Nowadays
nearly all VLSI (Very-Large-Scale-Integrated) circuits are made with MOS technology.
Device structure:
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The substrate which the transistor is manufactured on is a p-type substrate. This is a
single crystal silicon wafer with minute impurities with the Group III elements from the
periodic table. Most commonly used one is Boron. Opposite to this, there are two heavily
doped n-type regions indicated as source and drain in the substrate. Although there are no
metallurgical difference between these two, the difference is the result of their voltage
level according to Vt. There is also a thin layer of high quality oxide on the substrate.
Thickness of this layer varies from 0.02 to 0.1um of SiO2. This is an excellent electrical
insulator called gate oxide. That gate oxide area in between source and drain is called
gate. The last terminal of the MOS device is substrate also known as body. As a result
there are four terminals on a MOS transistors: gate, source, drain and substrate.
MOSFET Types
There are different kind of MOS devices mainly nMOS and pMOS. Both of these devices
are also split up in to two types, which are "enhancement" and "depletion".
pMOS is analogous to the nMOS transistor, except the majority carriers are holes and
Voltages are negative with respect to the substrate. These devices' prefixes are the
indicators for the majority carriers.
Transistor type
Majority carriers
Substrate
Source and Drain
PMOS
holes
n-type
p-type
NMOS
electrons
p-type
n-type
There are several parameters that characterise the behaviour. The first parameter of
interest is the threshold voltage Vt. Vt is very important for "operation mode" and
switching behaviour. Briefly this is the voltage value where device operates ("turns
on")iv.
Vt is a positive value for pMOS devices and it is a negative quantity for nMOS devices.
Enhancement-mode devices are the devices those are normally cut-off with zero gate
voltage.
Depletion-mode device is a conducting with a zero gate voltage.
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A MOSFET device's operation in terms of drain current and drain-source voltage are
below.
pMOS I-V Graph
Vds
-1.40E-03
Vgs=-3
-1.00E-03
Vgs=-4
-8.00E-04
Vgs=-5
-9.9
-8.9
-7.9
-6.9
-5.9
-4.9
-3.9
-2.9
-1.9
-0.9
-6.00E-04
Ids
-1.20E-03
Vgs=-6
Vgs=-7
-4.00E-04
Vgs=-8
-2.00E-04
Vgs=-9
0.00E+00
Vgs=-10
2.00E-04
This is the characteristic I-V curve of MOS transistors. From this curve, with known
threshold voltage Vt, one can easily calculate K, a constant for transistor
transconductance parameter. K is the crucial element to obtain a good spice simulation
of the device.
MOSFET device has three operating regions. These regions are :
1) Cut-off or subthreshold regionv
2) Non saturation or linear region
3) Saturation region (Saturation)
Cut-off region is the region where gate voltage Vg is less than the threshold voltage. This
is also called "Subthreshold region"vi operation.
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Depletion occurs when Vgs is very close to Vt. Drain voltage is smaller than gate voltage
minus threshold voltage.
Vds<Vgs-Vt
When the curve for this operation mode is observed, the lower part of the curve is much
linear than the upper part. Lower part is linear as Vd/Id is nearly constant, hence acting
like a resistor, but as drain-source voltage (Vds) increases curve bends, because the
channel resistance increases. This region is also called Triode region.
Saturation region is where current (Ids) saturates, and I-V curve follows a horizontal path
with a very small or no tangent at all.
The manufactured transistors for this project are enhancement mode transistors.
p-channel MOSFET (pMOS)
pMOS technology was the originally dominant onevii. UMIST cleanroom facilities are
using pMOS technology. Although nMOS dominated the technology later on, pMOS
devices are still important for discrete circuit design and CMOS (complementary MOS)
technology.
pMOS devices are fabricated on an n-substrate with p+ (p+ means heavily doped) drain
and source regions. In terms of device operation, it is very similar to nMOS except that
Vgs (gate-source voltage), Vds(drain source voltage) and Vt (threshold voltage ) are
negative. In complementary MOS devices pMOS is used at the pull-up part.
More information about pMOS devices will be examined in the next chapter
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n-channel MOSFET (nMOS)
nMOS technology came to stage after pMOS technology. Popularity of nMOS increased
very rapidly as it dominated the market. The main reasons behind this success are stated
below.
1) The nMOS devices requires lower supply voltages than pMOS, this means lower
power dissipation and less heat.
2) nMOS can be manufactured in smaller sizes than pMOS. As the size shrinks the
device speed increasesviii.
3) Electron mobility is higher than hole mobility. Because majority carriers at nMOS are
electrons, delay time is shorter.
In the design of CMOS devices, nMOS devices are used in pull-down part of the device.
MOS Capacitor
Understanding of the performance issues with MOS transistors are closely related to the
MOS capacitor. The switching speed is strongly dependent with the MOS capacitors.
Parasitic capacitance and interconnection capacitance formed by metal, polysilicon and
diffusion wires have a significant effect on total load capacitor.
MOS capacitor characteristics depend on the state of the semiconductor surface, which is
largely effected by gate voltage, Vg.
Surface has three modes. These are accumulation, depletion and inversion.
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For a p-substrate device when Vg<0, this negative Vg attracts holes to the silicon surface.
This is accumulation. The capacitance for this operation is oxide capacitance only.
When the same gate is charged with a small positive voltage with respective to the
substrate, a layer called depletion is formed under the silicon surface. This layer is
chargeless, hence acts like a dielectric. The resulting capacitor is depletion capacitor.
As the Vg gets bigger and more positive, negative charges begin to gather just under neat
the surface. This is the n-channel. In this situation, transistor is operating. But there is
another depleted layer formed just under the n-channel. Deep depletion or inversion layer
is the responsible for another form of capacitor called deep depletion capacitance, which
is in series with oxide capacitance.
To sum up, one must remember that oxide capacitance is always there. The voltage
applied to the gate determines either no, depletion or deep depletion capacitor formation.
This capacitor is in series with the oxide capacitance.
MOSFET Equations
Modelling of a realworld device is only possible with a good set of equations.
There are two very important MOSFET models. The first one is I-V model and the other
one is C-V model.
I-V model:
There are three regions of operation
1) Cut-off or subthreshold region
2) Non-saturation or linear region
3) Saturation region
The equations for a nMOS device will be different for each of them.
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1) Cut-off region:
Ids=0
Vgs<=Vt
2) Nonsaturation or triode region:
Ids=[(Vgs-Vt)*Vds-Vds2/2]
0<Vds<Vgs-Vt
3) Saturation region:
Ids=[(Vgs-Vt)2/2
As long as we know the value for Vt, determining  gets very easy.
 is the MOS transistor gain factor which depends on both the process parameters and
device geometry.
=(**W)/(tox*L)
: the effective surface mobility of the carriers in the channel
tox: the thickness of the gate insulator
 : permittivity of the insulator. (3.9*8.85*10-14F/cm) for SiO2
W: the width of channel
L: the length of channel
If Vt is known the calculation of the beta is straight forward, but to get a value for Vt
needs another graph called C-V graph.
By using C-V results, a value for threshold voltage Vt is extracted. Threshold voltage is
the voltage value for the lowest capacitance value on the graph. Explanation is simple.
MOS capacitor is consisting of an oxide and another one. From the basic maths the
equation for capacitor in series shows that as the number of capacitors in series increases,
resulting capacitor value is decreasing.
So at the very lower part of the C-V curve, the resultant capacitor value is at its smallest.
This means deep depletion (inversion mode) capacitor is formed and n-channel has
appeared just under the silicon surface. This is the voltage where transistor begins to
operate.
Vgs=Vt.
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In the project, the values for W and L are known. Both the I-V and C-V curves are
obtained from the test equipment. These will be enough to model the manufactured
transistor.
PROCESS INFORMATION
Manufacturing of a circuit on silicon requires difficult and repetitive operations. It is
difficult because the misjudgement of the experiment values (time, heat and etc.) will
result with a poor or a not-working device.
Planar process is the most commonly used method of producing junctions during the
manufacture of semiconductor devicesix. Planar process is the one that will be used for
the manufacturing of the devices. It was first introduced around 1960s. MOS devices
remained dim until this invention. Since then MOS transistors are very popular, thanks to
the invention of planar process.
Basically, it is an ordered organisation of sub processes. Most important ones are wetdry oxide growth on the silicon surface and photolithography. But before that, it is
important to know how the silicon wafer is produced.
BULK SEMICONDUCTOR GROWTH
In the manufacturing process a good quality substrate is very important. Because this
project involves silicon substrate, the focus will be bulk silicon growth.
Silicon:
Silicon, from the chemistry lessons, is a semiconductor element and atomic number is 14.
It is just under the Carbon in the periodic table column IV. Column IV elements like
Silicon and Germanium, behave strangely, they are neither real insulators nor metals. To
understand this phenomena requires a comparison of band gap energy diagrams.
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This band gap structure gives enormous flexibility of controlling the conductivity of the
semiconductor with the help of dopants from neighbouring periodic table columns. But
why especially silicon? Silicon's abundance in nature, ease of processing, occurrence of
an excellent oxide (SiO2) which is a good insulator and reasonable electronic properties
make the silicon the material of choice for most electronic devicesx. These are the most
important properties. After selecting the appropriate element (this is Silicon for this
project), how single crystal silicon is grown with exceptional purity is the next question
to be answered.
Silicon Growth:
There are two main types of silicon growth:
1) Czochralski technique
2) Bridgman technique
A substantial percentage of the (~%90) of the silicon crystals for the semiconductor
industry are prepared by the Czochralski techniquexi. Both of the devices manufactured in
this project is fabricated on Czochralski type silicon wafers.
For the sake of simplicity, process information will begin from, piranha solution
Piranha Solution:
A silicon wafer from manufacturer may contain metallic and organic substances on the
surface. To manufacture a good device, the surface of the silicon must be clean all the
time. Even a small particle may cause a leakage or broke device.
To get rid of these substances, a solution is prepared as prescribed below:
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Put 6 parts of H2SO4 inside the glass beaker and later on 1 part of H2O2 is added. This
mixture is self-heating, after cooling a bit, then another 1 part of H2O2 is placed in the
beaker. The wafer is put in to this solution for 5 to 10 minutes.
Rinsing:
This is extremely important nearly at all stages. By rinsing, contamination will be cleaned
away. De-ionised water is used for this step.
Drying:
Nitrogen is not chemically active at room temperatures and it is in abundance. In the
clean room nitrogen is used in several places. Removing the rinsing water droplets from
the wafer is a must before beginning the next step. So after rinsing, wafer is dried by
pressured Nitrogen.
Thermal Oxidation:
There are mainly two kinds of thermal oxidation. The first one is wet and the second one
is dry. In both processes the diagram is the same. Only difference is the carrier gas
entering the quartz tube. An oxide thickness growth of x , consumes a layer of silicon
0.44x thick.
Wet Oxidation:
Wet oxidation is a cruel way of growing SiO2. The wafer is placed in the quartz tube with
a temperature between 900 and 1200. A steam is blowed on to the wafer for 45minutes to
1 hour. 1hour wet oxidation at 1200C will result with an oxide thickness of up to 1m.
The equation for this reaction is:
Si(solid) + 2 H2O(gas)SiO2(solid) + 2H2(gas)
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The result of this reaction is a glass coating on the silicon.
Wet oxidation is unsuitable for Gate oxide. Instead it is used for acting as a mask for
diffusion purposes and insulator for separating transistors, various devices and leakage.
Dry Oxidation:
In dry oxidation, aim is to get a high quality and purity silicon oxide. This is achieved by
a slow but controlled growth. Si is interacted with 0xygen instead of steam. The growth is
slow but the quality of the silicon is extremely high. A good quality thin oxide layer will
be very suitable for the gate region of the transistor.
The equation for this process is:
Si(solid) +O2(gas) SiO2 (solid)
An oxidation period of 1 hour at 1200C will result with an oxide thickness of 0.2 m .
In both of these processes the crystal structure and orientation of the silicon effect growth
ratio.
Optical Lithography:
There are several ways for lithography. Because the project involves optical lithography,
the other methods for lithography will not be mentioned here. Optical lithography is
separated into several procedures.
1) Photoresist Coating: Photoresist is a radiation-sensitive compound. It is mainly
organic, which can be polymerised by Ultraviolet light, X-rays, electron beam or ion
beam. The process is carried in a clean room, which is typically illuminated, with
yellow light. This is because the Photoresist is sensitive to the wavelengths smaller
than 0.5um.
There are two types of photoresists: positive and negative photoresists.
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i)
Negative resist: The opaque areas on the mask become openings in the
surface. When exposed to UV it polymerises so unexposed areas are washed
away, leaving the exposed areas on the surface. Although negative resist is
cheaper than positive resist it has performance problem at high resolution
(small geometries).
ii)
Positive resist: The empty areas on the mask become openings in the surface.
When UV is exposed on it, it becomes soluble in developer , hence washed
away. Positive resist has a good performance but slightly expensive. It doesn't
suffer the performance problem that negative resist has.
2) The wafer is first held in a vacuum spindle and 3 to 4 drops of photoresist is applied
to the centre of wafer surface. The wafer is then rapidly accelerated up to a constant
rotational speed for at least 30 seconds. Spin speed is in the range of 1000 to 10000
rpm. This spinning will give a uniform photoresist thickness.
3) Pre-exposure baking: After spinning, the surface of the silicon is sticky and the
solvent in the photoresist had to be removed. By baking the coated wafer at a
temperature 80 to 100 C will eliminate these problems and improve the resist
adhesion to the wafer
4) Masks: Discrete, small and medium scale integration begins with generation of
patterns which are 100 times to 2000 times bigger than the final size. Schematics or
artwork is drawn for each layer. Nowadays there are various softwares which will
separate the layers from a diagram of the design. Various layers are then placed on to
the separate masks. A small mask defect may result with the failure of the device.
Masks are made from quartz or glass and they have chromium coating on one side of
them. The coated side will be proximiting to the surface of the silicon for transferring
the pattern to the silicon.
5) Exposure:
There are two main optical exposure methods:
shadow(projection)
printing and contact(proximity) printingxii.
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a) Projection Printing: This printing technique relays on high quality optics. To
achieve an optimum printing the mask and the wafer are moved together through
a well-collimated beam or spot of light. The wafer and the masks are not
damaged, because they are not close to damage each other. This improves defect
densities and mask life.
b) Proximity Printing: This process is characterised by getting the mask as close as
possible to the surface of the wafer to minimise errors due to dispersion of the
light beam of vibration. There are cases in which the mask may be touching the
top of the wafer during exposure called contact printing. In other cases, the mask
and wafer will be just very close and this is called proximity printing. In the
project contact printing is used to transfer the pattern on the mask to the wafer.
The machinery for this kind of printing is relatively cheap but there is a high risk
of mechanical damage for both the mask and the wafer.
6) Development: The exposed image on the wafer must be developed. The technique is
similar to photography. Depending on the photoresist used exposed areas of
photoresist will washed away or stay. After development, a pattern of photoresist,
which is similar to mask, will stay.
7) Post-baking: After development another baking is done for 15-30 minutes to make
ready photoresist for etching and removing water particles.
8) Etching: The pattern in the photoresist is transferred to the thin oxide film by etching.
The photoresist will prevent the area directly under it from being etched, so where
ever there is no photoresist, it will be etched to hole. Although there are several types
of etching, during the manufacturing process wet etching is used.
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a) Wet etching uses liquid chemicals to dissolve certain materials. For example HF
is used to etch SiO2 film which is patterned. Wet etching is also sub-categorised
in to two parts. Isotropic and Anistropic
i)
Isotropic means that the etching rate is same in all directions. This will
provide sloped steps to grant good step coverage.
ii)
Anistropic conveys that the etching is faster in a specific direction. This
kind of etching is needed if vertical etch is needed.
b) Dry etching includes two techniques plasma and sputter etching. Wet chemicals
are not used in this process.
9) Stripping: After etching there is no need for photoresist, so it has to be removed. This
can be done wet or dry. For Shipley photoresist acetone will be enough to remove
photoresist layer
Diffusion:
Diffusion is the key process in the project to introduce controlled amounts of dopants into
semiconductor. Diffusion is the combination of two separate processes: deposition and
diffusion. The first one, places the dopant on to the surface and second one drives the
dopant into the bulk of the wafer.
a) Deposition: Deposition is the process that introduces dopant atoms to the surface
of the semiconductorxiii. This can be done in two ways
i)
Chemical Deposition: This process is a chemical reaction between the
dopant source and the semiconductor material. The source dopant is
passed over wafer at a temperature of several hundred degrees. Dopant
vapour is formed by passing oxygen through a liquid source. As an
example, liquid source can be POCl3 (phosphorus oxychloride) and BBr3,
Boron tribromide. The resulting vapour is carried inside the tube by O2.
Although the equipment for this process is relatively cheap, control over
the process is not precise.
25
ii)
Ion implantation: Dopant atoms are introduced to the wafer physically by
ion implanter.
To make it clear with an analogy, it is like a gun firing bullets and hitting
the target. As a result certain amount of damage is done to the surface,
turning it into an amorphous layer. The other problem is dopant atoms will
not be electrically active because they will have a tendency the occupy the
gaps between the atoms in the lattice. Crystal structure has an effect on
this. Apart from all these, it has the advantage of uniform and controlled
doping.
In the manufacturing process deposition is achieved by applying liquid Boron or
Phosphorus solution on to the surface and spinning as in the photoresist case.
b) Diffusion: The deposited dopant on the surface is drive in to the crystal. The
effect is purely physical and the highly concentrated dopant at the surface is
diffused inside with the help of heat. Diffusion occurs in a furnace tube with a
strictly controlled temperature. The longer and the hotter the diffusion the deeper
the dopant will spread. The distribution of the dopants is not uniform in the bulk
and it decreases with the increasing depth. Gaussian distribution models diffusion.
Metallisation:
Metallisation is applied for forming interconnections, ohmic contacts and rectifying
metal-semiconductor contacts. Metal films can be formed in various methods. Physical
vapour deposition and chemical vapour deposition are the most important ones.
Aluminium and its alloys are used extensively for discrete devices and integrated circuits.
Physical Vapour deposition is the technique used in the project. This technique coats the
surface of the wafer by evaporating Aluminium at a very low temperature.
26
Manufacturing and Testing
Introduction
Manufacturing and Testing are the two very important part of the project. pMOS and
nMOS devices are made during the manufacturing process and the transistor on both of
them were tested using necessary equipment. There were 4 masks for each of the them.
These 4 masks are included in the appendices. Although manufacturing process is nearly
a straightforward process, it is explained here again because more than 3/5 of the project
time was spent on fabricating devices.
The manufacturing of pMOS device was a learning process for this project. Through this
period semiconductor processing techniques are improved and new ideas emerge. By
carrying the experience to the nMOS manufacturing, several new results obtained. pMOS
is the only technology available in the UMIST cleanroom, hence nMOS manufacturing
was a new challenge. To get the very best results all the data and experience from pMOS
manufacturing was combined with the patience and consistence to make an nMOS
transistor. pMOS process was began by four pieces of quarter wafers and ended up with
three quarter wafers. One of the wafer was experimented for thin oxide etching. In the
nMOS case it was the same number of wafers used, but to the end one wafer was carried
out. The other three of them carried to the various stages and used as a "road map" for the
real nMOS device. This chapter will discuss the routine procedure of pMOS
manufacturing and then nMOS manufacturing steps will follow. The chapter will
conclude with testing of the transistors. The photographs of the nMOS device can be
found in Appendix.
pMOS Manufacturing
pMOS manufacturing is a straight ahead process. This period is a kind of gaining
experience, guessing the possible problems for nMOS and trying to understand the logic
27
of everything done for semiconductor processing. More information is available in the
1996 2nd year Design and Fabrication of Microelectronic Components laboratory sheet.
Semiconductor manufacturing is a time consuming and care needing process. From the
very entrance to the lab to the end of every step must be done with lots of care and
cleanness.
pMOS manufacturing was done in 4 mask levels and took nearly 4 weeks. Although this
process takes 24 hours in total, Mondays and Fridays the lab was reserved for 3 rd year
Semiconductor devices. In normal circumstances with a previous knowledge this may be
done in two weeks.
To begin the process, an n-type substrate, 111 crystal oriented Czoylski wafer was taken.
This wafer was cut into 4 pieces with diamond tipped pencil. Although there is no
material harder than diamond, 111 orientation of the crystal was hardly broken. To avoid
any shattering of the crystal, the pieces were separated using a paper and a lead rod.
Cleaning
As a thumb rule, the cleaner every step goes, the better the change of having a working
device. So the wafer is cleaned with piranha solution as mentioned in the background
information chapter. A glass beaker is taken and 4 parts of H2SO4 is mixed with 2 parts
of H2O2. This is an exothermic event, which means the process it self is heat producing.
The wafers are carefully placed into the beaker and waited for 10-12 minutes. This has
been done to remove any metal or organic contamination on the chip wafer. After piranha
solution, the wafers has been rinsed for 10 minutes and made ready for buffered HF
solution. Buffered HF is a degraded HF. Chemically HF is the most reactive acid and it
can even react with glass. To avoid any glass melting, a plastic beaker was used . The
wafers were put in to the solution for 10-15 minutes. This step is required for removing
any previous oxide on the surface before any wet etching. The same rinsing process is
repeated for 15 minutes and the wafers left in the water till oxidation tube is ready.
28
The UMIST pMOS Process
1) Masking (Wet) Oxide: The wafer pieces are put in the centre of Wet oxide furnace
tube. The temperature was set to 1200C. A gas is blowed in to the tube. This is
oxygen passed through water at 95C. The process lasts 1 hour. And the resulting
thickness is 1um.
2) Mask 1: A positive photoresist is spun onto the wet oxidised wafer. Afterwards it was
pre baked. Mask 1 is used in mask aligner and the wafer is placed under Mask 1. The
U.V light is exposed and the resist pattern is developed and baked at 120C. The wafer
is etched using HF. The pattern on the photoresist is now transferred to the oxide. The
resist is removed with acetone.
3) Boron Diffusion: Boronsilica solution is applied to the surface of the wafer, then it
was spun and baked for a few minutes. The wafer is placed in Boron diffusion tube
for half an hour with a temperature of 1050C.
4) Mask 2 - Gate Oxide: The photoresist is spun on to the wafer, and the UV light is
exposed through mask 2 on to the wafer using mask aligner. This will define the gate
oxide areas. Developing and etching follows. The etched regions will be the places
where dry oxide will grow. The wafer is placed in dry oxidation furnace and very
good quality gate oxide is grown on top of the etched regions.
5) Mask 3 – Contact Holes: As the surface of the wafer is covered with silicon dioxide,
the contact holes will be opened on the gate oxide to contact drain, source and other
areas. The same photolithography process is repeated with mask 3.
6) Mask 4 – Metallisation: The last step is to deposit aluminium on the wafer surface.
This is achieved by evaporating aluminium from a hot filament in the vacuum. Same
photolithography steps followed. This time as etchant Aluminium Etchant was used.
This is a phosphoric acid based etchant.
29
This concluded pMOS fabrication. In the next part nMOS fabrication will be examined.
nMOS Manufacturing
Although nMOS fabrication process is not very different from pMOS fabrication,
because it is done first time, a more detailed examination will be given.
The starting material is p-type substrate with 111 crystal orientation.
The standard procedure of cleaning the wafer is done first and the fabrication begins with
the same Wet (Thick) oxidation.
Wet Oxidation
To wet oxidise (thick oxide) wafers, several procedures must be done. Wet oxidation is
different from dry oxidation by using water vapour instead of O2 inside the quartz tube.
Quartz tube for wet oxidation has a flask attached to it. After setting up the temperature
of the tube to 1200C, flask's ¾'s was filled with water. The heater for the for the flask was
turned on. The nitrogen tap was turned off and O2 tap has been opened. The O2 will
carry the water vapour to the tube and there a rapid and cruel SiO2 will emerge on the top
of the wafer surface. The wafers were carefully placed in a quartz carriage. When the
temperature get to the 1200C, the wafers are removed from de-ionised water, blowed dry
and placed inside the tube. For the next 1 hour, the wafer is left inside the wet oxide tube
for wet oxidation. Resulting thick oxide was used for masking and insulation purposes.
The thickness of the oxide is around 1 um.
30
Photoresist Coating
After taking the samples out of the tube, positive photoresist (Shipley) is applied to the
surface and spun for 30 seconds with 5000 rpm. To remove the stickiness and the solvent
in the photoresist, the coated wafers were put inside the pre-exposure (pre-bake) oven for
15 minutes. The temperature of this oven is 90C. The samples were then taken out for
exposure.
Mask 1
At this stage the whole surface of the substrate is covered with thick oxide and on top of
it, there is a layer of photoresist coating. The nitrogen taps for the exposure machine and
the status of the UV lamp was checked. Mask 1 was put in its place in the exposure
machine and wafer was positioned on top of a cylinder and with the help of vacuum it
was driven in just under the mask1. There is no need for mask alignment at this stage.
The samples were exposed to UV light for 110 seconds. Afterwards they have set into
developer solution. Developer solution spilled into a plastic beaker and the samples were
sank into the solution for 2 minutes and 45 seconds. They rinsed for 10 minutes. Later,
they were examined under microscope if they have developed properly. Development is
followed by a post-exposure bake (post-bake) for 15 minutes at 120C. As the trays
removed from the oven, a buffered HF solution applied for 4 minutes. This is the etching
process. Rinsing again follows etching process. After rinsing, the samples checked under
microscope to check if the etching was done as expected. The remaining photoresist
coating is removed by acetone and rinsed again.
31
Phosphorus Diffusion
The pattern on the mask 1 was transferred to the thick oxide on the silicon substrate. This
patterned (or etched) oxide will be used as a mask for boron diffusion. The rinsed wafers
are blowed dry with pressured nitrogen and brought to spinner again. A Phosphorus
solution was spilled on to the wafer and spun at 5000rpm for 30 seconds. This time the
wafer was put in the newly fitted phosphorus tube. The temperature was set to 1050C
degrees. One parts of oxygen to around three parts of nitrogen was used as a gas mixture
inside the tube. This process lasted for 40 minutes.
Mask 2
The diffusion is finished now, and the areas for gate oxide growth must be defined. First
same positive photoresist is used to coat the surface of the wafer with spinner. The
spinner settings are same as before. Pre-baked and then placed under mask 2 in the mask
aligner. Exposure time was 110 seconds. The wafer is developed for 2 minutes 45
seconds and then pre-baked for 20 minutes. The etching process with buffered HF
followed. Etching time was around 3 minutes. By completing this step, the regions to
grow dry oxide were defined. The next step is gate oxide growth.
Gate Oxide (Thin oxide) Growth
Temperature of the dry oxidation tube was set to a temperature of 1200C. This time no
water vapour is needed, because the desired oxide must grow slowly and controlled. The
wafers are placed in the dry oxidation tube with full oxygen and no nitrogen at all for 15
minutes. After 15 minutes the oxygen inlet was closed and nitrogen was allowed to the
tube. Although there is no oxygen entrance to the tube, the remaining oxygen in the tube
will continue oxidation for another 5-7 minutes. The total length of the process is 1 hour.
As a result, in the first 15 minutes there was only Oxygen in the tube and the last 45
minutes Nitrogen was the only gas entering the tube.
32
Mask 3 – Contact Holes and Gate Oxide Etching
Gate oxide growth and etching are two key operations of the whole process. High quality
oxide must be etched properly, otherwise the device will not work at all. First of all, the
important thing was a correct decision about etching time.
70 seconds etching, was first to be implemented. The buffered HF solution was poured
carefully in to the plastic beaker. One of the four samples was used as a "cobay". A
plastic handler was used to submerge that wafer in to the HF solution and left there for 70
seconds. A quick rinse followed this. The wafers were carefully checked under
microscope and a suspicion aroused about a serious undercutting. After a series of
discussions with several members of the staff, photoresist layer was removed by acetone.
It was obvious at that stage that the undercutting was more serious than expected. The
wafer was retired for photographing the undercutting.
A time period of 70 seconds was too much for etching thin oxide, a new strategy was
needed. This time a lower time period is decided.
45 seconds was the final decision about etching time. This time was discussed with
several people and a rough calculation of etching was made according to the "guessed"
thin oxide thickness. The same solution was applied for 45 seconds. Another wafer was
used this time. At the end of etching, the same rinsing process followed. It was blowed to
dry with Nitrogen and placed under the microscope. The results were more promising.
The photoresist removed and it was obvious that the etching was perfect. The remaining
2 wafers were etched for 45 seconds and photoresist is removed. They were all at the
desired level.
Metallisation
Metallisation is the last and the least important step. Any mistake during metallisation
can be recovered by removing the metal by etchant and repeating evaporation again.
33
The metal evaporator is opened, and checked if the aluminium is preloaded. The wafer is
placed upside down on the filament. Evaporator was closed tightly and the air inside was
evacuated using rotary pump. When vacuum level > 10e-1, the pump is changed to
diffusion pump. For 20 minutes the diffusion pump is left open to have a good vacuum
inside. Voltage is applied through filament and aluminium is evaporated. Diffusion pump
is closed and the chamber was opened. The wafer's surface is mirrored.
Mask 4
The metal-coated wafer is now headed to spinner. The spin speed was 5000 rpm and the
positive photoresist was used. Spinning lasted 30 seconds and then pre-baked for 5
minutes. Mask 4 is placed in mask aligner and exposed for 80 seconds this time. This
reduction of exposing time is due to the shiny surface of the wafer. Developing followed
for 1 minute. The wafer is then washed in de-ionised water. A post-bake is proceeded for
10 minutes at 120C.
Phosphoric-based acid etchant is used to strip off the aluminium this time. There is no
precise etching time for this operation, hence the wafers are carefully observed. When
aluminium is seen to strip off the wafer is taken out and rinsed with de-ionised water.
This concludes the fabrication of nMOS device, which took 4 weeks to finish.
Testing
The fabricated devices are tested for plotting two curves. The first one is I-V curve and
the second one is C-V curve.
After metallisation, the devices first sintered at the sintering furnace for 10 minutes.
Sintering will harden the metal. As the sintering finished the devices are placed in plastic
caps to carry to the test room.
First of all C-V curve is tested using HP Semiconductor parameter analyser. This test
equipment has needles and with the help of needles, under the microscope the device’s
pads are connected to the cables to test the required values. After the needles are set in
place, the device characteristics tested for different Vds and Vgs values. If the test results
34
are similar to the typical characteristic I-V curve for the MOS transistor, the device is
then packaged and taken to another room for high frequency C-V characteristics of the
device. The testing equipment is Hp4044 and it is connected to a PC. PC has a Visual
Basic program interface for testing. By putting the required testing parameters. It
produces the curves and saves them in a file.
Both MOS devices have 6 transistors, but 2 of them is grounded.(or connected to the
source and ground) only 4 of them is suitable for test purposes.
First the source, drain and gate pads of the device is determined. And the necessary
inputs to the pads are double-checked. Afterwards the test results are saved in a file for
later use. Some results are attached as appendices.
The outcome of the test results will be discussed in the next chapter.
35
Analysing the Data and Simulation
Introduction
This chapter will explain the roadmap from a fabricated device to a spice model
of that device. Firstly, the technique will be described and exampled by the pMOS
transistor that was manufactured. Later on the test results of the nMOS will be discussed.
Through out the discussion, the reader must be aware that the sampled test results are not
the only test results. There are around 20 tests done for pMOS and another 20 tests done
for nMOS device.
pMOS Device and Spice Model:
The device that has been tested was a pMOS enhancement transistor. The
substrate was n-type and the Boronsilica film was used for diffusion. The substrate is
czrolyski type wafer. Before analysing data, an examination of the spice parameters is
essential.
For this modelling, three parameters of SPICE will be used.
MOSFET Model parameters
Spice Name
Model Parameter
Units
Default
LEVEL
Model index (e.g. 1,2 or 3)
-
1
VTO
Zero-bias threshold voltage
V
0
KP
Transconductance Parameter
A/V2
2.0 * 10e-5
Level has three values.
1) Level 1: Schichman-Hodges
2) Level 2: MOS2, an analytical model
3) Level 3: MOS3, a semi-emprical model
Level value is not very important at this point, the model will be based on Level 1 value.
The other 2 parameters are the essentials. The other DC parameters like LAMBDA
(Channel length modulation), PHI(Surface Potential) and GAMMA (Bulk threshold
parameter) has not been considered for the sake of simplicity.
36
Threshold Voltage Parameter (VTO)
The Background Information chapter explains MOS capacitor, and MOS capacitor plot
reading. There were three cases:
a) Accumulation
b) Depletion
c) Inversion
When the channel was formed first time(inversion), the capacitor value drops to its
lowest value. This means when the gate voltage reaches the threshold voltage, the
capacitor value will be the lowest value on the plot. After threshold voltage is exceeded,
the capacitor value increases a bit more and then stays nearly same. Therefore by a close
examination of C-V plot will reveal the threshold voltage.
The Capacitor test results were saved in a text file and this text file is opened with
Microsoft Excel. There are six type of values saved in this file. To extract the necessary
threshold voltage only two of them were taken into consideration. These are Voltage and
C-V values. If the x axis is voltage value and the y axis is capacitance, the resulting graph
will look like this:
Voltage (V)
-9.1
-7.6
-6
-4.5
-3
-1.4
0.1
1.63
3.16
40
35
30
25
20
15
10
5
0
4.69
Capacitance (pF)
pMOS C-V Graph
37
As the graph clearly shows the threshold voltage is in between 0.1 and –3 volts. A very
basic Excel command is used to find which C-V value was the minimum of the whole
column. An empty cell below the C-V column is selected and "=MIN (D6: D53)" is
typed. The result was 17.26. The row that is matching this value is A27. 'A' column was
used as Voltage value. The voltage value for A27 is –1.734. At this voltage value the
capacitor value is at its lowest and p-channel is formed for the first time. That means this
is the nearest value of the Threshold voltage. As a result Threshold voltage is –1.734.
So:
VTO=Threshold Voltage=-1.734
Note: At this point it is important to state that the real equation for Vt is
Vt=Vto +  [ [2b+Vsb]-[2b]
where  is the constant that describes the surface bias effect and Vsb is the difference
between source and substrate.
Because the tested transistors source is connected to substrate Vsb automatically reduces
to 0. As a result equation reduces to
Vt=Vto
This value will be used to get KP value.
Transconductance Parameter:
Before examining Transconductance parameter, it will be useful to have a look at I-V
plot of pMOS device. Gate source voltage Vgs is decreased from 0 to –10 Volts with –1
volt steps. Drain source voltage, Vds, between 0 to –10 volts is applied for every gate
source Voltage. The final plot is indicated below.
38
pMOS I-V Graph
Vds
-1.40E-03
Vgs=-3
-1.00E-03
Vgs=-4
-8.00E-04
Vgs=-5
-9.9
-8.9
-7.9
-6.9
-5.9
-4.9
-3.9
-2.9
-1.9
-0.9
-6.00E-04
Ids
-1.20E-03
Vgs=-6
Vgs=-7
-4.00E-04
Vgs=-8
-2.00E-04
Vgs=-9
0.00E+00
Vgs=-10
2.00E-04
As the graph reflects a typical pMOS transistor characteristic, the numerical values will
be used to extract a value for KP. Transistor plot has three regions
1) ids=0
for Vgs<Vt
2) ids=K(2(Vgs-Vt)Vds-Vds2) (1+vds)
for Vgs>Vt and Vds<=Vgs-Vt
3) ids=K(Vgs-Vt)2 (I+vds)
for Vgs>Vt and Vds>=Vgs-Vt
where K =1/2  Cox (W/L)
For calculation purposes lambda Vds equals to zero. The third equation above becomes:
ids=K(Vgs-Vt)2
If the equation the equation is organised again K will equal to:
K=ids/ (Vgs-Vt)2.
The third equation is chosen because excluding Vds from calculations will be a bit more
helpful and a constant K value is expected at saturation for different gate source voltages.
The Excel sheet is opened, and the column next to Ids is labelled, as K. this column will
be the calculation column for K value. "=C4/POWER (A4-G4, 2)" is typed under the "K"
39
labelled cell. Now by dragging this calculation for the entire column will reveal some
values. At the beginning it has been said that, only the saturation region is considered. So
the values for the highest Vds values are to be averaged to get an approximate K value.
For Vds=-9.9, the K values for Vgs=-10,-9,-8,-7,-6,-5,-4 is averaged, the result has
appeared to be:
K=-2.2*10e-5
And then a set of equation is solved for pull-up transistor Width=30um and
Length=10um micrometer. The variable investigated is KP
KP= Cox
and
K=1/2 Cox (w/l)
so
K=KP*(w/2l)
hence
KP=(K*2l)/w
The numeric values are substituted and result came out as:
KP=K*2l/w=1.47*10e-5
Which is a reasonable value.
To sum up everything, the value for
VTO=-1.734,
KP=1.47*10e-5 and
LEVEL=1
PMOS Spice Model
In this part from the values a Spice model will be derived. Firstly, this model will be used
for a small circuit and then a digital simulation will be done.
To define a model in spice ". model" label is used. The standart notation is
.model <name_of_the_model> <type> (parameters)
The transistor model will have a name pmos_enhancement_mosfet for obvious reasons.
Type will be pMOS and parameters VTO and KP will be inserted in the parentheses.
VTO will stay same, but KP will be transformed into a different notation.
40
1.47e10e-5=14.7*10e-6. Since 10e-6 is called micro, the value will transform into 14.7u.
(u for micro)
The resulting notation is:
".model pmos_enhancement_mosfet pmos (kp=14.7u Vto=-1.734 lambda=0)"
Where lambda is channel length modulation.
Then whenever a new transistor is used, the following notation will be used.
<name_of_the_transistor> <drain> < gate> <source> <substrate> L=<#> W=<#>
drain,gate, source and substrate will be node numbers. L and W will be length and width
of the transistor.
So a notation for transistor M1 is:
M1 3 2 1 1 pmos_enhancement_mosfet pmos (kp=14.7u Vto=-1.734 lambda=0)
An example script for a circuit is given.
An Enhancement-Mode PMOS Circuit
**Circuit description **
** DC supplies
Vdd 1 0 DC +7V
*MOSFET Circuit
M1 3 2 1 1 p_mos_enhancement_mosfet L=10u W=30u
Rd 3 0 10k
Rg1 1 1 4Meg
Rg2 2 0 5Meg
*MOSFET model description (LEVEL=1)
.model pmos_enhancement_mosfet pmos (kp=14.7u Vto=-1.734 lambda=0)
*Analysis
*calculate DC bias point
.OP
** output requests **
*none required
41
.end
Although this is an example script, in the appendix the real spice script for the following
circuit is given. This script was not typed instead the Electronic Workbench is used to
produce the Spice File. This is a schematic diagram of a pMOS transistor SR Flip-Flop.
Simulation results are matching the operation of a real SR flip-flop
42
nMOS Data Analysing
nMOS device test results were not promising. Nearly most of the transistors on
the wafer were tested, this lasted more than 8 hours in 1.5 weeks. Different voltage levels
were tried. 9 of the test results were saved for close examination. Device operation was
puzzling and it is very hard to guess about the real reason.
At the end of this part possible reasons for malfunctioning will be explained.
After that a theoretical study of modelling a 'working' nMOS will be carried out.
nMOS Results
The tests were carried out with innumerable different options. Drain source
voltage was varying in between -4 to 9 volts and gate source voltage was applied from –5
to 9 volts. The results were much more alike. As an example a typical data is plotted as
seen below:
43
5.00E-03
4.00E-03
-1.5 Volts
3.00E-03
2.00E-03
-0.5 Volts
0.5 Volts
1.00E-03
1.5 Volts
2.5 Volts
+0
0
0E
+0
0
9.0
0E
+0
0
7.5
0E
+0
0
6.0
0E
+0
0
4.5
0E
3.0
0E
1.5
0.0
0E
+0
0
-1.00E-03
+0
0
0.00E+00
As seen from the graph this is not a nMOS I-V graph. But the amazing thing is as the gate
voltage increases Ids-Vds curve changes. It seems as if the gate voltage has an effect on
the current flowing. Although it is not the desired effect a modulation of gate voltage is
observable. This is really strange that as the gate voltage increases the channel is formed
with an increasing delay. As the voltage goes negative the n-channel is conducting with
the smallest Vds value, where as the gate voltage increases positively n-channel is
desiring for more Vds voltage to conduct. The gate voltage increase is acting like a
barrier. Why is it like that?
A Possible Theory:
Before examining the results, it is important to review what are the clues.
44
1) a p-type substrate
2) an n-type dopant for diffusion (Phosphorus)
3) As gate voltage increases current Ids decreases.
Under the gate oxide the region is p-type and under the drain and the source, the region is
n-type.
The most important clue is the 3rd one. As the gate voltage increases current Ids
decreases. So it seems as if there is a Field effect it is not pulling electrons for n-channel
formation but it is repelling them, and decreasing the current.
Hypothesis: The region under the gate oxide is not the p-substrate, but a p-substrate area
surrounded by diffused Phosphorus.
Here is a possible cross section diagram of nMOS for this hypothesis.
As the gate voltage increases p region will try to expand, this will weaken the diffusion
layer connection beneath. Or another cross section graph may include some n+ dopants at
the surface below the gate oxide.
The basic logic here is an expanding p-substrate area and hence trying to break
connection of diffusion regions under it. As far as the graphs concerned, this may be a
possible reason. But there may be other reasons and this may be wrong. But it is absolute
that the malfunctioning is caused because of a problem with diffusion.
Diffusion Problem and More reasons
When the project first started, there was no nMOS transistor fabricated yet. There were
some experiments with Phosphorus or n-type devices in the cleanroom but no results or
problems faced before, was available. During nMOS diffusion the first problem to occur
45
was the deposition of Phosphorus solution. The solution was too old and it may not work
properly. It has been claimed a new solution 'may' arrive in two weeks but after the first
part of the project - pMOS fabrication was lasted more than expected, this will be a big
problem. pMOS fabrication lasted longer than expected because of third year electronics
lab schedule. Mondays and Fridays the labs were closed for teaching. And one
Wednesday, there was open day. So the decision is made to carry out with the existing
solution and see if it is working. But before doing that, there was another very big
problem.
There was no tube for phosphorus diffusion. It took one week to fit a phosphorus tube
and make it ready for working at high temperatures. After several days of 24 hour
working at 600C the tube was finally ready for phosphorus (n-type doping). The last
problem occurred when the oxygen is needed for phosphorus tube. There was no oxygen
inlet to the tube, and there was no room for an Oxygen pressure-meter on the panel near
the tube. The staff member sorted out this problem in a wise manner. The sintering tube's
oxygen pressure-meter was used for phosphorus tube by redirecting the plastic pipes of
oxygen.
After the diffusion the other stages progressed as expected.
So, to sum up the problems:
1) There was no phosphorus diffusion tube in the clean room before.
2) The phosphorus solution was out of date
3) There was no prior knowledge of an n-type doping for MOSFET in the clean room
As a result, diffusion stages gone wrong which resulted with an unexpected diffusion.
And at this stage probably phosphorus solution is the main reason for horribly wrong
diffusion process.
Now, the following part will examine how spice modelling should be derived if a
working device is fabricated
46
nMOS Spice Model
The procedure is the same as it is in pMOS. First a C-V plot will be examined. The C-V
curve's lowest value will be marked and the voltage value corresponding to this value is
recorded. Because the assumption is source is connected to substrate, the equation
Vt=Vto +  [ [2b+Vsb]-[2b]
will again reduce to
Vt=Vto.
As a result the value recorded will be our VTO value for spice model.
After that, I-V plot is examined. The saturation region is the main focus. The test results
will be converted to an Excel spreadsheet. A new column is used for calculating K from
the equation:
Ids=K(Vgs-Vt)2 (Saturation equation)
The average value for K is calculated. This calculation involves only the saturation
regions for different gate voltages. To make the calculations safe the gate voltages higher
than twice the threshold voltage is considered. For these gate voltages only the K values
for highest Vds voltages will be considered. The average of the indicated K values will be
used as the K value. This numeric value will be placed in an equation with width and
length values of gate oxide to obtain KP.
The equation is
K=1/2(KP)(W/L)
KP=2KL/W
So the KP value will be calculated.
As KP and VTO is known, the next step is typing the notation.
Spice notation for nMOS:
The expected device was an nMOS enhancement transistor. So the notation will be same
with pMOS apart from the names.
.model nmos_enhancement_mosfet nmos (kp=<KPvalue> Vto=<VTOvalue> lambda=0)
If the KP =25*10e-6 and Vto=+1.7V the notation will look like this
.model nmos_enhancement_mosfet nmos (kp=25u vto=+1.75V lambda=0)
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For any transistor T1 with a gate length of 10um and gate width of 30um, this model will
be used as follows:
T1 1 2 0 0 nmos_enhancement_mosfet L=10um W=30um
Inverter Example
To show practical cases an nMOS inverter circuit simulation may be done as given.
Spice listing:
An Enhancement nMOS Inverter
** Circuit Description **
** DC supplies
Vdd 1 0 DC +5V
** input digital signal
Vi 3 0 DC 0V
** MOSFET Circuit
T1 2 3 0 0 nmos_enhancement_mosfet L=10um W=30um
T2 1 1 2 2 nmos_enhancement_mosfet L=30um W=10um
** MOSFET model statement (by default level 1)
.model nmos_enhancement_mosfet nmos (kp=25u Vto=+1.75V lambda=0)
** Analysis Requests **
.DC Vi 0V +5V 100mV
** Output requests **
.Plot DC V(2)
.probe
.end
Conclusion
Through out this chapter, the strategy of climbing from a hardware level to a
mathematical model or spice model is examined and sampled. As seen from the samples
the strategy is simple yet very effective. By knowing a MOSFET device's I-V model and
C-V model, process discussed here is the fastest path. To conclude this chapter a table
summarising the things done is presented below.
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Step
Process
Output
no
Plot the C-V graph from test results and obtain the VTO
minimum Capacitance value C. Find the corresponding V
1
value for this C.
By simplification V will equal to
Vthreshold hence VTO.
Use the VTO value as threshold voltage for saturation
2
region of the I-V plot. Use the equations to find K. From
KP
K, by knowing the device geometry, calculate KP
3
Put the VTO, KP and LAYER (=1) to derive a model for MOSFET
the transistor. If necessary assign 0 value to LAMBDA.
MODEL
Use this model as a template, by knowing gate oxide length TRANSISTOR
4
and width, type the notation for specific transistor.
DEFINITION
5
Convert the circuit diagram to spice code.
SPICE CODE
6
Simulate the spice code
SIMULATION
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Conclusion
In this chapter, the outcome of this project is reviewed and commented. At the end,
suggestions for further work are discussed.
Results:
As stated in the introduction chapter, nearly all the initial aims were reached. The
malfunctioning nMOS device was not very surprising. Because this was the first time
nMOS technology is tried in D16 cleanroom. If one considers, the phosphorus tube was
fitted and tried first time and the use of out-of-date phosphorus solution, the outcome will
not be an unexpected thing. Although this project showed that pMOS process might be
the best process for UMIST cleanroom, new challenges will open new doors to
innovation. nMOS device didn't worked this time, but maybe some year later, someone
will design the process in a manner to fabricate a working nMOS transistor using the data
from this project. The aim was to climb to the highest point of the mountain, but failed.
At least the flag was erected at the point this project achieved, so someone can carry out
from this place.
To sum up, here is a list of results achieved.
1) A fabricated pMOS device
2) A fabricated nMOS device
3) Test results for pMOS device
4) Test results for nMOS device
5) Analyses of plots
6) Model of the pMOS device
7) A 'possible' model of the nMOS device
8) Simulation of pMOS transistor
9) Simulation of pMOS flip-flop
10) A 'possible' simulation script for nMOS device
As a result pMOS fabrication is better for UMIST at this moment, but with the help of
upgrading the equipment, nMOS and even CMOS technology is open to discussion.
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Also topics covered and tool used opened new doors to understanding of electronics.
The topics covered through this project are surprisingly different.
1) MOSFET device operation
2) Semiconductor device fabrication
3) Fault finding
4) Modelling
5) Simulation
The tools used through out this subject are also various.
1) Hardware
a) Device fabrication equipment
b) Device testing equipment
2) Software
a) Excel
b) Mathematica
c) SIMPLer
d) SPICE
e) Word
Comment:
This final year project was a great opportunity for me to review and learn lots of different
topics and combining them. The MOSFET device operation, device characteristics,
fabrication, testing, interpreting test results, mathematical modelling, spice modelling and
simulations were covered through out the project. Of course this much of topics are very
hard to organise in a small report like this and when you combine the horrible writing
skills of the student, the reflections of this project may not be very impressive. But the
understanding I gained while progressing through each step is invaluable. By the help of
the problems that has been faced, time limitations and unexpected results, a new
understanding of electronics developed in my mind.
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Further Suggestions:
As stated before, this final year project tried the challenge of fabricating an nMOS
transistor in a cleanroom where the dominant technology is pMOS. I believe fabrication
of a 'working' nMOS device is possible in UMIST and a better spice models can be
derived. Before doing this kind of projects more experience of fabrication is suggested.
This will lead to a better device. As a last suggestion, a new chip must be designed. The
chip must include the same type of transistors but different geometries.
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Appendix 1
Feasibility Report
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Appendix 2
Photos of nMOS fabrication
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Appendix 3
Excel Spreadsheets
55
Appendix 4
Masks
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References
i
Handbook of Microcircuit Design and Application (Stout and Kaufman Chapter 4-1)
Digital Design (second edition) M. Morris Mano Chapter 6 page 205
ii
Handbook of Microcircuit Design and Application Chapter 3-4
iii
Microelectronic circuits, Sedra-Smith page 354
iv
Principles of CMOS VLSI design
v
CMOS VLSI design
vi
Sze, Semiconductor devices, Physics and Technology page 203
vii
Sedra-smith 364
viii
York,Trevor, VLSI design, Lecture notes
ix
The dictionary of electronics E.C Young page 430
x
Semiconductor devices Jasprit Singh
xi
Sze Semiconductor devices, Physics and Technology page 302
xii
Sze, Semiconductor devices, Physics and Technology 11.1 page 431
xiii
Texas Instruments Wafer Fabrication Basic Technology overview
2
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