Computer Engineering Department
Computer Architecture I Lab (ACOE201)
Experiment #3
Adders
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Computer Architecture Lab - ACOE201
Experiment #3:
Adders
Objectives:
To examine the design and operation of arithmetic circuits (adders) used in CPUs.
Conventions:
The
symbol indicates an operation that must be done in hardware e.g. pressing a
button or switch, making a connection on the board, a jumper etc.
The
symbol indicates an operation that must be done in software e.g. a command that
must be entered, a window that must be opened etc.
Introduction:
An arithmetic circuit is a circuit that performs a variety of arithmetic operations. It is a part of
the ALU. An arithmetic circuit can be implemented using a number of gates, or using circuits
like multiplexers and full adders as building blocks. This experiment shows how a ripple
carry adders and carry look-ahead adders work.
The circuit diagram of the full adder is shown in Figure 1.
Figure 1.
Launch the Xilinx ISE environment and create a new project, “lab3”.
Select the Spartan-6 Device family from the drop-down menu
Select the XC6LX16 device from the drop-down menu
Select the CSG324 package from the drop-down menu
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Computer Architecture Lab - ACOE201
Select schematic as the design entry method. Select “ISim” in the
simulator selection
Create a schematic source file named “full_adder”. Insert the schematic of Figure 1.
Select “Tools => Check Schematic” and then “Tools => Symbol Wizard” and “Using
Schematic” and “full_adder”. Click “Next” until “Finish”. The full-adder should be
available as a component in the symbol view in the schematic editor.
Create a new schematic source “lab3a” and add it to the project. Create a 4-bit ripple
carry adder by appropriately connecting 4 full adders. Insert your schematic in Figure
2
A3 B3
A 2 B2
A1 B 1
A 0 B0
0
A
B Cin
A
B Cin
A
B Cin
A
B Cin
1-Bit F.A.
1-Bit F.A.
1-Bit F.A.
1-Bit F.A.
Cout
Cout
Cout
Cout
Sum
Sum
Sum
Sum
Cout
S3
S2
S1
S0
Insert schematic here...
Figure 2: Circuit Diagram of 4-bit Ripple-Carry Adder
Select "Project => New Source". From the list of sources select "Verilog Test
Fixture", name the new source file "Lab3a_tb" and make sure "add to
project" is selected. Associate it with "Lab3a" NOT the full_adder. Go to the
“simulation” tab. Select the "Lab3a_tb" source file. Double click to open it.
Create appropriate inputs to test the adder of Figure 2 as follows:
initial begin
#10 A3=0; A2=0; A1=1; A0=0; B3=0; B2=0; B1=1; B0=0; cin=0;
...
end
endmodule
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Computer Architecture Lab - ACOE201
Go down to the Processes tab, expand Isim simulator and double click on
“Simulate behavioural model.
Insert simulation screenshot here...
Download the UCF file specifying the input and output pin connections from:
http://staff.fit.ac.cy/com.tk/ACOE201/Lab3.ucf
Add it to the project as a source file.
Synthesize and implement your design. Generate the programming file
Connect the FPGA to your PC through the USB cable provided and turn on
the power switch.
Configure the Spartan-3E board by clicking on Start => Programs => Digilent =>
Adept => Adept. Adept should identify the Nexys3 board. Browse to the project
folder and select the .bit file. Click on "Program". Wait until the message that
programming is successful.
Download and test the adder on the FPGA board and change the state of the
switches to fill up table 2. Use the inputs from simulation.
Table 2: Truth table of the 1-bit Arithmetic Unit.
A3
A2
A1
A0
B3
B2
3
B1
B0
Cin
Cout S3 S2 S1 S0
Computer Architecture Lab - ACOE201
Create a new project called “Lab3b”. Create a new schematic. Enter the schematic
of a 4-bit Carry Look-Ahead Adder.
Part 2.
A3 B3
A2 B2
3ns
3ns
3ns
3ns
2ns
S3
A1 B 1
3ns
3ns
2ns
S2
A0 B0
3ns
3ns
2ns
S1
2ns
2ns
2ns
S0
2ns
2ns
2ns
Cin
2ns
2ns
2ns
2ns
2ns
Cout
2ns
2ns
2ns
2ns
Insert schematic here...
Figure 3. Carry Look-Ahead Adder Schematic
Select "Project => New Source". From the list of sources select "Verilog Test
Fixture", name the new source file "Lab3b_tb" and make sure "add to
project" is selected. Associate it with "Lab3b" NOT the full_adder. Go to the
“simulation” tab. Select the "Lab3b_tb" source file. Double click to open it.
Use the same inputs as in Lab2b_tb.
initial begin
#10 A3=0; A2=0; A1=1; A0=0; B3=0; B2=0; B1=1; B0=0; cin=0;
...
end
endmodule
Go down to the Processes tab, expand Isim simulator and double click on
“Simulate behavioural model.
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Computer Architecture Lab - ACOE201
Insert simulation screenshot here...
Click on Project=> Add source and select Lab3.ucf from the previous project
(Lab3a).
http://staff.fit.ac.cy/com.tk/ACOE201/Lab3.ucf
Synthesize and implement your design. Generate the programming file
Connect the FPGA to your PC through the USB cable provided and turn on
the power switch.
Configure the Spartan-3E board by clicking on Start => Programs => Digilent =>
Adept => Adept. Adept should identify the Nexys3 board. Browse to the project
folder and select the .bit file. Click on "Program". Wait until the message that
programming is successful.
Download and test the Carry Look-Ahead Adder on the FPGA board and change
the state of the switches to fill up Table 3. Use the inputs from simulation.
Table 3: Truth table of the 1-bit Arithmetic Unit.
A3
A2
A1
A0
B3
B2
Questions:
1.
Discuss the results in table 2.
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B1
B0
Cin
Cout S3 S2 S1 S0
Computer Architecture Lab - ACOE201
2.
Discuss the results in table 3.
3.
How many slices were used for the circuit of Lab3a. How many for that of Lab3b?
Which adder is smaller?
4.
Open the "Post PAR static timing analysis report" and find the slowest path of
project Lab3a and Lab3b. What are their delays. Which adder is faster?
6