Session F4F
Design of Combinational Logic Training System
Using FPGA
Sujittra Sothong and Pornpimon Chayratsami
King Mongkut Institute of Technology Ladkrabang, mided_54@hotmail.com, kcpornpi@gmail.com
Abstract - This paper describes a design of a training
system for a combinational logic design course. The
goals of this design are to reduce a cost of the system and
to lower the lost and damage of TTL elements used in a
digital laboratory currently. The system uses a Field
Programmable Gate Array (FPGA) as a processor
containing basic logic gates, and uses a microcontroller
as a gate selector. The training system consists of a
system unit base, 17 basic logic gate models, and 10 lab
sheets. The system is evaluated in terms of quality and
using suitability of the system by experts and instructors
who work with technical schools in Thailand and have
been involving and teaching a combinational logic design
course for at least 5 years. The results show that the
system is rated to have a very good quality and is
suitable for being used as a training system in a
combinational logic course with inexpensive cost.
Output
Displays
On/off
Switch
IC model
slot #2
Signal input
switches
(A) TRAINING UNIT BASE
IC
models
Index Terms – Combinational Logic design, FPGA,
laboratory, training system
INTRODUCTION
Combinational logic circuit is introduced to students in the
digital circuit and logic design class, which is one of the
fundamental courses in electrical engineering majors [1].
The course is included in the vocational education level in
Thailand, which emphasizes students to have a practical
skill. Therefore, laboratory experiment is important for
students to increase theory understanding and hands-on
skill. To help instructors to manage the class efficiently, a
laboratory training system is an important tool.
Currently, there are two types of commercially
available training systems, which are hard wired “kits” and
simulator [2]. The kit generally consists of experiment
modules (including breadboard module), power supply,
signal generator, switches and display [3, 4]. The simulator
can be either PC based using a programmable logic device
(software and hardware) or virtual process (software only)
[5].
The technical school instructors, who have experiences
in using the TTL elements with breadboard module, notice
that the cost of constructing a combinational logic circuit is
primarily from the loss and damage of the TTL elements
using in the lab. While the instructors, who use other
experiment modules (no breadboard) or simulators, notice
that students do not obtain enough practical skills to build a
combinational logic circuit.
Accessories
(B) THE IC MODELS AND ACCESSORIES
FIGURE 1 TRAINING SYSTEM COMPONENTS
To solve the problem of the losing/damaging TTL
elements and to maintain practical skill of building a
combinational logic circuit, a design of the training system
for a combinational logic design course is proposed. The
design is based on an FPGA and a microcontroller. A plastic
acrylic IC model is used to replace the conventional TTL IC
elements. Detail of the design is shown later in the next
section. Then, the results of evaluation by experts in terms
of quality and using suitability of the system are reported.
Finally, the conclusion is made.
TRAINING SYSTEM DESIGN
The designed training system consists of a training unit
base, 17 basic logic gate IC models, 10 lab sheets, and
accessories. The unit base contains a set of output display, 4
IC model slots, and 16 signal input switches with displays
978-1-4244-6262-9/10/$26.00 ©2010 IEEE
October 27 - 30, 2010, Washington, DC
40th ASEE/IEEE Frontiers in Education Conference
F4F-1
Session F4F
FIGURE 2 THE TOP AND THE BOTTOM OF A 7408 IC MODEL
as shown in Figure 1(A). The output display includes 32
LEDs and two 7-segments. The IC model slots are the input
terminals for IC models and the input switches are used to
select a signal logic 0/1 (low/high) to the inputs of the logic
gate models. The basic logic gate models are made from
acrylic plastic. Each model has a label of a connection
diagram on top to ease users to build a circuit as shown in
Figure 1(B) and Figure 2. The bottom of each model is a
printed circuit board (PCB) that encodes the model to an
exclusive TTL character.
TRAINING UNIT BASE DESIGN
The design of the unit base consists of five parts: signal
input switch, IC model input, microcontroller, FPGA, and
display. Figure 3 is a block diagram of the training unit base
design.
selects the matched IC character that stored in the FPGA.
After setting and wiring all connections for an experiment,
the FPGA processes all input signals (0/1) from input
switches and provides output to be displayed on LEDs or 7segments.
The FPGA used in this training system is Altera
ACEX1K series, which can store 17 basic IC characters. It
contains 10,000 logic gates, 576 logic elements, 12,288 total
RAM bits, and 102 user I/O pins. Since FPGA is a SRAM –
base devices [6], the configuration data is stored in volatile
SRAM cells during device operation. Then that information
must be reloaded each time the device powers up [7].
Therefore, this training system requires a device, which is a
non-volatile source to keep configuration data to be loaded
in FPGA. The device used to store the configuration in the
design is the microcontroller, MCU AVR ATMEGA128,
which contains a 128 Kbyte FLASH memory.
IC MODEL DESIGN
In this training system design, there are 17 IC models (but
16 IC characters) used to complete all laboratories. Each
model has a binary code to identify itself as a TTL IC.
Therefore, the five-bit codes from 00000-11111 are used.
For examples, the 7408 TTL model is encoded to a binary
number “00100” and is converted to the PCB as shown in
Figure 2.
LABORATORY MANUAL
Another component included in the combinational logic
training system is a laboratory manual, which contains 10
lab sheets. The lab manual includes topics from an
introduction to applications of the combinational logic. The
topics of all lab sheets are as following:
•
•
•
•
•
•
•
•
•
•
Introduction to Logic Gates
NAND and NOR Gates Applications
Boolean Algebra and Combinational Logic Circuit
Combinational Logic and Circuit Design
Multiplexer and Demultiplexer
Encoder Circuit
Decoder Circuit
Binary Adder Circuit
Binary Subtraction Circuit
Comparator Circuit
RESULT
FIGURE 3 BLOCK DIAGRAM OF THE TRAINING UNIT BASE DESIGN
The signal input switch is an on/off switch that gives a
logic status of high/low (0/1) to a virtual logic gate stored in
the FPGA. The type of logic gate is selected by the IC
model that has a unique code to identify itself as a basic
TTL element. When a user plugs an IC model into the IC
input slot, the microcontroller decodes the IC code and
The designed training system is evaluated in terms of
quality and using suitability of the system. The evaluation of
the system quality is separated into two parts. First, the
system is tested all functions specified in the laboratory
manual. Then, it is sent to the experts and instructors, who
have been involving and teaching a combinational logic
design course for at least 5 years, to do the evaluation in
both aspects of the training system.
978-1-4244-6262-9/10/$26.00 ©2010 IEEE
October 27 - 30, 2010, Washington, DC
40th ASEE/IEEE Frontiers in Education Conference
F4F-2
Session F4F
D, Bo
Bi, A, B
(A) CONNECTING CIRCUIT
(A) RESULTS OF THE FULL SUBTRACTION CIRCUIT WHEN
(Bi, A, B) is (0, 0, 1)
D, Bo
(B) INPUT SWITCHES
(C) OUTPUT DISPLAY
FIGURE 4 AN EXPERIMENT VERIFYING A PROPERTY OF AN AND GATE
The first part of the quality evaluation is done by the
researchers to ensure that the designed training system will
cover all topics in the laboratory manual and work properly.
The results show that the designed training system is able to
work well in all laboratories stated in the manual. Examples
of the evaluation are shown in figure 4 and 5.
Figure 4 shows an experiment verifying a property of
an AND gate, which is a part of the first laboratory (An
Introduction to Logic Gates). The IC 7408 model is plugged
into the IC model slot #4, then two inputs of the AND gate
are connected to input switches and the output of the gate is
connected to an LED output display shown in Figure 4(A).
Figure 4(B) shows that when both switches of the inputs are
turned on (logic 1), the output of the gate results in logic 1
shown in figure 4(C). Notice that the LED is lit on and off
to represent logic 1 and logic 0, respectively.
Figure 5 shows an experiment of a binary subtraction
circuit, which uses four IC ports with four kinds of IC
models. This experiment is more complex than the one in
Figure 4. The IC 7408, 7404, 7486, and 7432 models are
plugged into IC slot #1, #2, #3, and #4 respectively. The
circuit is corresponding to the binary full subtraction
equation of
D = Bi ⊕ A ⊕ B
Bo = AB + Bi ( A ⊕ B )
Bi, A, B
(B) RESULTS OF THE FULL SUBTRACTION CIRCUIT WHEN
(Bi, A, B) is (1, 0, 1)
FIGURE 5 AN EXPERIMENT VERIFYING A FULL SUBTRACTION CIRCUIT
Where A is the minuend
B is the subtrahend.
Bi is the Borrow-in.
Bo is the Borrow-out.
D is the difference.
The truth table to the binary full subtraction is shown in
Table 1.
TABLE 1 TRUTH TABLE OF THE BINARY FULL SUBTRACTION
Input
Output
Bi
A
B
D
Bo
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
1
1
978-1-4244-6262-9/10/$26.00 ©2010 IEEE
October 27 - 30, 2010, Washington, DC
40th ASEE/IEEE Frontiers in Education Conference
F4F-3
Session F4F
The results of using the training system in an
experiment of a full subtraction circuit show that the I/O
LEDs are lit up corresponding to the logics in the truth
table. For example, both of the output LEDs are lit up when
the input (Bi, A, B) is (0, 0, 1) and the LED displayed the
output Bo is lit up when the input (Bi, A, B) is (1, 0, 1) as
shown in Figure 5(A) and 5(B) respectively. All of the
laboratories are performed on the designed training system
and they result in an appropriate performance.
After ensuring that the training system works properly
as specified in all laboratories, the system and the laboratory
manual are evaluated by 15 of experts and instructors, who
have been involving and teaching a combinational logic
design course for at least 5 years, via rating scale
questionnaires. The rating scale using in the questionnaire is
ranged from 1 (need improvement) to 5 (excellent) in each
item. Scores of each question from 15 evaluators are
averaged and interpreted. The evaluating criterion is as
following:
4.50-5.00 means “excellent.”
3.50-4.49 means “good.”
2.50-3.49 means “average.”
1.50-2.49 means “usable.”
1.00-1.49 means “need improvement.”
The questions are about the quality and suitability to
use of the system. The quality of the training system is
evaluated in terms of size, shape, safety, and convenience to
use of the system. The quality of the laboratory manual is
also evaluated in terms of format and description. After 14
days of investigation from each evaluator, the results show
that the system is rated to have an excellent quality in
average and is suitable for being used as a training system in
a combinational logic course, with an average opinion of the
experts and instructors in total of 4.54. In addition, the
evaluators have the same opinions on saving money and
times of doing an experiment by using the designed training
system. The system would help saving money that they have
to pay for the loss and damage TTL elements and also
would reduce experimental time by working without
opening a TTL datasheet.
system could be a prototype for further more digital training
system.
ACKNOWLEDGEMENTS
The initial idea of the training system design was developed
by Associate Professor Dr. Surasit Ratree from the
department of Engineering Education, King Mongkut
Institute of Technology Ladkrabang, Thailand, who passed
away in 2009.
REFERENCES
[1]
Mealy, B.J.; Parks, B., “Work in Progress-PLD-based introductory
digital design in a studio setting,” Frontiers in education conferenceglobal engineering: knowledge without borders, opportunities without
passports, 2007, page F1C-1 – F1C-2, 2007.
[2]
Michael Barrett, “The Design of a Portable Programmable Logic
Controller (PLC) Training System for Use outside of the Automation
Laboratory,” International Symposium for Engineering Education,
2008, Ireland.
[3]
http://www.kora_en.siteset.hu/fajl.php?id=7190 (Access February
2010)
[4]
http://www.troper.com/uploads/images/1715/DigitalLogicLabTrainer
DLLT-1300.pdf (Access February 2010)
[5]
http://riajati.com/pdf/lp2900.pdf (Access February 2010)
[6]
Zhong Wei-Sheng; Wang Yu-Ti; Zeng Xiao-Shu , "FPGA-based
implementation of hardware technology on Generic Algorithms,"
Control and Decision Conference, 2008. CCDC 2008. Chinese, vol.,
no., pp.1333-1335, 2-4 July 2008.
[7]
Guillermo A. Jaquenod and Marisa R. De Giusti, “Low cost
configuration of SRAM based Altera devices,” the 8th International
Workshop Iberchip (IWS2002), available:
http://www.iberchip.org/VIII/docs/sesj4-1_1/jaquenod01.pdf
CONCLUSION
This paper proposes a new application of FPGA in
education point of view. It describes a design of a training
system for a combinational logic design course that applies
FPGA to produce virtual basic logic gates. The training
system contains a system unit base, 17 basic logic gate
models, and 10 lab sheets. The system is tested and
evaluated by experts and instructors who have been
involving and teaching a combinational logic design course
for at least 5 years. The results show that the system is rated
to have an excellent quality and is suitable for being a
training system in a combinational logic course with
inexpensive cost. However, the system could be improved
to support a sequential logic design course if new elements
are added into FPGA processor. Therefore, this training
978-1-4244-6262-9/10/$26.00 ©2010 IEEE
October 27 - 30, 2010, Washington, DC
40th ASEE/IEEE Frontiers in Education Conference
F4F-4