CAD Algorithms
Physical Design Automation
of VLSI Systems
Mohammad Tehranipoor
ECE Department
7 October 2008
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Physical Design Automation
Objectives:
Obtain general understanding about IC design process
Study design automation
Study algorithms
Used in designing the layout of a chip
Prepare students for exposure to hard CAD problems
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VLSI Design Cycle
Large number of components:
Optimize requirements for higher performance
The physical design is not practical without the help of computers.
Performance relates to speed, power and size.
Time to market competition:
Cost:
Makes the use of computer necessary
Using computer makes it cheaper by reducing time-to-market.
Manual
System
Specifications
Chip
Automation
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VSLI Design Cycle (Cont.)
VLSI design cycle can be divided into the following steps:
System Specification:
Goals and constraints of the system
Functionality (what will a system do)
Performance figures like speed and power
Technology constraints like size and space (physical dimensions)
Fabrication technology and design techniques
Architectural/Functional Design:
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RISC, CISC, # of ALUs, floating point units, number and structure of
pipelines, etc.
Functional behavior and functional units to match specification
Functional subunits and relationship among them
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VSLI Design Cycle (Cont.)
Logic Design:
Implementation of functional subunits using logic representation
Use of standard building blocks like RAM, ROM, PLA, etc.
Logic design should match functional description.
Register Transfer Level (RTL) description of subunits.
Boolean expressions, finite state machines or schematics.
RTL is expressed in VHDL or Verilog.
Circuit Design
Logic networks or descriptions are converted into electronic circuits.
Circuit elements are designed to meet specifications.
Transistors are sized for current capacity and delay requirements.
Circuit simulation is used to verify the correctness and timing of each
component.
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VSLI Design Cycle (Cont.)
Physical Design: That’s the focus of our course.
The circuit representation is converted into a geometric representation.
Geometric representation of a circuit is called layout.
The exact details of the layout depends on design rules.
Design rules are guidelines based on the limitations of the fabrication
process.
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VSLI Design Cycle (Cont.)
CAD Tools:
Layout synthesis tools are fast but do have area and performance penalties.
Manual layout is very slow but does have better area and performance.
Most of the layout of a high performance custom design may be done
using manual design.
Synopsys, Cadence, Mentor Graphics, Magma, and more
Note that the objective of VLSI CAD tools are to minimize
the time for each iteration and the total number of iterations,
thus reducing time-to-market.
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VSLI Design Cycle (Cont.)
Fabrication:
After layout and verification, the design is ready for
fabrication (called tapeout).
Layout data is converted into photo-lithographic
masks.
Testing and Debugging:
After fabrication, each die is tested.
The wafer is diced into individual chips.
Each chip is packaged and tested.
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VLSI Design Cycle
System
Specifications
Functional
Design
X=(AB*CD)+ …
Logic Design
Circuit Design
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VLSI Design Cycle
Physical Design
Fabrication
Packaging
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New Trends in VLSI Design Cycles
Increasing Interconnect Delay:
Interconnect is not scaling at the same rate as the devices.
Almost 60% of path delay may be due to interconnect.
Increasing Interconnect Area:
Almost 30-40% of the area is covered by interconnects in modern designs.
Relative Delay
Interconnect vs. Gate Delay
Technology Node (nm)
ITRS2005
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New Trends in VLSI Design Cycles
Increasing number of Metal Layers:
To meet the increasing need of interconnect, number of metals is increasing.
Up to 12 metal layer in the next few years
In nanometer technology
designs:
Many Metal Layers
More silicon area
consumed by wires –
Miles of Cu wires
Increasing wire lengths
and interconnect
defects, i.e. more
bridging faults
Increasing number of
vias – Metal layers
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New Trends in VLSI Design Cycles
Increasing Planning Requirements:
Physical design considerations have to enter into design at much earlier
phase.
Synthesis:
The design time can be reduced if layout can be directly generated from a
higher level description.
Behavioral Model Physical Layout
New tools can support it.
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Physical Design Process
Physical Design converts circuit description into a geometric
description.
This description is used to manufacture a chip.
The input to a physical design cycle is a circuit diagram/netlist
and the output is the layout of the circuit.
Required Stages:
Partitioning
Floorplanning
Placement
Routing
Compaction
Extraction and Verification (post-layout verification)
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New Trends in Physical Design Process
Chip Level Signal Planning
Routing of major signals and buses must be planned from early design
stages, so that the interconnect distances can be minimized.
Interconnects length directly impact circuit delay and layout area
OTC Routing
Over-the-cell (OTC) routing allows routing over blocks and active
areas.
Reduces the layout area
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Major Challenges
Crosstalk
Cc
Cs
Cc
0.35 µm
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Cs
90 nm
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Cont.
Power Supply Noise and Temperature
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Cont.
Power Supply Noise
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Cont.
Temperature
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Steps of Iterative Design Process
Synthesis:
Analysis:
Synthesis derives or improves a representation at any step.
Behavioral synthesis, logic synthesis and layout synthesis are all
examples at various steps.
Analysis ensures that the design representation matches the requirements
at various steps.
Requirements like area, power dissipation and speed.
Verification:
Establishes the correctness of design at any given step.
Simulation at any step should match specifications.
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Design Process is Iterative
Behavioral
Simulation-Based Verification
Structural
Simulation-Based Verification
Synthesis
Simulation-Based Verification
PNR
Simulation/Emulation-Based
Verification
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Design Styles
JC
Preferred style for mass production, Highly
optimized layout, Time can be justified
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Selection of Design Style
Selection of design styles depends on many factors:
Type of chip
Volume
Mass production, Medium production volume, …
Cost
High performance, Area, …
Company’s budget, Cost of the chip
Time-to-market
Last two are dominant.
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Full Custom Design Style
Circuit partitioned into sub-blocks.
Blocks can be of any size/shape
Hierarchical design
Placement on any location is allowed
Allows very compact designs
Difficult automation
High performance
The process of automating a fullcustom design style has a much higher
complexity than other restricted styles.
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Standard Cell Design Style
Design process is somewhat
simpler than full-custom design
style
Rectangular cells of same height
Library based design
Cells arranged in rows
Easier automation
Inherently nonhierarchical
Lower performance
Well suited for moderate size
designs and medium production
volume.
Logic synthesis uses standard cell
design style.
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Standard Cell
Channel is the space between two rows.
Feedthrough is the empty cells in a row.
Feedthroughs are assigned for the interconnections of non-adjacent
cells.
Standard cell design style takes more area than full custom.
Along with semiconductor manufacturing advances, standard cell
methodology was responsible for allowing designers to scale ASICs
from comparatively simple single-function ICs (of several thousand
gates), to complex multi-million gate devices (SoC).
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Standard Cell
2-input NAND or NOR function is sufficient to form any arbitrary
Boolean function set
In modern ASIC design, standard cell methodology is practiced with a
sizeable library of cells
The library contains multiple implementations of the same logic function,
differing in area and speed
This variety enhances the efficiency of automated synthesis, place and
route tools
It gives the designer greater freedom to perform implementation tradeoffs
Area vs Speed vs Power Consumption
A complete group of standard cell descriptions is commonly called a
technology library.
The technology library is developed and distributed by the foundry
operator.
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Gate Array Design Style
A simplification of Standard Cell Design Style
Gate array design is a manufacturing method in which the diffused layers, i.e.
transistors and other active devices, are predefined and wafers containing such
devices are held in stock prior to metallization, in other words, unconnected
A regular lattice shaped structure
Pre-fabricated logic
Both vertical and Horizontal channels
Only wiring masks need to be defined
Rapid fabrication
Low performance
Easy automation
Non-hierarchical structure
Logic synthesis can use gate array.
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Gate Array
Photo-lithographic masks are required only for the metal layers
Production cycles are much shorter as metallization is a comparatively
quick process
Advantages/Disadvantages:
The steps involved for creating any prefabricated wafer are the same
Only the last few steps in the fabrication process will be used.
Cheaper and easier to produce than full-custom and standard cell.
It offers more area and less time.
Difficulties in routing the interconnect require migration onto a
larger array device with consequent increase in the price
Pure, logic-only gate array design is rarely implemented by circuit
designers today
FPGA is preferred.
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Gate Array
Today gate arrays are evolving into
Structured ASICs
Structured ASICs consist of a large IP
core like a CPU, DSP unit, peripherals,
standard interfaces, integrated memories
SRAM, and a block of reconfigurable
uncommited logic.
This shift is largely because ASIC
devices are capable of integrating large
blocks of system functionality and
"system on a chip" requires far more
than just logic blocks.
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FPGA Design Style
Extremely rapid prototyping
Re-programmable
Lowest performance
Easy automation
Cells and interconnects are prefabricated.
The user simply programs the
interconnects.
Contains programmable logic blocks
and interconnects
Logic blocks can be programmed to
perform the function of basic logic gates
such as AND, and XOR, or more
complex combinational functions such as
decoders or mathematical functions.
FPGAs contain FFs
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LUT Programming
Source: Fundamentals of Digital Logic , McGraw Hill 2000
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LUT Programming
3-input LUT
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LUT Programming Sequential
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Comparison of Design Styles
Production
Volume:
Mass
Production
Volume
Complexity:
High
Medium
Production
Volume
Medium
Production
Volume
Low
Production
Volume
Low
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Physical Design Automation
Physical design implies “physical realization” of
integrated circuit layout.
Input to physical design cycle is a circuit design
Circuit netlist (gate level representation)
RTL description of the circuit
Output from this stage is a layout of the circuit
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The task from input to output is accomplished in several design stages,
each addressing specific goals.
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Physical Design Cycle
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Physical Design Cycle
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Physical Design Cycle
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VLSI Design Automation
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