Xilinx® Virtex™-5 FXT PCI Express
Development Kit
User Guide
Table of Contents
1.0
Introduction ............................................................................................................................................................................... 5
1.1
Description............................................................................................................................................................................ 5
1.2
Board Features ..................................................................................................................................................................... 5
1.3
Test Files .............................................................................................................................................................................. 5
1.4
Reference Designs ............................................................................................................................................................... 6
1.5
Ordering Information ............................................................................................................................................................. 6
2.0
Functional Description .............................................................................................................................................................. 7
2.1
Xilinx Virtex-5 FXT FPGA ..................................................................................................................................................... 8
2.2
GTX Interface ....................................................................................................................................................................... 8
2.2.1 GTX Reference Clock Inputs.......................................................................................................................................... 11
2.2.2 PCI Express x8 Add-in Card .......................................................................................................................................... 11
2.2.3 SFP Connectors ............................................................................................................................................................. 14
2.2.4 GTX on EXP Connectors JX1 AND JX2......................................................................................................................... 17
2.2.5 10 Gb/s Media Connector .............................................................................................................................................. 17
2.3
Memory............................................................................................................................................................................... 19
2.3.1 DDR2 SDRAM Interface................................................................................................................................................. 19
2.3.2 DDR2 SODIMM Interface ............................................................................................................................................... 21
2.3.3 P30 Flash Interface ........................................................................................................................................................ 24
2.3.4 Platform Flash Interface ................................................................................................................................................. 25
2.4
Clock Sources .................................................................................................................................................................... 25
2.4.1 MAX3674 Programmable LVDS Clock Synthesizer ....................................................................................................... 28
2.4.1.1
MAX3674 Clock Generation ...................................................................................................................................... 29
2.4.1.2
MAX3674 Programming Mode ................................................................................................................................... 30
2.4.1.3
MAX3674 M, NA, NB, and P Settings ........................................................................................................................ 30
2.5
Communication................................................................................................................................................................... 31
2.5.1 10/100/1000 Ethernet PHY ............................................................................................................................................ 32
2.5.2 Universal Serial Bus (USB) ............................................................................................................................................ 34
2.5.3 RS232 ............................................................................................................................................................................ 36
2.6
User Switches..................................................................................................................................................................... 36
2.7
User LEDs .......................................................................................................................................................................... 37
2.8
Configuration ...................................................................................................................................................................... 37
2.8.1 Configuration Modes ...................................................................................................................................................... 37
2.8.2 JTAG Chain.................................................................................................................................................................... 38
2.8.3 Byte Peripheral Interface (BPI)....................................................................................................................................... 38
2.8.4 System ACE Module Connector..................................................................................................................................... 39
2.9
Power ................................................................................................................................................................................. 40
2.9.1 FPGA I/O Voltage (VCCO) ............................................................................................................................................. 42
2.9.2 FPGA Reference Voltage (Vref) ..................................................................................................................................... 42
2.9.3 GTX Voltage Regulators (AVCC, AVCCPLL, VTTRX, VTTTX, VTTRXC)...................................................................... 42
2.10
Thermal Management ........................................................................................................................................................ 44
2.10.1
Passive Heat Sink ...................................................................................................................................................... 44
2.10.2
Active Heat Sink Support ........................................................................................................................................... 44
2.11
Expansion Connectors ....................................................................................................................................................... 44
2.11.1
EXP Interface............................................................................................................................................................. 45
3.0
Test Designs ........................................................................................................................................................................... 49
3.1
Factory Test........................................................................................................................................................................ 49
3.2
Ethernet Test ...................................................................................................................................................................... 49
4.0
Revisions ................................................................................................................................................................................ 50
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Figures
Figure 1 - Virtex-5 FXT PCI Express Board Picture ................................................................................................................................... 6
Figure 2 - Virtex-5 FXT PCI Express Board Block Diagram ....................................................................................................................... 7
Figure 3 - GTX Ports on the Virtex-5 FXT PCI Express Board ................................................................................................................. 10
Figure 4 - GTX Clock Sources on the Virtex-5 FXT PCI Express Board .................................................................................................. 11
Figure 6 - PCI Express x8 Interface ......................................................................................................................................................... 13
Figure 7 - SFP Module Interfaces............................................................................................................................................................. 15
Figure 8 - Host Board Connector AMP 1367073-1 (photo taken from AMP Web Page) .......................................................................... 16
Figure 9 - 10 Gb/s Media Connector Interface ......................................................................................................................................... 18
Figure 10 - DDR2 SDRAM Interface ........................................................................................................................................................ 19
Figure 11 - Flash Interface ....................................................................................................................................................................... 24
Figure 12 - Clock Nets Connected to Global Clock Inputs........................................................................................................................ 26
Figure 13 – MAX3674 Clock Synthesizer ................................................................................................................................................. 28
Figure 14 – M, NA, NB, and P DIP Switches for the MAX3674 ................................................................................................................ 30
Figure 15 - 10/100/1000 Mb/s Ethernet Interface ..................................................................................................................................... 32
Figure 16 - RS232 Interface ..................................................................................................................................................................... 36
Figure 17 - JTAG Chain on the Virtex-5 PCI Express Board .................................................................................................................... 38
Figure 18 - SAM Interface (50-pin header) ............................................................................................................................................... 39
Figure 19 - Board Power Supply .............................................................................................................................................................. 41
Figure 20 - GTX Voltage Regulators ........................................................................................................................................................ 43
Figure 21 - Heat Sink Mounting-Hole Pattern ........................................................................................................................................... 44
Figure 22 - EXP I/O Voltage Settings ....................................................................................................................................................... 45
Figure 23 - Board Jumpers, Headers, Connectors ................................................................................................................................... 51
Figure 24 – VCCO_EXP1 "JP5" ............................................................................................................................................................... 51
Figure 25 – VCCO_EXP2 “JP6” ............................................................................................................................................................... 52
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Tables
Table 1 - Ordering Information ................................................................................................................................................................... 6
Table 2 - Differences between Virtex-5 devices ......................................................................................................................................... 8
Table 3 - Communications Standards Supported by the Virtex-5 GTX ...................................................................................................... 8
Table 4 - GTX Placement Names............................................................................................................................................................... 9
Table 5 – ICS874003-05 F_SEL Switch Settings ..................................................................................................................................... 12
Table 6 - GTX Pin Assignments for PCI Express ..................................................................................................................................... 14
Table 7 - GTX Pin Assignments for the SFP Interfaces ........................................................................................................................... 16
Table 8 - SFP Host Connector Pin Description ........................................................................................................................................ 16
Table 9 - FPGA I/O Assignments for the SFP Interfaces.......................................................................................................................... 17
Table 10 - GTX Pin Assignments for EXP Connectors ............................................................................................................................. 17
Table 11 - GTX Pin Assignments for 10 Gbps Media Connector ............................................................................................................. 18
Table 12 - DDR2 SDRAM Timing Parameters ......................................................................................................................................... 20
Table 13 - FPGA Pin Assignments for DDR2 SDRAM ............................................................................................................................. 21
Table 14 - DDR2 SODIMM Parameters ................................................................................................................................................... 22
Table 15 - FPGA Pin Assignments for DDR2 SODIMM ........................................................................................................................... 23
Table 16 - Flash Interface Pin Assignments ............................................................................................................................................. 24
Table 17 - On-Board Clock Sources ......................................................................................................................................................... 27
Table 18 - Clock Socket "U25" Pin-out ..................................................................................................................................................... 27
Table 19 - User Clock Inputs .................................................................................................................................................................... 28
Table 20 - MAX3674 Clock Synthesizer Pin Description .......................................................................................................................... 29
Table 21- Example of the MAX3674 M, NA, NB, and P Settings.............................................................................................................. 30
Table 22 - DIP Switch Setting for M[9:0]................................................................................................................................................... 31
Table 23 - DIP Switch Setting for NA[2:0] and NB.................................................................................................................................... 31
Table 24 - DIP Switch Setting for P and PLOAD_N ................................................................................................................................. 31
Table 25 - MAX3674 Pin Assignments ..................................................................................................................................................... 31
Table 26 - Ethernet PHY Hardware Strapping Options ............................................................................................................................ 33
Table 27 – Faceplate Ethernet PHY “U25” Pin Assignments ................................................................................................................... 34
Table 28 - Auxiliary Ethernet PHY "U12" Pin Assignments ...................................................................................................................... 34
Table 29 - USB Interface FPGA Pin-out ................................................................................................................................................... 35
Table 30 - RS232 Signals......................................................................................................................................................................... 36
Table 31 - Push Button Pin Assignments ................................................................................................................................................. 36
Table 32 - DIP Switch Pin Assignments ................................................................................................................................................... 37
Table 33 - LED Pin Assignments.............................................................................................................................................................. 37
Table 34 – Setting the Configuration Mode “JP3”..................................................................................................................................... 37
Table 35 - Flying Lead JTAG Header ....................................................................................................................................................... 38
Table 36 - SAM Interface Signals ............................................................................................................................................................. 40
Table 37 – I/O Bank Voltages................................................................................................................................................................... 42
Table 38 - Typical Current Measurements per MGT Tile.......................................................................................................................... 43
Table 39 - Recommended Active Heat Sinks ........................................................................................................................................... 44
Table 40 - EXP Connector Signals ........................................................................................................................................................... 45
Table 41 - EXP v1.3 Alternate Function Pins ........................................................................................................................................... 46
Table 42 - EXP Connector "JX1" Pin-out.................................................................................................................................................. 47
Table 43 - EXP Connector "JX2" Pin-out.................................................................................................................................................. 48
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1.0 Introduction
The purpose of this manual is to describe the functionality and contents of the Virtex-5 FXT PCI Express Development Kit from Avnet
Electronics Marketing. This document includes instructions for operating the board, descriptions of the hardware features and
explanations of the test code programmed in the on-board PROM. For reference design documentation, see the PDF file included with
the project files of the design.
1.1
Description
The Virtex-5 FXT PCI Express Development Kit provides a complete hardware environment for designers to accelerate their
time to market. The kit delivers a stable platform to develop and test designs targeted to the advanced Xilinx FPGA family. The
installed Virtex-5 FXT device offers a prototyping environment to effectively demonstrate the enhanced benefits of leading
edge Xilinx FPGA solutions. Reference designs are included with the kit to exercise standard peripherals on the evaluation
board for a quick start to device familiarization.
1.2
Board Features
FPGA
— Xilinx Virtex-5 XC5VFX70T-2FF1136 FPGA
OR
— Xilinx Virtex-5 XC5VFX100T-2FF1136 FPGA
I/O Connectors
— Two EXP general-purpose I/O expansion connectors
— One 50-pin 0.1” Header supports Avnet SystemACE Module (SAM)
RocketIO™ GTX Transceiver Connectors
— Two Small-Form Pluggable (SFP) cages
— Two transceivers supplied on an EXP connectors for use by an expansion module
— One CX4 connecter supports 4 lanes @ 3.125 Gbps
— One PCI Express add-in card interface (8 lanes @ 2.5 / 5.0 Gbps)
Memory
— 64 MB DDR2 SDRAM components
— 256 MB DDR2 SODIMM module
— 32 MB FLASH
Communication
— RS-232 serial port
— USB 2.0
— Two 10/100/1000 Ethernet ports
Power
— Regulated 3.3V, 2.5V, 1.8V and 1.0V supply voltages derived from the PCI Express slot or an external 5V supply
— SSTL2 Termination Regulators
— Point of Load Regulators for MGT supply rails
Configuration
— 16MB Platform Flash XL Configuration Flash
— Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration
— Fly-wire support for Xilinx Parallel Cable III
1.3
Test Files
The Flash on the Virtex-5 FXT PCI Express Board comes programmed with a factory test example design. Additional test
files that can be used to verify the functionality of the peripherals on the board can be found on the Avnet Electronics
Marketing Design Resource Center (DRC) web site: www.em.avnet.com/drc. The test designs listed below are discussed in
Section 3.0.
—
—
Factory Test
Ethernet Test
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1.4
Reference Designs
Reference designs that demonstrate some of the potential applications of the Virtex-5 FXT PCI Express development board
can be downloaded from the Avnet Design Resource Center (www.em.avnet.com/drc). The reference designs include all of
the source code and project files necessary to implement the designs. See the PDF document included with each reference
design for a complete description of the design and detailed instructions for running a demonstration on the development
board. Check the DRC periodically for updates and new designs.
Figure 1 - Virtex-5 FXT PCI Express Board Picture
1.5
Ordering Information
The following table lists the evaluation kit part numbers and available software options.
Internet link at http://www.em.avnet.com/drc
Part Number
Hardware
AES-V5FXT-PCIE70-G
Xilinx Virtex-5 FXT PCI Express Kit populated with an
XC5VFX70T-2 speed grade device
AES-V5FXT-PCIE100-G
Xilinx Virtex-5 FXT PCI Express Kit populated with an
XC5VFX100T-2 speed grade device
Table 1 - Ordering Information
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2.0 Functional Description
A high-level block diagram of the Virtex-5 FXT PCI Express board is shown below followed by a brief description of each sub-section.
PCI-Express x8
(2 I/O, 8 GTXs)
Connector
Connector
GTX Interfaces
EXP Slot
(160 I/O, 2 GTXs)
SFP Connectors
(2 GTXs, 14 I/O)
Configuration and Debug Ports
CX4 Connector
(4 GTXs)
SAM Connector
(30 I/O)
PC4/USB
JTAG Port
Communication Ports
Trace Port
(23 I/O)
10/100/1000 PHY
(29 I/O)
Debug Port
10/100/1000 PHY
(29 I/O)
Cypress USB 2.0
(24 I/O)
Memory Interfaces
128MB DDR2 SDRAM SODIMM
(x64, 130 I/O)
Virtex-5
FX70T/FX100T
FFG1136
64MB DDR2 SDRAM
(x32, 77 I/O)
RS232 Port
(4 I/O)
SM/BPI
16MB Platform Flash XL
(Configuration/User Data Flash)
32MB Flash, User Data/Code Storage
(x16, 50 I/O)
Clock Sources
Miscellaneous I/O
Programmable
LVDS Clock Source
Push Switches
(4 I/O)
LVDS Clock Input
(SMA Connectors)
DIP Switches
(8 I/O)
User LEDs
(8 I/O)
Voltage Regulators
3.3V
Regulator
2.5V
Regulator
1.8V
Regulator
LVTTL OSC
@ 100 MHz
1.0V
Regulator
LVTTL OSC Socket
0.9V
Regulator
Figure 2 - Virtex-5 FXT PCI Express Board Block Diagram
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2.1
Xilinx Virtex-5 FXT FPGA
The Virtex-5 FXT FPGA devices available in the FF1136 package have four embedded Ethernet MAC Blocks, three embedded
PCI Express Endpoint Blocks and six Clock Management Tiles (each tile contains two DCMs and one PLL). The following
table shows the differences between these devices.
Device
XC5VFX70T
XC5VFX100T
Number of
Slices
11,200
16,000
BlockRAM
(Kb)
5,328
8,208
DSP48E
Slices
128
256
GTX
Transceivers
16
16
I/O Pins
640
680
Table 2 - Differences between Virtex-5 devices
A common Printed Circuit Board (PCB) is used for both of the FPGA devices.
The Virtex-5 FXT PCI Express development board uses production silicon devices. The pin-out used for the PCI Express
interface supports the Xilinx recommended pin-out for production silicon.
2.2
GTX Interface
The RocketIO™ GTX Transceiver is a full-duplex serial transceiver for point-to-point transmission applications. Up to 16
transceivers are available on a single Virtex-5 FXT FPGA. The transceiver block is designed to operate at any serial bit rate in
the range of 150 Mb/s to 6.5 Gb/s per channel, including the specific bit rates used by the communications standards listed in
the following table. Multiple channels can be bonded together for increased data throughput. The data width of the FPGA fabric
interface is programmable (one or two bytes) allowing the parallel data frequency to be tailored to the user application.
Standards
PCI Express
SFI-5
OC-12
OC-48
Channels (# of
transceivers)
1, 2, 4, 8
1
1
1
Fibre Channel
1
Gigabit Ethernet
XAUI (10-Gbit Ethernet)
10-Gbit Fibre Channel
Infiniband
1
4
4
1, 4
HD-SDI
1
Serial ATA
1
Serial Rapid I/O
Aurora (Xilinx protocol)
1, 4
1, 2, 3, 4, …
I/O Bit Rate (Gb/s)
2.5
2.488 – 3.125
0.622
2.488
1.06
2.12
1.25
3.125
3.1875
2.5
1.485
1.4835
1.5
3.0
1.25
2.5
3.125
0.100 – 3.75
Table 3 - Communications Standards Supported by the Virtex-5 GTX
The Virtex-5 FXT transceivers are grouped into tiles with two transceivers per tile. The two transceivers in each tile share a
single PLL and other resources involving the reset and power control. A trailing number ‘0’ or ‘1’ is used to distinguish between
the two transceivers in the tile. These transceiver tiles are physically located into a single column on the die. Each tile has a
placement name associated to its X-Y coordinate on the die. For example, GTX_Dual_X0Y0 is the first tile in the column. The
GTX_Dual placement name is used in the User Constraint File (UCF) to map specific tiles on the device to those instantiated
in a HDL design.
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GTX Interface
Lanes
10Gb/s Media
Connector
SFP
EXP1
EXP2
0,1
2,3
0,1
0,1
2,3
4,5
6,7
PCI Express
Number
FX70T/FX100T
GTX_Dual_X0Y4
MGT112
GTX_Dual_X0Y5
MGT116
GTX_Dual_X0Y6
MGT120
GTX_Dual_X0Y7
MGT124
GTX_Dual_X0Y3
GTX_Dual_X0Y2
GTX_Dual_X0Y1
GTX_Dual_X0Y0
MGT114
MGT118
MGT122
MGT126
Table 4 - GTX Placement Names
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The following figure shows the 16 RocketIO transceiver ports used on the Virtex-5 FXT PCI Express board. The GTX tiles are
depicted in their actual locations (rough, not exact).
Figure 3 - GTX Ports on the Virtex-5 FXT PCI Express Board
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ICS874003-05
Jitter Attenuator
2.2.1
GTX Reference Clock Inputs
Each GTX_Dual tile has a reference clock input that can also be used by any adjacent dual tile. Several of these reference
clock inputs are supplied by on-board clock sources while others are supplied externally. Two programmable LVDS
synthesizers are used to provide variable clock sources to the dedicated GTX clock inputs. These synthesizers provide
reference clock frequencies that support the full range of line rates. A dedicated pair of differential SMA connectors is
connected to one of the GTX clock inputs. The SMA connector inputs are for user clocks generated by external test equipment
or by the Virtex-5 itself on one of the SMA output connectors (requires SMA cables to make the connection). PCI Express
applications use the 100 MHz reference clock provided over the card edge. PCI Express Gen2 applications will use a 250 MHz
reference clock provided by the jitter attenuator. The following figure shows the clock sources provided to the dedicated GTX
clock inputs.
Figure 4 - GTX Clock Sources on the Virtex-5 FXT PCI Express Board
Two sets of differential SMA connectors are connected to regular I/O pins on the Virtex-5 FPGA. These SMA connectors can
be used to forward a reference clock out to a scope to provide a trigger input during GTX testing.
2.2.2
PCI Express x8 Add-in Card
Eight of the GTX transceivers are connected to the PCI Express card edge interface. PCI Express is an enhancement to the
PCI architecture where the parallel bus has been replaced with a scalable, fully serial interface. The differences in the electrical
interface are transparent to the software so existing PCI software implementations are compatible. Use of the Virtex-5 FXT PCI
Express board in a PCI Express application requires the implementation of the PCI Express protocol in the FPGA. The PCI
Express Endpoint Block embedded in the Virtex-5 FPGA implements the PCI Express protocol and the physical layer interface
to the GTX ports. This block must be instantiated in the user design. For more information, see the “Virtex-5 Endpoint Block for
PCI Express Designs User Guide” on the Xilinx web site.
http://www.xilinx.com/support/documentation/user_guides/ug197.pdf
The PCI Express electrical interface on the Virtex-5 FXT PCI Express board consists of 8 lanes, each lane having a
unidirectional transmit and receive differential pair. Each lane supports both first generation data rate of 2.5 Gbps and second
generation data rate of 5.0 Gbps. In addition to the 8 serial lanes there is a 100 MHz reference clock that is provided from the
system slot. In order to work in open systems, add-in cards must use the reference clock provided over the PCI Express card
edge to be frequency locked with the host system.
To accommodate both Gen 1 and Gen 2 PCI Express systems the Virtex-5 FXT PCI Express board utilizes the on board
ICS874003-05 jitter attenuator. See the figure below for an illustration of how the PCI Express reference clock is connected to
the Virtex-5 FXT FPGA.
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Figure 5 – PCI Express Reference Clock Conversion for Gen 2
The ICS874003-05 device will provide the 100 MHz reference clock OR the 250 MHz reference clock to the PCI Express
dedicated GTX_DUAL tiles with the proper F_SEL switch configuration. The F-SEL switch is SW16. Refer to the table below
for the proper switch configuration. This table assumes the QA0 and/or QA1 outputs are used for forwarding the reference
clock to the Virtex-5 FPGA. See the IDT data sheet for switch settings regarding the QB outputs
SW16.1
SW16.2
SW16.3
PCI Express Mode of Operation ( QA0/QA1 Fout)
ON
OFF
ON
PCI Express Generation 1 (100 MHz)
OFF
OFF
OFF
PCI Express Generation 2 (250 MHz)
Table 5 – ICS874003-05 F_SEL Switch Settings
There is also a side band signal from the PCI Express card edge that connects to a regular I/O pin on the Virtex-5 FPGA. The
“PERST#” signal is an active low reset signal provided by the host PCI Express slot. The following figure shows the PCI
Express interface to the Virtex-5 FPGA.
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PETp0
PETn0
PERp0
PERn0
MGT_DUAL
X0Y3
PETp1
PETn1
MGT114
PERp1
PERn1
PETp2
PETn2
PERp2
PERn2
MGT_DUAL
X0Y2
PETp03
PETn3
MGT118
PERp3
PERn3
Virtex-5
FX70T
FX100T
FPGA
PETp4
PETn4
PERp4
PERn4
MGT_DUAL
X0Y1
PCI EXPRESS
x8 EDGE
CONNECTOR
PETp05
PETn5
MGT122
PERp5
PERn5
PETp6
PETn6
PERp6
PERn6
MGT_DUAL
X0Y0
JP7
PETp07
PETn7
MGT126
1
x4
PERp7
PERn7
x8
PRSNT2#
SELECT
CREFCLKp
CREFCLKn
FPGA I/0
CPERST#
Figure 6 - PCI Express x8 Interface
The lane width of the PCI Express interface is determined by the PRSNT1# and PRSNT2# connections. There are separate
PRSNT2# pins for each of the lane options: one lane (x1), four lanes (x4) and eight lanes (X8). These pins are pulled-up on
the host motherboard. There is a single PRSNT1# pin that is pulled-low or tied to GND on the host motherboard. The add-in
card connects the PRSNT1# pin to the PRSNT2# pin for the widest lane option in most applications, which effectively pulls the
corresponding PRSNT2# pin low. This indicates to the host controller the lane width supported by the add-in card. The Virtex-5
FXT PCI Express board provides the ability for the user to select the lane width by connecting the desired PRSNT2# pin with a
jumper on JP7. See Appendix A for more information about the JP7 jumper settings.
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The PCI Express transmit lanes are AC coupled (DC blocking capacitors are included in the signal path) on the development
board as required by the PCI Express specification. The Virtex-5 FXT PCI Express board takes advantage of the polarity
inversion feature of the GTX transceivers. The “P” and “N” of all of the odd-numbered PCI Express lanes are swapped on the
board to improve the PCB routing. Each GTX has attributes that are used to enable polarity inversion on either the transmit or
receive pairs, or both. The polarity inversion attributes are “TXPOLARITY” for the transmit pairs and “RXPOLARITY” for the
receive pairs. Setting these attributes to a logic 1 enables the inversion.
GTX Instance
FX70T/FX100T:
GTX_Dual_X0Y3
FX70T/FX100T:
GTX_Dual_X0Y2
FX70T/FX100T:
GTX_Dual_X0Y1
FX70T/FX100T:
GTX_Dual_X0Y0
Net Name
PCIe_RX0P
PCIe_RX0N
PCIe_TX0P
PCIe_TX0N
Connector.pin#
P4.B14
P4.B15
P4.A16
P4.A17
Virtex-5 pin#
W1
Y1
V2
W2
PCIe_RX1P
PCIe_RX1N
PCIe_TX1P
PCIe_TX1N
P4.B19
P4.B20
P4.A21
P4.A22
AA1
AB1
AB2
AC2
PCIe_RX2P
PCIe_RX2N
PCIe_TX2P
PCIe_TX2N
P4.B23
P4.B24
P4.A25
P4.A26
AE1
AF1
AD2
AE2
PCIe_RX3P
PCIe_RX3N
PCIe_TX3P
PCIe_TX3N
P4.B27
P4.B28
P4.A29
P4.A30
AG1
AH1
AH2
AJ2
PCIe_RX4P
PCIe_RX4N
PCIe_TX4P
PCIe_TX4N
P4.B33
P4.B34
P4.A35
P4.A36
AL1
AM1
AK2
AL2
PCIe_RX5P
PCIe_RX5N
PCIe_TX5P
PCIe_TX5N
P4.B37
P4.B38
P4.A39
P4.A40
AP2
AP3
AN3
AN4
PCIe_RX6P
PCIe_RX6N
PCIe_TX6P
PCIe_TX6N
P4.B41
P4.B42
P4.A43
P4.A44
AP6
AP7
AN5
AN6
PCIe_RX7P
PCIe_RX7N
PCIe_TX7P
PCIe_TX7N
P4.B45
P4.B46
P4.A47
P4.A48
AP8
AP9
AN9
AN10
P/N Swapped?
No
No
Yes (RX)
Yes (TX)
No
No
Yes (RX)
Yes (TX)
No
No
Yes (RX)
Yes (TX)
No
No
Yes (RX)
Yes (TX)
Table 6 - GTX Pin Assignments for PCI Express
2.2.3
SFP Connectors
Two GTX transceivers are connected to Small Form-factor Pluggable (SFP) interfaces, which provide the ability to support
optical links with the addition of optical transceiver modules (not included in the kit). The following figure shows a high-level
block diagram of the SFP interfaces on the development board. This interface utilizes one GTX_Dual tile and a set of lowspeed control signals to interface to two SFP modules. One of the programmable LVDS synthesizers on the board is used to
provide the reference clock. The SFP interfaces on the Virtex-5 FXT PCI Express Board have been designed to support
transceivers with transmission rates up to 3.75 Gbps operating over multimode or single mode fiber.
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MGTTXP0
MGTTXN0
MGTRXP0
MGTRXN0
SFP_TD1_P
TD+
SFP_TD1_N
SFP_RD1_P
TDRD+
SFP_RD1_N
RD-
FPGA I/O
SFP_TR1_ LOS
SFP_TR1_ RATESELECT
SFP_TR1_ MODDEF2
SFP_TR1_ MODDEF1
SFP_TR1_ MODDEF0
SFP_TR1_ TXFAULT
SFP_TR1_ TXDISABLE
LOS
Rate Select
MOD- DEF(2)
MOD- DEF(1)
System Interface
1/2 GTX_Dual_X0Y6
SFP Module Connector
GbE
MOD- DEF(0)
Tx Fault
Tx Disable
P3 Enable
Virtex-5
FX70T/FX100T
FF1136
J20
MGTTXP 1
MGTTXN1
MGTRXP1
MGTRXN1
SFP_TD2_P
TD+
SFP_TD2_N
SFP_RD2_P
TDRD+
SFP_RD2_N
RD-
FPGA I/O
SFP_TR2_ LOS
SFP_TR2_ RATESELECT
SFP_TR2_ MODDEF2
SFP_TR2_ MODDEF1
SFP_TR2_ MODDEF0
SFP_TR2_ TXFAULT
SFP_TR2_ TXDISABLE
LOS
Rate Select
MOD- DEF(2)
System Interface
1/2 GTX_Dual_X0Y6
SFP Module Connector
GbE
MOD- DEF(1)
MOD- DEF(0)
Tx Fault
Tx Disable
P2 Enable
J18
Figure 7 - SFP Module Interfaces
The SFP connectors include a Host Board Connector, and top and bottom EMI cages. The Host Connectors are directly
connected or DC coupled to the GTX ports. SFP compliant modules include AC coupling capacitors in the modules for both the
transmit and receive signal paths so the AC coupling internal to the Virtex-5 FXT GTX receiver may be bypassed
(RXDCCOUPLE = TRUE). MGT120 transceivers 0 and 1 are connected to the two SFP host connectors labeled “P2” and “P3”
as indicated in the previous figure. The MGT120 tile is GTX_Dual “X0Y6” in the FX70T/FX100T devices.
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GTX Instance
FX70T/FX100T:
GTX_Dual_X0Y6
Net Name
SFP0_RXN
SFP0_RXP
SFP0_TXP
SFP0_TXN
Connector.pin#
P3.12
P3.13
P3.18
P3.19
Virtex-5 pin#
A2
A3
B4
B3
P/N Swapped?
No
SFP1_RXN
SFP1_RXP
SFP1_TXP
SFP1_TXN
P2.12
P2.13
P2.18
P2.19
C1
D1
E2
D2
No
No
No
Table 7 - GTX Pin Assignments for the SFP Interfaces
SFP modules connect to the board via the Host Board Connector defined in the SFP Multi-Source Agreement (MSA). This 20pin connector provides connections for power, ground, high-speed serial data, and the low-speed control signals for controlling
the operation of the SFP module. The following figure shows the host connector used on the Virtex-5 FXT PCI Express Board.
Figure 8 - Host Board Connector AMP 1367073-1 (photo taken from AMP Web Page)
The following table lists the Host Board Connector pin assignments and provides a brief description of each signal.
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
VEET
Tx Fault
Tx Disable
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
Rate Select
LOS
VEER
VEER
VEER
RDRD+
VEER
VCCR
VCCT
VEET
TD+
TDVEET
Function
Transmitter Ground
Transmitter Fault Indication
Transmitter Disable
Module Definition 2 (Serial Interface Data Line)
Module Definition 1 (Serial Interface Clock Line)
Module Definition 0 (Module Present Signals, active low)
Not Connected
Loss of Signal
Receiver Ground
Receiver Ground
Receiver Ground
Inverse Received Data Out
Received Data Out
Receiver Ground
Receiver Power
Transmitter Power
Transmitter Ground
Transmitter Data In
Inverse Transmitter Data In
Transmitter Ground
Table 8 - SFP Host Connector Pin Description
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The following table lists the FPGA I/O assignments for the SFP interfaces.
Net Name
Virtex-5 Pin#
SFP #0
SFP0_LOS
SFP0_MOD0
SFP0_MOD1
SFP0_MOD2
SFP0_RSEL
SFP0_TX_DISABLE
SFP0_TX_FAULT
H7
G5
H5
J7
D15
J5
J6
SFP #1
SFP1_LOS
SFP1_MOD0
SFP1_MOD1
SFP1_MOD2
SFP1_RSEL
SFP1_TX_DISABLE
SFP1_TX_FAULT
G7
E7
E6
G6
A15
F6
F5
Table 9 - FPGA I/O Assignments for the SFP Interfaces
2.2.4
GTX on EXP Connectors JX1 AND JX2
Two GTX transceivers are brought out to the board-to-board connectors labeled “JX1” and “JX2” on the board for use by EXP
daughter cards. The MGT124 transceiver is directly connected to JX1 and JX2 pins 54 and 56 (RX+ and RX-) and pins 53 and
55 (TX+ and TX-). The user must evaluate whether AC coupling is required on the daughter card to safely interface with the
Virtex-5 GTX transceiver. The MGT124 tile is GTX_Dual “X0Y7” in the FX70T/FX100T devices.
GTX Instance
FX70T/FX100T:
GTX_Dual_X0Y7
Net Name
EXP1_TXP
EXP1_TXN
EXP1_RXP
EXP1_RXN
EXP2_TXP
EXP2_TXN
EXP2_RXP
EXP2_RXN
Connector.pin#
JX1.53
JX1.55
JX1.54
JX1.56
JX2.53
JX2.55
JX2.54
JX2.56
Virtex-5 pin#
B10
B9
A9
A8
B5
B6
A6
A7
P/N Swapped?
No
No
No
No
Table 10 - GTX Pin Assignments for EXP Connectors
2.2.5
10 Gb/s Media Connector
Four GTX transceivers are connected to a board-to-cable connector for general purpose use. The connector footprint on the
Virtex-5 FXT PCI Express Board supports the jack screw attachment version of the Molex LaneLink™ 4X I/O connector. This
surface-mount connector is optimized for high-speed differential signals supporting serial data rates up to 3.125 Gb/s. This
interface can be used for short-range, point-to-point applications requiring full-duplex operation over four lanes (8 unidirectional
signals: 4 transmit pairs and 4 receive pairs). This interface utilizes two GTX tiles to support four RocketIO transceivers
running at 3.125 Gb/s to implement a 10 Gb/s channel. A single cable can be used to connect to EXP daughter cards with 10
Gb/s capable PHY devices for prototyping purposes. The cable is not included in the kit but can be purchased from an
authorized Molex distributor (P/N: 74506-3001). The LaneLink 4X connector is labeled “J7” on the board. The following figure
shows a high-level block diagram of the 10 Gb/s interface on the development board.
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GTX Dual X0Y4
GTX Dual X0Y5
Figure 9 - 10 Gb/s Media Connector Interface
The 10 Gb/s Media Connector is directly connected or DC coupled to the GTX ports. Care must be taken not to exceed the
GTX receiver tolerances when interfacing to external devices. The AC coupling internal to the Virtex-5 FXT GTX receiver
should not be bypassed unless the external connection has DC blocking capacitors on the transmit lanes. The “P” and “N” of
some of the differential pairs are swapped on the board to improve the PCB routing to the 10 Gb/s Media Connector. Set the
“RXPOLARITYx” and “TXPOLARITYx” attributes to logic 1 to enable the polarity inversion feature for the transceivers indicated
in the following table (see the “P/N Swapped” column). This interface utilizes four of the GTX ports; MGT112 transceivers 0
and 1, and MGT116 transceivers 0 and 1. The programmable LVDS clock synthesizer labeled “U21” on the board is used to
provide the reference clock to both tiles.
GTX Instance
FXT100T/FX70T:
GTX_Dual_X0Y4
FXT100T/FX70T:
GTX_Dual_X0Y5
Net Name
CX4_RX0P
CX4_RX0N
CX4_TX0N
CX4_TX0P
Connector.pin#
J7.2
J7.3
J7.23
J7.24
Virtex-5 pin#
P1
N1
N2
M2
P/N Swapped?
Yes
CX4_RX1P
CX4_RX1N
CX4_TX1N
CX4_TX1P
J7.5
J7.6
J7.20
J7.21
R1
T1
T2
U2
Yes
CX4_RX2P
CX4_RX2N
CX4_TX2N
CX4_TX2P
J7.8
J7.9
J7.17
J7.18
H1
G1
G2
F2
Yes
CX4_RX3P
CX4_RX3N
CX4_TX3N
CX4_TX3P
J7.11
J7.12
J7.14
J7.15
K1
J1
K2
L2
No
No
No
No
No
Table 11 - GTX Pin Assignments for 10 Gbps Media Connector
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2.3
Memory
The Virtex-5 FXT PCI Express Board is populated with both high-speed RAM and non-volatile ROM to support various types of
applications. Each development board has four memory interfaces: 1) 64MB DDR2 SDRAM, 2) 256MB DDR2 SDRAM
SODIMM, 3) 32MB non-volatile flash, and 4) 16MB Xilinx Platform XL configuration flash. If additional memory is necessary for
development, check the Avnet Design Resource Center (DRC) for the availability of EXP compliant daughter cards with
expansion memory (sold separately). Here is the link to the DRC web page: www.em.avnet.com/drc.
2.3.1
DDR2 SDRAM Interface
Two Micron DDR2 SDRAM devices, part number MT47H16M16BG-5E, make up the 32-bit data bus. Each device provides
32MB of memory on a single IC and is organized as 4 Megabits x 16 x 4 banks (256 Megabit). The Virtex-5 FXT PCI Express
Board can support larger devices with addressing support for up to 128MB (two 512-Megabit devices). The device has an
operating voltage of 1.8V and the interface is JEDEC Standard SSTL_18 (Class I for unidirectional signals, Class II for
bidirectional signals). The -5 speed grade supports 5 ns cycle times with a 3 clock read latency (DDR2-400). The following
figure shows a high-level block diagram of the DDR2 SDRAM interface on the development board.
Data[
Data[15:
15:0]
Addr[[12:
Addr
12:0]
BA[
BA[1:0]
CLK0
CLK0_P/N
DQS1
DQS1_P/N
DQS0
DQS0_P/N
DQM1
DQM1
DQM0
DQM0
CSn
CLKEN
WEn
RASn
CASn
ODT
VirtexVirtex-5
FF1136
FF1136
16M
16M x 16
DDR2
DDR2
SDRAM
Data[
Data[31:
31:16]
16]
16M
16M x 16
DDR2
DDR2
SDRAM
DQM3
DQM3
DQM2
DQM2
DQS3
DQS3_P/N
DQS2
DQS2_P/N
CLK1
CLK1_P/N
Figure 10 - DDR2 SDRAM Interface
The DDR2 signals are connected to I/O Banks 9, 11 and 18 of the Virtex-5 FXT FPGA. The output supply pins (VCCO) for the
DDR2 banks are connected to 1.8 Volts. This supply rail can be measured at test point TP1. The reference voltage pins
(VREF) for the DDR2 banks are connected to the reference output of the TI TPS51116 3 amp LDO Synchronous buck
controller. This device provides the supply voltage and reference voltage necessary for the SSTL_18 I/O standard. The
termination voltage is 0.9 Volts and can be measured at test point TP2.
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The following table provides timing and other information about the Micron device necessary to implement a DDR2 memory
controller.
MT47H16M16BG-5E: Timing Parameters
Load Mode Register time (TMRD)
Write Recovery time (TWR)
Write-to-Read Command Delay (TWTR)
Delay between ACT and PRE Commands (TRAS)
Delay after ACT before another ACT (TRC)
Delay after AUTOREFRESH Command (TRFC)
Delay after ACT before READ/WRITE (TRCD)
Delay after ACT before another row ACT (TRRD)
Delay after PRECHARGE Command (TRP)
Refresh Command Interval (TREFC)
Avg. Refresh Period (TREFI)
Time (ps) or
Number
2 tCK
15000
10000
40000
55000
75000
15000
10000
15000
70000000
7800000
Memory Data Width (DWIDTH) (2 devices)
Row Address Width (AWIDTH)
Column Address Width (COL_AWIDTH)
Bank Address Width (BANK_AWIDTH)
Memory Range (64 MB total)
32
13
9
2
0x3FFFFFF
Table 12 - DDR2 SDRAM Timing Parameters
The following guidelines were used in the design of the DDR2 interface to the Virtex-5 FXT FPGA. These guidelines are based
on Micron recommendations and board level simulation.
•
50 ohm* controlled trace impedance
•
Dedicated data bus with matched trace lengths (+/- 50 mils)
•
Memory clocks and data strobes routed differentially
•
Series termination on bidirectional signals at the memory device
•
Parallel termination following the memory device connection on shared signals (control, address)
•
50 ohm* pull-up resistor to the termination supply (0.9V) on clock signals
•
100 ohm* pull-up resistor to the termination supply on each branch of shared signals (control, address)
•
Termination supply that can both source and sink current
•
Feedback clock routed with twice the length to simulate the total flight time
* Ideal impedance values. Actual may vary.
Some of the design considerations were specific to the Virtex-5 architecture. For example, the data strobe signals (DQS) were
placed on Clock Capable I/O pins in order to support data capture techniques utilizing the SERDES function of the Virtex-5 I/O
blocks. All DDR2 signals are compliant to the Xilinx recommended and MIG generated pin out.
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The following table contains the FPGA pin numbers for the DDR2 SDRAM interface.
Net Name
DDR2_A0
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
Virtex-5 pin#
AB28
AA28
AG28
AH28
AE28
AF28
AH27
AJ26
AF24
AG25
AG27
AF25
AF26
DDR2_BA0
DDR2_BA1
AK29
AK27
DDR2_CS#
DDR2_ODT
AD31
AH30
DDR2_WE#
DDR2_RAS#
DDR2_CAS#
DDR2_CLKEN
DDR2_CK0
DDR2_CK0#
DDR2_CK1
DDR2_CK1#
AD26
AC24
AC25
AD25
AH29
AG30
AD24
AE24
DDR2_DQS0
DDR2_DQS0#
DDR2_DQS1
DDR2_DQS1#
DDR2_DQS2
DDR2_DQS2#
DDR2_DQS3
DDR2_DQS3#
AK26
AJ27
AB30
AC30
AB31
AA31
Y28
Y29
Net Name
DDR2_D0
DDR2_D1
DDR2_D2
DDR2_D3
DDR2_D4
DDR2_D5
DDR2_D6
DDR2_D7
DDR2_D8
DDR2_D9
DDR2_D10
DDR2_D11
DDR2_D12
DDR2_D13
DDR2_D14
DDR2_D15
DDR2_D16
DDR2_D17
DDR2_D18
DDR2_D19
DDR2_D20
DDR2_D21
DDR2_D22
DDR2_D23
DDR2_D24
DDR2_D25
DDR2_D26
DDR2_D27
DDR2_D28
DDR2_D29
DDR2_D30
DDR2_D31
Virtex-5 pin#
AB26
AB25
AA24
Y24
AC27
AB27
AA26
AA25
AK31
AJ31
AD29
AE29
AF31
AC29
AD30
AA30
AA29
V29
W29
Y31
W31
V27
V28
V30
W27
Y27
W25
V25
W26
Y26
V24
W24
DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3
AC28
AJ30
AF30
AF29
Table 13 - FPGA Pin Assignments for DDR2 SDRAM
2.3.2
DDR2 SODIMM Interface
The Virtex-5 FXT PCI Express Board implements a 200-pin, small outline, dual in-line memory module (SODIMM) interface. A
Micron DDR2 SDRAM module, part number MT4HTF3264HY-53E, is populated in the SODIMM connector labeled “U38” on
the backside of the board. This single rank module provides up to 256MB of memory organized as 32 Meg x 64. The
bandwidth of the -53E speed grade module is 4.3GB/s with a memory clock of 533 MHz (3.75ns). The Virtex-5 FXT PCI
Express Board was designed to support larger density modules with eight-bank addressing and dual rank modules with two
chip selects.
The DDR2 SODIMM signals are connected to I/O Banks 11, 15, 19, and 23 of the Virtex-5 FXT FPGA. The output supply pins
(VCCO) for these banks are connected to 1.8 Volts. I single Texas Instruments TPS51116PWP buck regulator is used to
supply both the 1.8V supply voltage as well as the 0.9V reference and termination voltage necessary to implement the
SSTL_18 I/O standard. The termination voltage rail “0.9V_TT” can be measured at test point TP2.
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The following table provides timing and other information about the Micron device necessary to implement a DDR2 SODIMM
memory controller.
MT4HTF3264HY-53ED3: Timing Parameters
Load Mode Register time (TMRD)
Write Recovery time (TWR)
Write-to-Read Command Delay (TWTR)
Delay between ACT and PRE Commands (TRAS)
Delay after ACT before another ACT (TRC)
Delay after AUTOREFRESH Command (TRFC)
Delay after ACT before READ/WRITE (TRCD)
Delay after ACT before another row ACT (TRRD)
Delay after PRECHARGE Command (TRP)
Refresh Command Interval (TREFC)
Avg. Refresh Period (TREFI)
Memory Data Width (DWIDTH)
Row Address Width (AWIDTH)
Column Address Width (COL_AWIDTH)
Bank Address Width (BANK_AWIDTH)
Memory Range (256 MB total)
Time (ps) or
Number
2 tCK
15000
10000
40000
55000
75000
15000
10000
15000
70000000
7800000
64
13
10
2
0xFFFFFFF
Table 14 - DDR2 SODIMM Parameters
The following guidelines were used in the design of the DDR2 SODIMM interface to the Virtex-5 FXT FPGA. These guidelines
are based on Micron recommendations and board level simulation.
•
50 ohm* controlled trace impedance
•
Dedicated data bus with matched trace lengths (+/- 50 mils)
•
Memory clocks and data strobes routed differentially
•
50 ohm* pull-up resistor to the termination supply (0.9V) on clock, control and address signals
•
Termination supply that can both source and sink current
•
Feedback clock routed with twice the length to simulate the total flight time
* Ideal impedance values. Actual may vary.
Some of the design considerations were specific to the Virtex-5 architecture. For example, the data strobe signals (DQS) were
placed on Clock Capable I/O pins in order to support data capture techniques utilizing the SERDES function of the Virtex-5 I/O
blocks. The appropriate DDR2 memory signals were placed in the clock regions that correspond to these particular Clock
Capable I/O pins.
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The following table contains the FPGA pin numbers for the DDR2 SODIMM interface.
DDR2_DIMM_A0
DDR2_DIMM_A1
DDR2_DIMM_A2
DDR2_DIMM_A3
DDR2_DIMM_A4
DDR2_DIMM_A5
DDR2_DIMM_A6
DDR2_DIMM_A7
DDR2_DIMM_A8
DDR2_DIMM_A9
DDR2_DIMM_A10
DDR2_DIMM_A11
DDR2_DIMM_A12
Virtex-5
pin#
B32
A33
B33
C33
C32
D32
C34
D34
G32
F33
E34
E32
E33
DDR2_DIMM_BA0
DDR2_DIMM_BA1
DDR2_DIMM_BA2
H33
H34
J34
DDR2_DIMM_S0#
DDR2_DIMM_S1#
DDR2_DIMM_ODT0
DDR2_DIMM_ODT1
DDR2_DIMM_WE#
DDR2_DIMM_RAS#
DDR2_DIMM_CAS#
DDR2_DIMM_CKE0
DDR2_DIMM_CKE1
DDR2_DIMM_CK0
DDR2_DIMM_CK0#
DDR2_DIMM_CK1
DDR2_DIMM_CK1#
M32
P34
T33
R34
K33
K34
L34
K32
L33
U33
T34
U32
U31
DDR2_DIMM_SA0
DDR2_DIMM_SA1
R33
R32
DDR2_DIMM_SDA
DDR2_DIMM_SCL
P32
N32
DDR2_DIMM_EVENT
T24
Net Name
DDR2_DIMM_D0
DDR2_DIMM_D1
DDR2_DIMM_D2
DDR2_DIMM_D3
DDR2_DIMM_D4
DDR2_DIMM_D5
DDR2_DIMM_D6
DDR2_DIMM_D7
DDR2_DIMM_DM0
DDR2_DIMM_DQS0
DDR2_DIMM_DQS0#
Virtex-5
pin#
U28
U27
T29
T28
U30
R31
T31
N30
U26
P31
P30
DDR2_DIMM_D32
DDR2_DIMM_D33
DDR2_DIMM_D34
DDR2_DIMM_D35
DDR2_DIMM_D36
DDR2_DIMM_D37
DDR2_DIMM_D38
DDR2_DIMM_D39
DDR2_DIMM_DM4
DDR2_DIMM_DQS4
DDR2_DIMM_DQS4#
Virtex-5
pin#
E26
F26
F25
H24
H25
G26
G25
J27
P24
H28
G28
DDR2_DIMM_D8
DDR2_DIMM_D9
DDR2_DIMM_D10
DDR2_DIMM_D11
DDR2_DIMM_D12
DDR2_DIMM_D13
DDR2_DIMM_D14
DDR2_DIMM_D15
DDR2_DIMM_DM1
DDR2_DIMM_DQS1
DDR2_DIMM_DQS1#
M31
M30
L30
J31
J30
G31
H30
L29
R27
K31
L31
DDR2_DIMM_D40
DDR2_DIMM_D41
DDR2_DIMM_D42
DDR2_DIMM_D43
DDR2_DIMM_D44
DDR2_DIMM_D45
DDR2_DIMM_D46
DDR2_DIMM_D47
DDR2_DIMM_DM5
DDR2_DIMM_DQS5
DDR2_DIMM_DQS5#
M26
M25
J25
J24
L26
L25
L24
K24
N24
G27
H27
DDR2_DIMM_D16
DDR2_DIMM_D17
DDR2_DIMM_D18
DDR2_DIMM_D19
DDR2_DIMM_D20
DDR2_DIMM_D21
DDR2_DIMM_D22
DDR2_DIMM_D23
DDR2_DIMM_DM2
DDR2_DIMM_DQS2
DDR2_DIMM_DQS2#
E31
F31
J29
H29
F30
G30
F29
E29
R26
N29
P29
DDR2_DIMM_D48
DDR2_DIMM_D49
DDR2_DIMM_D50
DDR2_DIMM_D51
DDR2_DIMM_D52
DDR2_DIMM_D53
DDR2_DIMM_D54
DDR2_DIMM_D55
DDR2_DIMM_DM6
DDR2_DIMM_DQS6
DDR2_DIMM_DQS6#
B30
A30
D30
D31
D29
C30
A31
B31
A24
B25
C25
DDR2_DIMM_D24
DDR2_DIMM_D25
DDR2_DIMM_D26
DDR2_DIMM_D27
DDR2_DIMM_D28
DDR2_DIMM_D29
DDR2_DIMM_D30
DDR2_DIMM_D31
DDR2_DIMM_DM3
DDR2_DIMM_DQS3
DDR2_DIMM_DQS3#
P27
P26
N28
M28
K27
L28
K28
E27
P25
E28
F28
DDR2_DIMM_D56
DDR2_DIMM_D57
DDR2_DIMM_D58
DDR2_DIMM_D59
DDR2_DIMM_D60
DDR2_DIMM_D61
DDR2_DIMM_D62
DDR2_DIMM_D63
DDR2_DIMM_DM7
DDR2_DIMM_DQS7
DDR2_DIMM_DQS7#
D27
C28
A29
C27
D26
A25
B26
D25
C24
B27
A26
Net Name
Net Name
Table 15 - FPGA Pin Assignments for DDR2 SODIMM
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2.3.3
P30 Flash Interface
The Flash memory consists of a single 32MB Intel StrataFlash Embedded Memory (P30) device in a 64-ball Easy BGA
package. The P30 device is an asynchronous memory that also supports a synchronous-burst read mode for highperformance applications. The P30 device has an 85 nanosecond access time. The P30 flash connects to pins in Banks 1, 2
and 4 of the Virtex-5 FPGA. The Flash I/O voltage (VCCQ) is set to 3.3V to match the VCCO voltage of Banks 1 and 2. The
following figure shows a high-level block diagram of the P30 flash interface on the development board.
Figure 11 - Flash Interface
The following table contains the FPGA pin numbers for the Flash interface.
Net Name
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
FLASH_A24
FLASH_A25
Virtex-5 pin#
K12
K13
H23
G23
H12
J12
K22
K23
K14
L14
H22
G22
J15
K16
K21
J22
L16
L15
L20
L21
AE23
AE22
AG12
J17
K19
NC
Net Name
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_D8
FLASH_D9
FLASH_D10
FLASH_D11
FLASH_D12
FLASH_D13
FLASH_D14
FLASH_D15
Virtex-5 pin#
AD19
AE19
AE17
AF16
AD20
AE21
AE16
AF15
AH13
AH14
AH19
AH20
AG13
AH12
AH22
AG22
FLASH_CE#
FLASH_WE#
FLASH_OE#
FLASH_RST#
FLASH_BYTE#
FLASH_WAIT
FLASH_ADV#
FLASH_CLK
AL34
AF20
AF14
AK32
AH32
AL33
V10
AJ32
Table 16 - Flash Interface Pin Assignments
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2.3.4
Platform Flash Interface
The Virtex-5 FXT PCI Express Board utilizes an on-board Xilinx Platform Flash XL device to configure the FPGA quickly using
Select Map or BPI configuration modes. The Platform Flash device can also be used to store user data. When being used to
configure the FPGA, the flash clock is sourced by the FPGA CCLK pin. A separate IO pin on the FPGA is used to source a
clock to the Platform Flash when the device isn’t being used for configuration. A jumper must be placed at J11 to connect the
user IO to the Platform Flash. The diagram below shows how both the P30 flash and Platform Flash are connected to the
FPGA.
Jumpers
Virtex-5 FX70T/FX100T
FF1136
M2
INIT_B
M1
PROGRAM_B
Xilinx Platform Flash XL
(16MB)
READY_WAIT
RPn
M0
Ln
IO_L9P_CC_GC_4
pull-up
FPGA I/O
WPn
K
CCLK
ADDR[22:0]
Address[22:0]
FWE_B
Wn
FOE_B
Gn
FCS_B
En
Data[15:0]
Data[15:0]
Intel TE28F256P30
(32MB)
Data[15:0]
OEn
WEn
Address[22:0]
FPGA I/O
Address [23]
FPGA I/O
Address[24]
FPGA I/O
CSn
Figure 12 - V5FXT Development Board Flash Interface
2.4
Clock Sources
The Virtex-5 FXT PCI Express board includes all of the necessary clocks on the board to implement high-speed logic and
RocketIO transceiver designs as well as providing the flexibility for the user to supply their own application specific clocks. The
clock sources described in this section are used to derive the required clocks for the memory and communications devices,
and the general system clocks for the logic design. This section also provides information on how to supply external user
clocks to the FPGA via the on-board connectors and oscillator socket. For a description of the GTX reference clock sources,
see Section 2.2.1.
The following figure shows the clock nets connected to the I/O banks containing the global clock input pins on the Virtex-5 FXT
FPGA. Fifteen out of the twenty global clock inputs of the Virtex-5 FPGA are utilized on the board. However the majority of
these inputs are for expansion clocks and user inputs. It should be noted that single-ended clock inputs must be connected to
the P-side of the pin pair because a direct connection to the global clock tree only exists on this pin. The I/O voltages (VCCO)
for the two FPGA banks containing the global clock input pins (Banks 3 and 4) are jumper selectable to either 2.5V or 3.3V. In
order to use the differential clock inputs as LVDS inputs, the VCCO voltage for the corresponding bank must be set for 2.5V
since the Virtex-5 FPGA does not support 3.3V differential signaling. Single-ended clock inputs do not have this restriction and
may be either 2.5V or 3.3V. The interface clocks coming from 3.3V devices on the board are level-shifted to the appropriate
VCCO voltage by CB3T standard logic devices prior to the Virtex-5 input pins. Setting both of the voltage selection jumpers to
2.5V (default condition) enables the board to support both single-ended and differential clock inputs.
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GREFCLK_P
GBE_AUX_MCLK
GREFCLK_N
GBE_FP_MCLK
GMII_AUX_TX_CLK
GMII_AUX_RX_CLK
GMII_FP_TX_CLK
GMII_FP_RX_CLK
USB IF CLK
EXP1_DIFF_CLK_IN_N
EXP2_DIFF_CLK_IN_N
SystemAce CLK
EXP1_DIFF_CLK_IN_P
EXP2_DIFF_CLK_IN_P
EXP1_SE_CLK_IN
EXP2_SE_CLK_IN
Figure 12 - Clock Nets Connected to Global Clock Inputs
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The on-board 100 MHz oscillator provides the system clock input to the global clock tree. This single-ended, 100 MHz clock
can be used in conjunction with the Virtex-5 Clock Management Tiles (CMTs) to generate the various logic clocks and the
clocks forwarded to the DDR2 SDRAM devices. The interface clocks supplied by the communications devices are derived from
dedicated crystal oscillators.
Additionally, there are two on-board Maxim MAX3674 LVDS clock synthesizers that are connected to various GTX dual tiles to
giving the user the ability to source those tiles with a wide range of frequencies. Please note that the standard output type for
these synthesizers is LVPECL. The circuitry surrounding the outputs of U7 and U21 converts the LVPECL outputs to LVDS for
use with the FPGA inputs. SMA connectors are also attached to the outputs of these devices so that the user can utilize the
clock sources off-board if needed. The MAX3674 clock synthesizers are explained in detail in Section 2.4.1.
Reference#
Frequency
Derived Interface Clock
U10
Y3
100 MHz
24 MHz
Y1
16 MHz
Y4
25 MHz
Y2
25 MHz
Y5
25 MHz
CLK_100 MHZ
USB_IFCLK
CLK_SYN0_P
CLK_SYN0_N
SMA_OUT_P (J1)
SMA_OUT_N (J2)
GMII_AUX_RX_CLK
GMII_AUX_TX_CLK
GBE_AUX_MCLK
CLK_SYNTH1_P
CLK_SYNTH1_N
SMA_OUT_P (J3)
SMA_OUT_N (J4)
GMII_FP_RX_CLK
GMII_FP_TX_CLK
GBE_FP_MCLK
Derived
Frequency
100 MHz
30, 48 MHz
21.25 – 1360
MHz
2.5, 25, 125 MHz
125 MHz
125 MHz
21.25 – 1360
MHz
2.5, 25, 125 MHz
125 MHz
125 MHz
Virtex-5 pin#
G15
L19
D8 (GTX X0Y7)
C8 (GTX X0Y7)
--J20
J16
H19
H4 (GTX X0Y5)
H3 (GTX X0Y5)
--AG18
AH17
J14
Table 17 - On-Board Clock Sources
In addition to the 100 MHz oscillator, an 8-pin DIP clock socket is provided on the board so the user can supply their own
oscillator of choice. The socket is a single-ended, LVTTL or LVCMOS compatible clock input to the FPGA that can be used as
an alternate source for the system clock.
Signal Name
Enable
GND
Output
VDD
Socket pin#
1
4
5
8
Table 18 - Clock Socket "U25" Pin-out
There are two pairs of SMA connectors for user supplied differential clocks. The first pair is connected to dedicated GTX clock
input pins to provide a reference clock to the transceivers as shown in Figure 4 in Section 2.2.1. The reference designators for
these connectors are “J24” and “J25”. The silk screen labels indicate the polarity of the inputs with a trailing minus sign for the
N pin and a positive sign for the P pin. These differential clock inputs are AC coupled to the Virtex-5 MGTREFCLK_120 pins.
The other pair of SMA connectors is connected to global clock input pins for general purpose use. The P-side connector could
alternatively be used for a single-ended clock. If supplying a differential clock to the SMA connectors labeled “J26” and “J27”,
make sure the jumper on “JP6" is set for 2.5V and limit the peak-to-peak voltage to 2.5V.
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Net Name
CLK_SOCKET
GREFCLK_P
GREFCLK_N
CLK_SMA_P
CLK_SMA_N
Input Type
Global clock
Connector.pin#
U25.5
J26.1
J27.1
J24.1
J25.1
Global clock
GTX clock
Virtex-5 pin#
K18
AF18
AE18
E4
D4
Table 19 - User Clock Inputs
2.4.1
MAX3674 Programmable LVDS Clock Synthesizer
The Virtex-5 FXT PCI Express Development Board design uses the Maxim MAX3674 LVPECL/LVDS frequency synthesizers
for generating various clock frequencies. A list of features included in the MAX3674 device is shown below.
•
Output frequency range: 21.25 MHz to 1360 MHz
•
RMS period jitter: 0.9 ps @ 500 MHz
•
Cycle-to-cycle jitter: 1.6 ps @ 500 MHz
•
Output rise and fall time: 340 ps (maximum)
•
Output duty cycle: varies dependant on output frequency
The following figure shows a high-level block diagram of the MAX3674 programmable clock synthesizer.
MR_N
LOCK
XTAL1
XTAL2
CLKOUT0
SDA
QA
QA_N
MAX3674
CLKOUT1
SCL
Serial Load
ADR[0:1]
Control
NB
P
PLOAD_N
QB
QB_N
Clock Input
N[0:2]
Parallel Load
M[0:9]
Figure 13 – MAX3674 Clock Synthesizer
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Signal Name
M0:M1, M3, M9
M2, M4:M8
NA0, NA2, NB
NA1
P
PLOAD_N
MR_N
Direction
Input
Input
Input
Input
Input
Input
Input
Pull up/Pull down
Pull up
Pull down
Pull up
Pull down
Pull down
Pull up
Pull up
SCL
Input
Pull up
SDA
Bidir
Pull up
ADDR[0:1]
Input
Appendix
XTAL1, XTAL2
Input
LOCK
Output
QA, QB
QAN, QBN
Output
Output
Description
The PLL feedback divider configuration inputs.
The PLL post-divider programming inputs.
The PLL pre-divider programming input.
Programming Interface select (Default = Parallel)
Active low reset signal.
Serial interface clock input. Data is shifted into
the device on the rising edge of this clock.
Serial interface data input.
Serial interface address. The address is
determined by JT jumpers on the Mini Module
baseboard.
Crystal clock input/output
The PLL frequency locked status indicator. This
is attached to an LED that illuminates when the
PLL is locked. LED D10, D11, D12 correspond to
the 3 MAX3674 devices on the board.
Positive clock outputs
Negative clock outputs
Table 20 - MAX3674 Clock Synthesizer Pin Description
2.4.1.1
MAX3674 Clock Generation
The MAX3674 output clocks are generated based on the following formula (assuming the crystal clock input is set to 16 MHz):
(1) Determine the output divider setting, NA, which encompasses the output frequency.
(Table 8 of the MAX3674 datasheet)
(2) Calculate the VCO Frequency:
FVCO = FOUT x NA
(3) Determine the setting for the feedback divider, M:
M = (FVCO / FREF) x P
REQUIREMENT: 1359 < FVCO < 2721
(4) Configure the MAX3674 with the obtained settings by programming the dipswitches on the Virtex-5 FXT
PCI Express Development Board
Equation Variables:
FREF = Crystal Frequency
P = Pre-PLL Divider (Table 4 of the MAX3674 datasheet)
M = PLL Feedback Divider (Table 5 of the MAX3674 datasheet)
NA = Post-PLL Divider (Table 6 of the MAX3674 datasheet)
NB = Output Divider Setting (Table 7 of the MAX3674 datasheet)
FREQUENCY RANGES (Table 8 of the MAX3674 datasheet)
Please refer to the MAX3674 datasheet for detailed tables regarding the parallel interface configuration details. The MAX3674
parallel interface is programmed via a set of dipswitches on the Mini Module Plus baseboard. These dipswitches should be
configured prior to powering up the board.
The following table shows how the parallel interface can be set to generate a clock source for a common application. All the
values are based on the 16 MHz crystal clock input to the MAX3674 device.
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Interconnect
Technology
1 Gbps
Ethernet
10 Gbps
XAUI
2.5 Gbps
PCIe
QA
or
QB
( MHz)
MAX3674 M, NA, NB, and P Settings
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
NA2
NA1
NA0
NB
P
125.00
0
1
1
1
1
1
0
1
0
0
1
1
0
0
1
156.25
1
0
0
1
1
1
0
0
0
1
1
1
0
0
1
250.00
0
1
1
1
1
1
0
1
0
0
0
1
0
0
1
Table 21- Example of the MAX3674 M, NA, NB, and P Settings
2.4.1.2
MAX3674 Programming Mode
The Virtex-5 FXT PCI Express Development Board allows programming of the M and N values in parallel mode. In parallel
mode, M, NA, NB, and P values are programmed into the device upon the release of the master reset signal (rising edge of the
MR_N signal). Please refer to the MAX3674 datasheet for more information on programming through the parallel interface.
2.4.1.3
MAX3674 M, NA, NB, and P Settings
The following figure shows how the MAX3674 programmable clock synthesizer is used on the Virtex-5 FXT PCI Express
Development Board. Parallel Mode is supported via DIP switches that are provided on the board for the manual setting of the
M, NA, NB, and P values for the MAX3674 devices.
The following tables show the DIP switch settings for M, NA, NB, and P selections. Please refer to Table 20 for the information
on pull-up and pull-down resistors provided internal to the MAX3674 device for the M, NA, NB, and P input signals.
Figure 14 – M, NA, NB, and P DIP Switches for the MAX3674
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SWITCH[9:0]
M[9:0]
DIP10
DIP9
DIP8
DIP7
DIP6
DIP5
DIP4
DIP3
DIP2
DIP1
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Switch Position
OFF
0
1
1
1
1
1
0
1
0
0
ON
1
0 - Note (1)
0 - Note (1)
0 - Note (1)
0 - Note (1)
0 - Note (1)
1
0 - Note (1)
1
1
Table 22 - DIP Switch Setting for M[9:0]
Note(1) – The polarity is the opposite of all other DIP switch positions to compensate for internal pullup or pulldown resistors in
the MAX3674 device.
SWITCH[3:0]
NA[2:0], NB
DIP3
DIP2
DIP1
DIP0
NA2
NA1
NA0
NB
Switch Position
OFF
0
1
0
0
ON
1
0 – Note(1)
1
1
Table 23 - DIP Switch Setting for NA[2:0] and NB
Note(1) – The polarity is the opposite of all other DIP switch positions to compensate for internal pullup or pulldown resistors in
the MAX3674 device.
SWITCH[1:0]
P, PLOAD_N
DIP1
DIP0
P
PLOAD_N
Switch Position
OFF
1
0
ON
0 – Note(1)
1
Table 24 - DIP Switch Setting for P and PLOAD_N
Note(1) – The polarity is the opposite of all other DIP switch positions to compensate for internal pullup or pulldown resistors in
the MAX3674 device.
The following table shows the FPGA pin and SMA connector assignments for the two MAX6374 devices.
Device
U7
U7
U21
U21
Net Name
MAX1_QA_p
MAX1_QA_n
CLK_SYN0_p
CLK_SYN0_p
MAX2_QA_p
MAX2_QA_n
CLK_SYN1_p
CLK_SYN2_p
I/O Type
SMA Output
FPGA INPUT
SMA Output
FPGA INPUT
Connector.pin#
J1
J2
J3
J4
-
Virtex-5 pin#
D8 (MGT_124)
C8 (MGT_124)
H4 (MGT_116)
H3 (MGT_116)
Table 25 - MAX3674 Pin Assignments
2.5
Communication
The Virtex-5 FXT FPGA has access to Ethernet, USB and RS232 physical layer transceivers for communication purposes.
Network access is provided by two 10/100/1000 Mb/s Ethernet PHY devices, which are connected to the Virtex-5 via standard
GMII interfaces. The PHY devices connect to the outside world with standard RJ45 connectors. The primary connector is
located on the PCI faceplate. The auxiliary connector is only accessible if the PC cover is left open or if the board is used
standalone (not plugged into a PC). General purpose I/O transfers are supported by way of the USB 2.0 port. The USB Type B
peripheral connector on the faceplate facilitates communication with the board while enclosed in a PC case. Serial port
communication to the embedded PowerPC processor or FPGA fabric is provided through a dual-channel RS232 transceiver.
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2.5.1
10/100/1000 Ethernet PHY
The PHY devices are National DP83865DVH Gig PHYTER V. The DP83865 is a low power version of National’s Gig
PHYTER V with a 1.8V core voltage and a selectable I/O voltage (2.5V or 3.3V). The PHY is connected to a Tyco RJ-45 jack
with integrated magnetics (part number: 1-6605833-1). The jack also integrates two LEDs and their corresponding resistors as
well as several other passive components. External logic is used to logically OR the three link indicators for 10, 100 and 1000
Mb/s to drive a Link LED on the RJ-45 jack. The external logic is for the default strap options and may not work if the strap
options are changed. Four more LEDs are provided on the board for status indication. These LEDs indicate Link at 10 Mb/s,
Link at 100 Mb/s, Link at 1000 Mb/s and Full Duplex operation. The PHY clock is generated from its own 25 MHz crystal. The
following figure shows a high-level block diagram of the interface to the DP83865 Tri-mode Ethernet PHY.
Figure 15 - 10/100/1000 Mb/s Ethernet Interface
Both PHY devices have the same address, 0b00001 by default, since they have separate, dedicated management interfaces.
PHY address 0b00000 is reserved for a test mode and should not be used. Three-pad resistor jumpers are used to set the
strapping options. These jumper pads provide the user with the ability to change the settings by moving the resistors. The
strapping options used for both PHY devices are shown in the following table. The dual-function pins that are used for both a
strapping option and to drive an LED, have a set of two jumpers per pin. The dual-function pins are indicated by an asterisk in
the table.
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Function
Auto-Negotiation*
Full/Half Duplex*
Speed 1*
Speed 0*
PHY address 0*
Non-IEEE Compliant Mode
Manual MDIX Setting
Auto MDIX Enable
Multiple Node Enable
Clock to MAC Enable
Jumper Installation
Faceplate (U25)
Auxiliary (U12)
JT32: pins 1-2
JT13: pins 1-2
JT33: pins 1-2
JT14: pins 1-2
JT32: pins 2-3
JT13: pins 2-3
JT33: pins 2-3
JT14: pins 2-3
JT30: pins 1-2
JT15: pins 1-2
JT31: pins 1-2
JT16: pins 1-2
JT30: pins 2-3
JT15: pins 2-3
JT31: pins 2-3
JT16: pins 2-3
JT29: pins 1-2
JT17: pins 1-2
JT37: pins 1-2
JT18: pins 1-2
Resistor
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
(Speed1 – 0)
(Speed1 – 0)
JT23: pins 1-2
JT25: pins 1-2
JT5: pins 1-2
JT6: pins 1-2
0 ohm
0 ohm
(Speed0 – 0)
JT34: pins 1-2
JT38: pins 1-2
JT34: pins 2-3
JT38: pins 2-3
JT35: pins 1-2
JT35: pins 2-3
JT36: pins 1-2
JT36 pins 2-3
JT27: pins 1-2
JT27: pins 2-3
(Speed0 – 0)
JT19: pins 1-2
JT20: pins 1-2
JT19: pins 2-3
JT20: pins 2-3
JT9: pins 1-2
JT9: pins 2-3
JT12: pins 1-2
JT12: pins 2-3
JT10: pins 1-2
JT10: pins 2-3
0 ohm
0 ohm
0 ohm
0 ohm
1K
1K
1K
1K
1K
1K
JT26: pins 1-2
JT26: pins 2-3
JT24: pins 1-2
JT24: pins 2-3
JT8: pins 1-2
JT8: pins 2-3
JT11: pins 1-2
JT11: pins 2-3
1K
1K
1K
1K
Mode Enabled
Auto-negotiation enabled (default)
Auto-negotiation disabled
Full Duplex (default)
Half Duplex
Speed Selection: (Auto-Neg enabled)
Speed1 Speed0 Speed Advertised
1
1
1000BASE-T, 10BASE-T
1
0
1000BASE-T
0
1
1000BASE-T, 100BASE-TX
0
0
1000BASE-T, 100BASE-TX,
10BASE-T
Default: 1000BASE-T, 100BASE-TX, 10BASE-T
PHY Address 0b00001 (default)
PHY Address 0b00000
Compliant and Non-comp. Operation (default)
Inhibits Non-compliant operation
Straight Mode (default)
Cross-over Mode
Automatic Pair Swap – MDIX (default)
Set to manual preset – Manual MDIX Setting
(JT12)
Single node – NIC (default)
Multiple node priority – switch/hub
CLK_TO_MAC output enabled (default)
CLK_TO_MAC output disabled
Table 26 - Ethernet PHY Hardware Strapping Options
The default options as indicated in Table 26 are Auto-Negotiation enabled, Full Duplex mode, Speed advertised as
10/100/1000 Mb/s, PHY address 0b00001, IEEE Compliant and Non-compliant support, straight cable in non-MDIX mode,
auto-MDIX mode enabled, Single node (NIC) and CLK_TO_MAC enabled. The pin-out for a jumper pad is shown below.
JT#
1
2
3
The auto-MDIX mode provides automatic swapping of the differential pairs. This allows the PHY to work with either a straightthrough cable or crossover cable. Use a CAT-5e or CAT-6 Ethernet cable when operating at 1000 Mb/s (Gigabit Ethernet). The
boundary-scan Test Access Port (TAP) controller of the DP83865 must be in reset for normal operation. This active low reset
pin of the TAP (TRST) is pulled low through a 1K resistor on the board.
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The following tables provide the Virtex-5 pin assignments for the Ethernet PHY interfaces.
Net Name
GBE_FP_MDC
GBE_ FP_MDIO
GBE_ FP_MCLK
GMII_ FP_GTC_CLK
GMII_ FP_TXD0
GMII_ FP_TXD1
GMII_ FP_TXD2
GMII_ FP_TXD3
GMII_ FP_TXD4
GMII_ FP_TXD5
GMII_ FP_TXD6
GMII_ FP_TXD7
GMII_ FP_TX_EN
GMII_ FP_TX_ER
GMII_ FP_TX_CLK
Virtex-5 pin#
P7
P6
J14
T9
M6
M5
N8
N7
M7
L6
N5
P5
L5
L4
AH17
Net Name
GBE_ FP_INT#
GBE_ FP_RST#
GMII_ FP_CRS
GMII_ FP_COL
GMII_ FP_RXD0
GMII_ FP_RXD1
GMII_ FP_RXD2
GMII_ FP_RXD3
GMII_ FP_RXD4
GMII_ FP_RXD5
GMII_ FP_RXD6
GMII_ FP_RXD7
GMII_ FP_RX_DV
GMII_ FP_RX_ER
GMII_ FP_RX_CLK
Virtex-5 pin#
K7
K6
R6
T6
R8
T8
U7
R9
P9
R11
P10
T10
T11
U10
AG18
Table 27 – Faceplate Ethernet PHY “U25” Pin Assignments
Net Name
GBE_AX_MDC
GBE_ AX _MDIO
GBE_ AX _MCLK
GMII_ AX_GTC_CLK
GMII_ AX _TXD0
GMII_ AX _TXD1
GMII_ AX _TXD2
GMII_ AX _TXD3
GMII_ AX _TXD4
GMII_ AX _TXD5
GMII_ AX _TXD6
GMII_ AX _TXD7
GMII_ AX _TX_EN
GMII_ AX _TX_ER
GMII_ AX _TX_CLK
Virtex-5 pin#
D24
E23
H19
E24
E19
F19
C17
D17
E21
D20
G21
E18
E16
D16
J16
Net Name
GBE_ AX _INT#
GBE_ AX _RST#
GMII_ AX _CRS
GMII_ AX _COL
GMII_ AX _RXD0
GMII_ AX _RXD1
GMII_ AX _RXD2
GMII_ AX _RXD3
GMII_ AX _RXD4
GMII_ AX _RXD5
GMII_ AX _RXD6
GMII_ AX _RXD7
GMII_ AX _RX_DV
GMII_ AX _RX_ER
GMII_ AX _RX_CLK
Virtex-5 pin#
B17
F24
F21
F20
D19
D21
D22
F18
G18
E22
F23
G17
F16
E17
J20
Table 28 - Auxiliary Ethernet PHY "U12" Pin Assignments
2.5.2
Universal Serial Bus (USB)
The Virtex-5 FXT PCI Express Development Board includes a Cypress EZ-USB FX2™ USB Microcontroller, part number
CY7C68013A-100AC. The EZ-USB FX2 device is a single-chip integrated USB 2.0 transceiver, Serial Interface Engine (SIE)
and 8051 microcontroller. This device supports full-speed (12 Mbps) and high-speed (480 Mbps) modes, but does not support
low-speed mode (1.5 Mbps). The FX2 interface to the Virtex-5 FPGA is a programmable state machine that supports 8- or 16bit parallel data transfers. This interface is called the General Programmable Interface (GPIF). The GPIF is controlled by
Waveform Descriptors that are created with the Cypress “GPIFTool” utility and downloaded to the FX2 over the USB cable.
The GPIF descriptors are stored in internal RAM and are loaded by the firmware during initialization. The GPIF interface is
made up of the signals in the following table, which are connected to Virtex-5 FPGA. The USB FX2 device can also be used in
a slave mode where the FPGA accesses the FX2 like a FIFO. For more information about the FX2 modes of operation, see the
“EZ-USB FX2 Technical Reference Manual” and the FX2 datasheet available on Cypress Semiconductor’s web site
(http://www.cypress.com).
Some of the additional GPIF pins are connected to the SelectMAP configuration port on the Virtex-5 FPGA. Avnet has
designed a Windows utility program that can utilize this connection to the SelectMAP port to update the FPGA configuration
over the USB port. The additional pins used for the SelectMAP interface are shaded in the table. The Virtex-5 FXT PCI
Express board should be used with version 3.2 or later of the “ADS USB Utility”. This program can be downloaded from the
Design Resource Center (www.em.avnet.com/drc). The USB Utility only supports bit files generated with CCLK as the start-up
clock.
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The Cypress USB 16-bit data bus is muxed with the data bus from the configuration PROM so that either the configuration
PROM or the USB device can be used to configure the Virtex-5 FPGA. The MUX OE and SEL pins are controlled by a decoder
circuit that will auto detect when USB-FPGA configuration is going to begin allowing the proper data bus to be connected to the
Virtex-5 FPGA. After the USB device has finished configuring the FPGA the configuration PROM data bus is the default bus
connected to the FPGA via the MUX.
NOTE: If it is desired to configure the FPGA via the USB port a jumper must be placed on JP14 to enable the Cypress
device to drive the M0-M2 configuration mode pins on the Virtex-5 FPGA.
FX2 Signal
CTL[0]
CTL[1]
CTL[2]
CTL[3]
CTL[4]
CTL[5]
RDY[0]
RDY[1]
RDY[2]
RDY[3]
RDY[4]
FD[0]
FD[1]
FD[2]
FD[3]
FD[4]
FD[5]
FD[6]
FD[7]
FD[8]
FD[9]
FD[10]
FD[11]
FD[12]
FD[13]
FD[14]
FD[15]
GPIFADR[0]
GPIFADR[1]
GPIFADR[2]
GPIFADR[3]
GPIFADR[4]
GPIFADR[5]
GPIFADR[6]
GPIFADR[7]
IFCLK
Net Name
USB_CTL0
USB_CTL1
USB_CTL2
CTL3_PROG#
CTL4_CS#
CTL5_RDWR#
USB_RDY0
USB_RDY1
FPGA_BUSY
FPGA_DONE
FPGA_INIT#
USB_FD0 (D0)
USB_FD1 (D1)
USB_FD2 (D2)
USB_FD3 (D3)
USB_FD4 (D4)
USB_FD5 (D5)
USB_FD6 (D6)
USB_FD7 (D7)
USB_FD8 (D8)
USB_FD9 (D9)
USB_FD10 (D10)
USB_FD11 (D11)
USB_FD12 (D12)
USB_FD13 (D13)
USB_FD14 (D14)
USB_FD15 (D15)
USB_PC0
FPGA_M2
FPGA_M1
FPGA_M0
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK
USB_IFCLK
PA0/INT0#
PA1/INT1#
PA2/SLOE
PA3/WU2
PA4/FIFOADR0
PA5/FIFOADR1
PA6/PKTEND
PA7/SLCS#
RESET#
USB_INT0#
USB_INT1#
USB_SLOE
USB_WU2
USB_FA0
USB_FA1
USB_PEND
USB_SLCS#
USB_RST#
Virtex-5 pin#
F9
F8
F10
E9
E8
AD19
AE19
AE17
AF16
AD20
AE21
AE16
AF15
AH13
AH14
AH19
AH20
AG13
AH12
AH22
AG22
L19
G10
G8
H8
D11
D10
K11
J11
D12
H9
Description
Control output or Slave-FIFO Flag A (Level#)
Control output or Slave-FIFO Flag B (Full#)
Control output or Slave-FIFO Flag C (Empty#)
Output enable for FPGA_PROG# driver
SelectMAP chip select when USB_CFG_EN# low
SelectMAP write enable when USB_CFG_EN# low
Sample-able ready inputs
SelectMAP port busy indication
FPGA configuration DONE pin
FPGA initialization pin
Bidirectional FIFO data bus (also SelectMAP data)
Bidirectional FIFO data bus (also SelectMAP data)
Optional FPGA_CCLK out – see JT4 selection
SelectMAP port mode - M2
SelectMAP port mode - M1
SelectMAP port mode - M0
Optional JTAG interface – TDI (install RP1)
Optional JTAG interface – TDO (install RP1)
Optional JTAG interface – TMS (install RP1)
Optional JTAG interface – TCK (install RP1)
Interface clock, optional FPGA_CCLK (JT4)
Port A I/O or active-low interrupt 0
Port A I/O or active-low interrupt 1
Port A I/O or slave-FIFO output enable
Port A I/O or alternate wake-up pin
Port A I/O or slave-FIFO address select 0
Port A I/O or slave-FIFO address select 1
Port A I/O or slave-FIFO packet end
Port A I/O or slave-FIFO enable
USB device active-low reset
Table 29 - USB Interface FPGA Pin-out
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2.5.3
RS232
The RS232 transceiver is a 3222 available from Harris/Intersil (ICL3222CA) and Analog Devices (ADM3222). This transceiver
operates at 3.3V with an internal charge pump to create the RS232 compatible output levels. This level converter supports two
channels. The primary channel is used for transmit and receive data (TXD and RXD). The secondary channel may be
connected to the FPGA by installing jumpers on “J13” and “J10” for use as CTS and RTS signals. The RS232 console
interface is brought out on the DB9 connector labeled “P1”. The Virtex-5 FXT PCI Express Board supports straight-through
serial cables.
2 (RD)
TXD
Din1
Dout1
RXD
Rout1
Virtex-5
FF1136
RS232
Transceiver
Rin1
DB9
Connector
3 (TD)
J13
RTS
CTS
Dout2
7 ( RTS)
Din2
Rout2
Rin2
8 ( CTS)
J10
P1
Figure 16 - RS232 Interface
A male-to-female serial cable should be used to plug “P1” into a standard PC serial port (male DB9). The following tables show
the FPGA pin-out and jumper settings for the RS232 interface.
Net Name
RS232_RXD
RS232_TXD
RS232_RTS
RS232_CTS
Description
Received Data, RD
Transmit Data, TD
Request To Send, RTS
Clear To Send, CTS
Virtex-5 Pin #
C14
C15
A14
A16
Table 30 - RS232 Signals
2.6
User Switches
Four momentary closure push buttons have been installed on the board and attached to the FPGA. These buttons can be
programmed by the user and are ideal for logic reset and similar functions. Pull down resistors hold the signals low until the
switch closure pulls them high (active high signals).
Net Name
SWITCH_PB1
SWITCH_PB2
SWITCH_PB3
SWITCH_PB4
Reference
SW5
SW6
SW7
SW8
Virtex-5 Pin #
D14
E14
F14
F15
Table 31 - Push Button Pin Assignments
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An eight-position dipswitch (SPST) has been installed on the board and attached to the FPGA. These switches provide digital
inputs to user logic as needed. The signals are pulled low by 1K ohm resistors when the switch is open and tied high to 1.8V
when closed as shown in the following table.
Net Name
Reference
SWITCH0
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
SW9 – 1
SW9 – 2
SW9 – 3
SW9 – 4
SW9 – 5
SW9 – 6
SW9 – 7
SW9 – 8
Voltage when
closed
Virtex-5 Pin#
1.8V
C20
B20
B21
A21
C19
C18
C22
B22
Table 32 - DIP Switch Pin Assignments
2.7
User LEDs
Eight discrete LEDs are installed on the board and can be used to display the status of the internal logic. These LEDs are
attached as shown below and are lit by forcing the associated FPGA I/O pin to a logic ‘1’ and are off when the pin is either low
(0) or not driven.
Net Name
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
Reference
D1
D2
D3
D4
D5
D6
D7
D8
Virtex-5 Pin#
B16
B15
AN34
AN33
AN32
AP32
AG15
AG16
Table 33 - LED Pin Assignments
2.8
Configuration
The Virtex-5 FXT PCI Express Board supports several methods of configuring the FPGA. The possible configuration sources
include Boundary-scan (JTAG cable), Byte Peripheral Interface PROM, the Cypress USB device or the System ACE Module
(SAM) header. The blue LED labeled “DONE” on the board illuminates to indicate when the FPGA has been successfully
configured.
2.8.1
Configuration Modes
Upon power-up the FPGA will be enabled in a configuration mode defined by the jumpers on “JP3”. The default configuration
mode is Boundary Scan (JTAG) mode when no jumpers are installed which will allow the FPGA to be configured from the
JTAG programming cable. The following table shows the various configuration modes that are supported:
Table 34 – Setting the Configuration Mode “JP3”
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The jumpers must be set for Boundary-scan when using a System ACE Module to configure the FPGA. The mode pins are
pulled up by weak resistors so that the Cypress USB device can override the mode selection to configure the FPGA in Slave
SelectMAP mode. See Section 2.5.2 for more information on using the Cypress device to configure the FPGA.
2.8.2
JTAG Chain
The Virtex-5 FXT PCI Express Board has two devices in the JTAG chain, the Virtex-5 FXT FPGA and the System Ace header.
The following figure shows a high-level block diagram of the JTAG Chain on the development board.
Figure 17 - JTAG Chain on the Virtex-5 PCI Express Board
Programming the Virtex-5 FPGA via Boundary-scan mode requires a JTAG download cable (not included in the kit). The
Virtex-5 FXT PCI Express Board has a single connector to support the ribbon cable connection of the Parallel Cable IV and
Platform Cable USB. The connector is labeled “JP3”. For more information about JTAG download cables, perform a search on
the Xilinx web page http://www.xilinx.com using the key words “Programming Cables”. When using the flying leads connection
of the Parallel Cable III, connect the leads to SAM header as indicated in the following table.
Signal Name
TDO
TMS
TDI
VCC
GND
TCK
JP8 pin
3
5
7
2
4
10
Table 35 - Flying Lead JTAG Header
2.8.3
Byte Peripheral Interface (BPI)
The Virtex-5 FXT PCI Express Board has an onboard configuration PROM that utilizes the BPI interface for FPGA
configuration. The PROM can be programmed with new configuration data using a JTAG download cable and the iMPACT
software that comes with the Xilinx ISE tools. The iMPACT software indirectly programs the Flash by downloading a bitstream
to the FPGA that facilitates communication with the Flash device when a program operation is selected. The Flash must be
erased before programming a new configuration file into the device. The PROM File Formatter in iMPACT must be used to
convert the user bitstream(s) into a file format supported by the BPI Flash programmer (ex. MCS file). After the Flash has been
re-programmed, pressing the pushbutton labeled “SW4” will reconfigure the FPGA with the new configuration data stored in
the Flash device (assuming JP3 is set for BPI mode). Late versions of the iMPACT tool will force the reconfiguration of the
FPGA immediately after programming if the option is selected.
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.......
JTAG Configuration Port
(includes VCC and GND for
stand-alone operation)
JTAG Test Port
(inludes VCC and GND)
.......
2.8.4
System ACE Module Connector
The Virtex-5 FXT PCI Express Board provides support for the Avnet Memec System ACE Module (SAM) via the 50-pin
connector labeled “JP8” on the board. The SAM can be used to configure the FPGA or to provide bulk Flash to the logic
design. The Avnet Memec System ACE module (DS-KIT-SYSTEMACE) is sold separately. The figure below shows the
System ACE Module and its interface to the Virtex-5 FXT PCI Express Board.
CF Connector
SystemACE™
Controller
5050-pin Connector
(connects to a 5050-pin 0.1" square post header on the main board)
board )
4
JTAG
Configuration Port
28
2
10
6
MPU
Interface
Reset &
Clock
Power &
Ground
Misc
Signals
Figure 18 - SAM Interface (50-pin header)
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The following table shows the System ACE ports that are accessible over the SAM header. The majority of the pins on this
header may be used as general purpose I/O when not using a System ACE Module. The Virtex-5 pin numbers are provided for
these general purpose pins.
Virtex-5 Pin#
AG32
AE33
AF34
V32
V33
W34
V34
Y33
AA33
AA34
Y34
AJ34
AD32
AK34
AK33
-
System ACE
Signal Name
3.3V
TDO
TMS
TDI
PROGRAMn
GND
OEn
MPA0
MPA2
2.5V
MPD00
MPD02
MPD04
MPD06
MPD08
MPD10
MPD12
MPD14
MPA4
MPA6
IRQ
RESETn
DONE
CCLK
GND
SAM Connector Pin #
(JP9)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
System ACE
Signal Name
3.3V
GND
CLOCK
GND
TCK
GND
INITn
WEn
MPA1
MPA3
2.5V
MPD01
MPD03
MPD05
MPD07
MPD09
MPD11
MPD13
MPD15
MPA5
GND
CEn
BRDY
BITSTREAM
NC
Virtex-5 Pin#
H14
AE32
AE34
AH34
Y32
W32
AC34
AD34
AC32
AB32
AC33
AB33
AF33
AG33
AH33
-
Table 36 - SAM Interface Signals
2.9
Power
The Virtex-5 FXT PCI Express Board power is developed from a +5V input provided by the furnished power supply or derived
from the +12V rail of a PCI Express bus via an Emerson LGA10C-00SADJJ power module. The +1.8V, +2.5V, and +1.0V
power rails are developed by Emerson LGA06C-00SADJJ power modules; these modules are capable of furnishing up to 6A
each. The +3.3V power is developed from an Emerson LGA20C-00SADJJ power module capable of furnishing up to 20A. The
DDR devices have a dedicated TI TPS51116 regulator that produce both the main 1.8V power and the 0.9V termination power.
In stand-alone mode the board is connected to the external power supply via the “J21” barrel socket connector (included 6.5A
power supply), or the PC hard-drive power connector “J29” (optional power connection). The current requirements for the
board are application specific. It should be noted that, per the PCI Express specification, maximum power available to a single
x8 PCI Express add-in card is 25 watts (5A @+5V). For stand-alone applications, the fuse may be removed from the fuse
holder “F1”; for PCI applications the fuse must be installed in the fuse holder. The figure below shows a high-level block
diagram of the main power supplies on the development board.
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Figure 19 - Board Power Supply
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2.9.1
FPGA I/O Voltage (VCCO)
FPGA banks 0, 1, 2, 5, 12, 13, and 20 are powered at VCCO = +3.3V and banks 11, 15, 17, 19, 21, and 23 are powered at
VCCO = +1.8V. There are six selectable voltage rails, four to service the I/O signals from the two EXP connectors, and another
two to service banks 3 and 4 where the EXP clocks are connected. These selectable voltage rails may be powered at +2.5V
or +3.3V using the jumpers labeled “JP5”, and “JP6”.
Bank #
0
1
2
3
4
5
6
11
12
13
15
17
18
19
20
21
22
23
25
1.8V
3.3V
2.5V/3.3V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Selectable
Rail
VCCO_EXP1
VCCO_EXP2
VCCO_EXP2
VCCO_EXP1
VCCO_EXP1
VCCO_EXP2
Table 37 – I/O Bank Voltages
2.9.2
FPGA Reference Voltage (Vref)
The Virtex-5 FXT PCI Express Board provides the reference voltage of +0.9V to the FPGA banks connected to the DDR2
memory interfaces. Those banks are: 11, 15, 17, 19 and 21.
2.9.3
GTX Voltage Regulators (AVCC, AVCCPLL, VTTRX, VTTTX, VTTRXC)
The Virtex-5 FXT PCI Express Board provides point-of-load regulation for the GTX supplies with high-precision, low drop-out
linear regulators from Texas Instruments. The TPS54xxx family of LDO regulators provide up to 6.0 amps of current. The
ultra-low input voltage requirement minimizes the voltage drop across the regulator saving the added cost of thermal solutions
in most applications. The adjustable output range, down to 0.9V, makes the TPS54xxx series switchers a good fit for the low
voltage GTX supplies. The small 4.5mm x 9.6mm PWP packages are ideal for space limited applications like PCI form-factor
add-in cards. The following figure shows a high-level block diagram of the GTX power supplies.
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Figure 20 - GTX Voltage Regulators
The GTX supply pins require 1.0 Volt or 1.2 Volts depending on the pin type. The adjustable TPS54xxx regulators use an
external voltage divider to set the output voltage. A single TPS54610 regulator supplies the MGTAVCC pins of every
GTX_Dual tile. This regulator also supplies the MGTAVTTRXC pin. The remaining supply pins are separated into two power
rails based on application. The “GTX_1.2V_PCIe” rail supplies the MGTAVCCPLL, MGTVTTTX and MGTVTTRX pins for the
four GTX_Dual tiles used for the PCI Express interface. Likewise the “GTX_1.2V_GP” rail supplies the same type of pins for
the four remaining tiles consisting of the SFP, SATA, EXP and 10 Gb/s Media interfaces. A single, adjustable TPS73701 LDO
is used to supply the MGTAVTTRXC pin. The following table contains estimated current utilization for the GTX rails based on
the Virtex-5 datasheet.
Net Name
GTX_1.2V_xxx
GTX_1.0V
MGT Rails
MGTVTTTX
MGTVTTRX
MGTAVTTRXC
MGTAVCC
MGTAVCCPLL
Current Consumption per tile
Min
Typical
Max
51.9mA
-
-
30.2mA
0.1mA
62.5mA
30.5mA
Table 38 - Typical Current Measurements per MGT Tile
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2.10 Thermal Management
The Virtex-5 FXT FPGA on the development board requires a heat sink to keep the junction temperate within the operating
limits of the device. The amount of power that needs to be dissipated is design dependent. The main contributors to the overall
power are utilization, frequency and the number of active RocketIO transceivers. The board includes a passive heat sink that is
adequate for moderate logic utilization and moderate frequency designs in ambient air flow. Forced air flow may be required to
support designs containing more than eight active RocketIO transceivers. Even with forced air flow the passive heat sink may
not be capable of dissipating the power in all applications. For designs with higher utilization, high-frequency blocks and/or
more than eight active transceivers, an active heat sink may be required. The Virtex-5 FXT PCI Express provides a
placeholder on the board for a 5 volt fan connector (J28) or a 12V fan connector (J22). The following sections provide details
on the passive heat sink included with the kit and the active heat sinks supported by the board (purchased separately).
2.10.1 Passive Heat Sink
The Virtex-5 FXT PCI Express Board includes a 6 mm passive heat sink with push-pin attachment to the Virtex-5 FPGA. This
heat sink is part of the Aavid Thermalloy product offering for Ball Grid Arrays (BGA). More information is available on Aavid’s
web site: http://www.aavidthermalloy.com/products/bga/index.shtml. A 37.4 mm x 37.4 mm heat sink is used to fit the 35 mm
FF1136 package. The push-pin mounting holes in the board support the industry standard hole pattern shown below.
Figure 21 - Heat Sink Mounting-Hole Pattern
The part number for the Aavid Thermalloy heat sink is 372924M02000G. The 6 mm height provides enough vertical clearance
to install an EXP daughter module in the board-to-board connectors straddling the Virtex-5 FPGA. The forced air flow should
be directed across the length of the board if used on a bench top. Standard PC cases usually pull air across the PCI cards in
this direction.
2.10.2 Active Heat Sink Support
The Virtex-5 FXT PCI Express Board supports active heat sinks with both 5V and 12V power connectors and the industry
standard push-pin hole pattern. The Virtex-5 FXT PCI Express board supports up to a 40 mm x 40 mm heat sink and/or heat
sink fan. The 3-pin power connector labeled “J28” is used for 5V fans with Molex mating series 2695 and 40 mm of lead length.
The 2-pin power connector labeled “J22” is used for 12V fans with Molex mating series. The following table provides Aavid
Thermalloy part numbers for recommended active heat sinks (purchased separately).
Part
Number
11-5602-45
11-5602-51
Fan
Voltage
5V
12V
Height
15.0 mm
11.5 mm
Lead
Length
127 mm
40 mm
Thermal
Resistance
3.40 C/W
3.70 C/W
Board
Connector
J28
J22
Table 39 - Recommended Active Heat Sinks
2.11 Expansion Connectors
The Virtex-5 FXT PCI Express board provides expansion capabilities for customized user application daughter cards and
interfaces over two EXP expansion connectors. The EXP expansion connectors on the board can support two half-card EXP
modules, or a single dual slot EXP module. Both off-the-shelf EXP modules and user-developed modules can easily be
plugged onto the Virtex-5 FXT PCI Express board to add features and functions to the backend application of the main board.
For more information, view the EXP specification at www.em.avnet.com/exp.
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2.11.1 EXP Interface
The EXP specification defines a 132-pin connector, with 24 power, 24 grounds, and 84 user I/Os. The standard EXP
configuration implemented on the Virtex-5 FXT PCI Express board uses two connectors (Samtec part number QTE-060-09-FD-A) in a dual slot EXP configuration, with a total of 164* user I/Os. Using a jumper, you can set the voltage levels for the EXP
user I/O to either 2.5V or 3.3V. As shown in the following figure, “JP5” sets the I/O voltage for the EXP connector labeled “JX1”
while “JP6” sets the I/O voltage for the EXP connector labeled “JX2”, by setting the VCCO voltage for the banks of the FPGA
that connect to the EXP I/O.
Figure 22 - EXP I/O Voltage Settings
The EXP specification defines four user signal types: Single Ended I/O, Differential I/O, Differential and Single Ended Clock
Inputs, and Differential and Single Ended Clock Outputs. Because the FPGA I/Os can be configured for either single-ended or
differential use, the differential I/Os defined in the EXP specification can serve a dual role. All the differential I/O signals can be
configured as either differential pairs or single-ended signals, as required by the end application. In providing differential
signaling, higher performance LVDS interfaces can be implemented between the baseboard and EXP module. Connection to
high speed A/Ds, D/As, and flat panel displays are possible with this signaling configuration. Applications that require singleended signals only can use each differential pair as two single-ended signals.
Net Names
EXPx_SE_IO
EXPx_SE_CLK_IN
EXPx_SE_CLK_OUT
EXPx_DIFF_p/n
EXPx_DIFF_CLK_IN_p/n
EXPx_DIFF_CLK_OUT_p/n
Total
Signal Description
Single-ended I/O
Single-ended clock input
Single-ended clock output
Differential I/O pairs
Differential clock input pair, global
Differential clock output pair
JX1
34
1
1
20
1
1
80
JX2
34
1
1
22
1
1
84
Total
68
2
2
42
2
2
164
Table 40 - EXP Connector Signals
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Since the Virtex-5 FXT FPGA supports regional clocking and GTX transceivers, the optional RCLK pair and MGT pairs defined
in version 1.3 of the EXP specification are utilized. The “EXPx_RCLK_DIFF_p/n” differential pairs on both “JX1” and “JX2” are
connected to clock-capable pins to support regional clocking applications. Since these regional clock pairs can also be used as
general purpose differential I/O pairs, they are counted as “Differential I/O pairs” in the previous table.
The “EXPx_MGT_RX_DIFF_p/n” pair and “EXPx_MGT_TX_DIFF_p/n” pair are connected to MGT124 to support high-speed,
serial communication to the daughter card(s). These MGT pairs are connected to “JX1” and “JX2” pins “54 & 56” and “53 & 55”
respectively. These pins can only be used by daughter cards supporting the RocketIO transceiver link. This reduces the
number of differential I/O pairs from 22 down to 20 for the EXP connectors labeled “JX1” and “JX2”. The alternate function nets
defined in the EXP v1.3 specification that are supported by the Virtex-5 FXT PCI Express board are shown in the following
table.
Alternate Function Nets
Signal Description
EXPx_RCLK_DIFF_p/n10
EXPx_MGT_RX_DIFF_p/n20
EXPx_MGT_TX_DIFF_p/n21
Differential clock input pair, regional
GTX transceiver, receive pair
GTX transceiver, transmit pair
Supported?
JX1
JX2
Yes
Yes
Yes
Yes
Yes
Yes
Table 41 - EXP v1.3 Alternate Function Pins
The Virtex-5 FPGA user I/O pins that connect to the two EXP connectors are shown in the following table. The Samtec QTE
connector plugs on the Virtex-5 FXT PCI Express board (part number: QTE-060-09-F-D-A) mate with the Samtec QSE highperformance receptacles (part number: QSE-060-01-F-D-A), located on the daughter card. Samtec also provides several highperformance ribbon cables that will mate to the “JX1” and “JX2” connectors.
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Virtex-5
Pin#
AN14
AB10
AN13
AA8
AP12
AC8
AM12
AC10
AE8
AD10
AK11
AF8
AK8
AF9
H17
H18
AF11
AE11
A9
A8
AK7
AK6
AJ7
AJ6
AG8
AH8
AH7
AG7
AH5
AG6
AG5
AF5
W6
Y6
AA6
Y7
AE7
AF6
AA5
AB5
AC4
AC5
-
Net Name
EXP1_SE_IO_0
EXP1_SE_IO_2
2.5V
EXP1_SE_IO_4
EXP1_SE_IO_6
2.5V
EXP1_SE_IO_8
EXP1_SE_IO_10
2.5V
EXP1_SE_IO_12
EXP1_SE_IO_14
2.5V
EXP1_SE_IO_16
EXP1_SE_IO_18
2.5V
EXP1_SE_IO_20
EXP1_SE_IO_22
2.5V
EXP1_SE_IO_24
EXP1_SE_IO_26
EXP1_DIFF_CLK_IN_p
EXP1_DIFF_CLK_IN_n
GND
EXP1_SE_IO_30
EXP1_SE_IO_31
GND
EXP1_MGT_RX_DIFF_p
EXP1_MGT_RX_DIFF_n
GND
EXP1_DIFF_p18
EXP1_DIFF_n18
GND
EXP1_DIFF_p16
EXP1_DIFF_n16
GND
EXP1_DIFF_CLK_OUT_p
EXP1_DIFF_CLK_OUT_n
GND
EXP1_DIFF_p14
EXP1_DIFF_n14
EXP1_DIFF_p12
EXP1_DIFF_n12
3.3V
EXP1_RCLK_IN_p
EXP1_RCLK_IN_n
3.3V
EXP1_DIFF_p8
EXP1_DIFF_n8
3.3V
EXP1_DIFF_p6
EXP1_DIFF_n6
3.3V
EXP1_DIFF_p4
EXP1_DIFF_n4
3.3V
EXP1_DIFF_p2
EXP1_DIFF_n2
3.3V
EXP1_DIFF_p0
EXP1_DIFF_n0
GND
GND
GND
GND
GND
GND
EXP Connector Pin #
(JX1)
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
82
81
84
83
86
85
88
87
90
89
92
91
94
93
96
95
98
97
100
99
102
101
104
103
106
105
108
107
110
109
112
111
114
113
116
115
118
117
120
119
122
121
124
123
126
125
128
127
130
129
132
131
Net Name
EXP1_SE_IO_1
EXP1_SE_IO_3
2.5V
EXP1_SE_IO_5
EXP1_SE_IO_7
2.5V
EXP1_SE_IO_9
EXP1_SE_IO_11
2.5V
EXP1_SE_IO_13
EXP1_SE_IO_15
2.5V
EXP1_SE_IO_17
EXP1_SE_IO_19
2.5V
EXP1_SE_IO_21
EXP1_SE_IO_23
2.5V
EXP1_SE_IO_25
EXP1_SE_IO_27
EXP1_SE_IO_28
EXP1_SE_CLK_IN
GND
EXP1_SE_IO_29
EXP1_SE_CLK_OUT
GND
EXP1_MGT_TX_DIFF_p
EXP1_MGT_TX_DIFF_n
GND
EXP1_SE_IO_32
EXP1_SE_IO_33
GND
EXP1_DIFF_p19
EXP1_DIFF_n19
GND
EXP1_DIFF_p17
EXP1_DIFF_n17
GND
EXP1_DIFF_p15
EXP1_DIFF_n15
EXP1_DIFF_p13
EXP1_DIFF_n13
3.3V
EXP1_DIFF_p11
EXP1_DIFF_n11
3.3V
EXP1_DIFF_p9
EXP1_DIFF_n9
3.3V
EXP1_DIFF_p7
EXP1_DIFF_n7
3.3V
EXP1_DIFF_p5
EXP1_DIFF_n5
3.3V
EXP1_DIFF_p3
EXP1_DIFF_n3
3.3V
EXP1_DIFF_p1
EXP1_DIFF_n1
GND
GND
GND
GND
GND
GND
Virtex-5
Pin#
AP14
AA10
AM13
AA9
AN12
AB8
AM11
AC9
AD9
AD11
AJ11
AE9
AK9
AF10
AJ9
K17
AJ10
V9
B10
B9
AH9
AH10
AG10
AG11
V8
U8
W10
W9
Y11
W11
W7
V7
Y8
Y9
AB6
AB7
AD4
AD5
AC7
AD7
AD6
AE6
-
Table 42 - EXP Connector "JX1" Pin-out
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Virtex-5
Pin#
AH24
AJ24
AH23
AK24
AK23
AL23
AJ22
AK22
AK21
AL21
AJ19
AK19
AL20
AL19
AG21
AG20
AK18
AL18
A6
A7
AN30
AM30
AN22
AM22
AN15
AP15
AN23
AM23
AL27
AL28
AP26
AP25
AN25
AM25
AP27
AN27
AN24
AP24
AP22
AP21
AL29
AL30
-
Net Name
EXP2_SE_IO_0
EXP2_SE_IO_2
2.5V
EXP2_SE_IO_4
EXP2_SE_IO_6
2.5V
EXP2_SE_IO_8
EXP2_SE_IO_10
2.5V
EXP2_SE_IO_12
EXP2_SE_IO_14
2.5V
EXP2_SE_IO_16
EXP2_SE_IO_18
2.5V
EXP2_SE_IO_20
EXP2_SE_IO_22
2.5V
EXP2_SE_IO_24
EXP2_SE_IO_26
EXP2_DIFF_CLK_IN_p
EXP2_DIFF_CLK_IN_n
GND
EXP2_SE_IO_30
EXP2_SE_IO_31
GND
EXP2_MGT_RX_DIFF_p
EXP2_MGT_RX_DIFF_n
GND
EXP2_DIFF_p18
EXP2_DIFF_n18
GND
EXP2_DIFF_p16
EXP2_DIFF_n16
GND
EXP2_DIFF_CLK_OUT_p
EXP2_DIFF_CLK_OUT_n
GND
EXP2_DIFF_p14
EXP2_DIFF_n14
EXP2_DIFF_p12
EXP2_DIFF_n12
3.3V
EXP2_RCLK_IN_p
EXP2_RCLK_IN_n
3.3V
EXP2_DIFF_p8
EXP2_DIFF_n8
3.3V
EXP2_DIFF_p6
EXP2_DIFF_n6
3.3V
EXP2_DIFF_p4
EXP2_DIFF_n4
3.3V
EXP2_DIFF_p2
EXP2_DIFF_n2
3.3V
EXP2_DIFF_p0
EXP2_DIFF_n0
GND
GND
GND
GND
GND
GND
EXP Connector Pin #
(JX2)
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
82
81
84
83
86
85
88
87
90
89
92
91
94
93
96
95
98
97
100
99
102
101
104
103
106
105
108
107
110
109
112
111
114
113
116
115
118
117
120
119
122
121
124
123
126
125
128
127
130
129
132
131
Net Name
EXP2_SE_IO_1
EXP2_SE_IO_3
2.5V
EXP2_SE_IO_5
EXP2_SE_IO_7
2.5V
EXP2_SE_IO_9
EXP2_SE_IO_11
2.5V
EXP2_SE_IO_13
EXP2_SE_IO_15
2.5V
EXP2_SE_IO_17
EXP2_SE_IO_19
2.5V
EXP2_SE_IO_21
EXP2_SE_IO_23
2.5V
EXP2_SE_IO_25
EXP2_SE_IO_27
EXP2_SE_IO_28
EXP2_SE_CLK_IN
GND
EXP2_SE_IO_29
EXP2_SE_CLK_OUT
GND
EXP2_MGT_TX_DIFF_p
EXP2_MGT_TX_DIFF_n
GND
EXP2_SE_IO_32
EXP2_SE_IO_33
GND
EXP2_DIFF_p19
EXP2_DIFF_n19
GND
EXP2_DIFF_p17
EXP2_DIFF_n17
GND
EXP2_DIFF_p15
EXP2_DIFF_n15
EXP2_DIFF_p13
EXP2_DIFF_n13
3.3V
EXP2_DIFF_p11
EXP2_DIFF_n11
3.3V
EXP2_DIFF_p9
EXP2_DIFF_n9
3.3V
EXP2_DIFF_p7
EXP2_DIFF_n7
3.3V
EXP2_DIFF_p5
EXP2_DIFF_n5
3.3V
EXP2_DIFF_p3
EXP2_DIFF_n3
3.3V
EXP2_DIFF_p1
EXP2_DIFF_n1
GND
GND
GND
GND
GND
GND
Virtex-5
Pin#
AJ15
AJ12
AK14
AJ14
AK12
AK13
AL13
AL14
AL15
AJ17
AM15
AL16
AM16
AK17
AK16
AH15
AJ16
AP19
B5
B6
AP16
AP17
AM17
AN17
AN18
AM18
AN20
AP20
AM21
AM20
AL25
AL24
AM31
AL31
AN28
AM28
AP29
AN29
AP30
AP31
AM26
AL26
-
Table 43 - EXP Connector "JX2" Pin-out
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3.0 Test Designs
This section describes the factory test design that is pre-programmed into the P30 Flash device as well as the Ethernet test provided on
the Design Resource Center (DRC) web site: www.em.avnet.com/drc. The factory test design is used to verify some of the functionality
of the board and may require additional test apparatus.
If the Flash device has been erased, the bit file containing the test design(s) is available on the Design Resource Center web site:
www.em.avnet.com/drc. The Flash can be re-programmed by using the Xilinx iMPACT software. The bit file will have to be converted
into an MCS file format using iMPACT.
The Ethernet and Factory test designs available on the DRC web site use a terminal session as the user interface. Using a straightthrough serial cable, connect the Virtex-5 FXT PCI Express Board to a PC. Open a terminal session and configure it for 19200 baud, 8
data bits, no parity, 1 stop bit and no flow control (19200-8-N-1-N).
3.1
Factory Test
The Factory Test verifies the electrical connectivity of the DDR2 SDRAM and Flash memory, and the user LEDs and switches.
The user can initiate the tests by typing ‘test <enter>’ in a terminal session configured as shown in Section 3.0 (19200-8-N-1N). Some of the tests require user inputs and observation (watching the LEDs and pressing the switches). The cumulative
results are displayed at the completion of test processes.
3.2
Ethernet Test
The Ethernet Test design provides the user with the ability to ping the Virtex-5 FXT PCI Express board to verify network
connectivity via the on-board National 10/100/1000 Mbps Ethernet PHY. The National PHY supports auto-MDIX mode, which
allows either a straight-through or a cross-over Ethernet cable to be used. The default IP address of the board is
172.16.158.147. To ping the board, plug an Ethernet cable into the RJ45 connector labeled “J23”. Then change the IP address
of the board to match the subnet of the PC or network it’s connected to using a terminal program configured as shown in
Section 3.0 (19200-8-N-1-N). At the prompt, type ‘i’ and then enter the new IP address for the board (first three fields must
match the IP address of the PC: MMM.MMM.MMM.xxx; the last field must be different). Use periods ‘.’ between fields and hit
the <enter> key when finished. Then open a command shell on the PC (Start Menu -> Run, cmd) and type ‘ping
MMM.MMM.MMM.xxx’. You should see four replies to the ping request.
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4.0 Revisions
V1.0
Initial release for production board (AES-XLX-V5-PCIe-PCB-B)
January 26, 2010
V1.1
Made correction to Table 43
June 1, 2011
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Appendix A
EXP Connector (JX2)
J12
EXP Connector (JX1)
J22
JP6
JP5
J20
J18
Debug
JP2
This section provides a description of the jumper settings for the Virtex-5 FXT PCI Express board. The board is ready to use
out of the box with the default jumper settings. The following figure depicts a map of the component side of the board with
Jumper/Header/Connector locations detailed. The jumper sites are colored pink below.
Figure 23 - Board Jumpers, Headers, Connectors
JP1 “MAX3674 I2C” – Gives the user access to the two MAX3674 clock synthesizers. The user can opt to program the
synthesizers via the I2C bus rather than using the DIP Switches. Default: Open.
JP3 “Configuration mode selection” – Use to select the configuration mode for the FPGA. Default: JP1 1-2, 5-6 (BPI). See
section 2.8.1 for more information.
JP4 “FLSH WP” – Flash Write-protect Enable, install a shunt to protect programmed data in the Flash memory. Default: JP14
1:2, read/write enabled (unprotected).
JP5 “EXP1_VCCO_SEL” – Vcco selectable voltage for Banks 3, 18 and 22. This selects the voltage level for the single ended
and differential signals on the EXP connector labeled “JX1”. The following figure shows JP5 in its default configuration
(VCCO_EXP1 = +2.5V).
Figure 24 – VCCO_EXP1 "JP5"
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JP6 “EXP2_VCCO_SEL” – Vcco selectable voltage for Banks 4, 6 and 25. This selects the voltage level for the single ended
and differential signals on the EXP connector labeled “JX2”. The following figure shows JP6 in its default configuration
(VCCO_EXP2 = +2.5V).
JP6
3.3V
1
2.5V
3
VCCO_EXP2
Figure 25 – VCCO_EXP2 “JP6”
JP7 “PCIe Lane Width” – Selects the number of PCI Express lanes to advertise to the host PC. A single jumper is installed to
connect the PRSNT1# pin to the PRSNT2# pin that corresponds to the desired lane width (x1, x4 or x8). This allows the user
to force fewer lanes to be used to target applications requiring less than 8 lanes. Default: JP5 5-6 (8 lanes).
J5 “USB RST” – USB Reset, install a shunt to hold the Cypress EZ-USB device in reset. When open, the USB reset line is
controlled by either an I/O pin of the FPGA or the push-button labeled “SW2”. Default: Open, the FPGA or push-button controls
the USB reset.
J9 “PC4/USB JTAG” – Ribbon cable connector used by the Xilinx Parallel Cable IV and Platform Cable USB.
J10 “R2IN” – Install a shunt to connect the second RX port of the RS232 transceiver to the DB9 connector for hardware
handshaking. This can be used to implement the ready to send (RTS) signal. Default: Open.
J11 “PROM FPGA_CCLK” – The onboard configuration PROM can be configured to be clocked from the FPGA’s CCLK (Slave
SelectMap). If this is desired a shunt must be placed on J11 to enable the FPGA_CCLK signal to clock the PROM. Default:
Open.
J12 “HSWAP” – Enables pull-ups on the Virtex-5 I/O pins during configuration. Install a jumper to enable the configuration pullups. Default: Open; pull-ups disabled.
J13 “T2OUT” – Install a shunt to connect the second TX port of the RS232 transceiver to the DB9 connector for hardware
handshaking. This can be used to implement the clear to send (CTS) signal. Default: Open.
J14 “USB_CONFIG” – Install a shunt on this jumper to enable the Cypress EZ-USB device to configure the FPGA. The ADS
USB Utility must be used to perform this operation. The jumper must be removed to return the board the other configuration
modes. Default Open.
J15 – USB Serial EEPROM write protect, install a shunt to protect programmed data. Default: Open, read/write enabled.
J16 – Test access to the 8051 serial port of the Cypress FX2 device.
J17 – USB Serial EEPROM address select, Default: Open.
J18 “P2 EN” – SFP Enable, install a shunt to enable a module plugged into the Small Form Pluggable (SFP) cage labeled “P1”
on the board. Default: Open (disabled).
J19 – Test access to the DXP and DXN pins of the FPGA.
J20 “P3 EN” – SFP Enable, install a shunt to enable a module plugged into the Small Form Pluggable (SFP) cage labeled “P2”
on the board. Default: Open (disabled).
J22 – +12V Active Heat sink power.
J28 “FAN” – +5V Active Heat sink power.
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