Computing Systems
Instructions: language of the
computer
claudio.talarico@mail.ewu.edu
1
Instructions
ƒ Instructions are the language of the machine
ƒ We’ll be work with the MIPS instruction set architecture
ƒ Design goals
ƒ find a language that make it easy to build the hardware
and the compiler
ƒ maximizing performance and minimizing cost
ƒ Stored-program concept
ƒ programs (= instructions and data) can be stored in
memory as numbers
continue
with “next”
instruction
ƒ Fetch & execute cycles
ƒ Fetch the instruction from memory and put it into a special
register (IR)
ƒ The bits in the register “control” the subsequent actions
required to execute the task specified by the instruction
2
1
Instruction set characteristic
ƒ Small
ƒ Few primitive instructions
ƒ Simple
ƒ Few instruction formats
ƒ Regular
ƒ Instructions can be handled in similar ways
ƒ Complete
ƒ support all kind of high level language instructions
ƒ Efficient
ƒ High level language instructions can be mapped efficiently
ƒ Compatible
3
Definition of the architecture
ƒ Data types
- bit, byte, word, unsigned integer, char, …
ƒ Operations
- arithmetic, logical, shift, flow control, data transfers, …
ƒ # of operands (3, 2, 1, or 0 operands)
- number of operands affect the instruction length
ƒ Registers
ƒ Memory organization
4
2
MIPS arithmetic
ƒ all arithmetic instructions have 3 operands
ƒ operands order is fixed (destination first)
C code
c = a+b
MIPS code
add $s0, $s1, $s2
Design principle: Simplicity favors regularity. Why ?
ƒ of course this complicate some things …
C code
f = (g + h) – (i + j)
MIPS code
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
5
Registers vs.
memory
Control
Input
Memory
Datapath
Output
Processor
ƒ Arithmetic operands must be registers,
- only 32 registers provided
- each register is 32 bits (word)
I/O
Absolute truth ?
Design Principle: Smaller is faster. Why ?
ƒ Compiler associates variables with registers, but …
ƒ What about programs with lots of variable or complex data
structures ?
ƒ Only a small amount of data can be kept in the computer’s registers, the
rest is kept in memory
ƒ We’ll need instructions that transfer data between memory and registers
6
3
Memory organization
ƒ Viewed as a large, single-dimension array, with an address.
ƒ A memory address is an index into the array
ƒ "Byte addressing" means that the index points to a byte of memory
0
1
2
3
4
5
6
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
...
7
Memory organization
ƒ Bytes are nice, but most data items use larger "words"
ƒ For MIPS, a memory word is 32 bits wide (= 4 bytes)
ƒ 232 bytes with byte addresses from 0 to 232 - 1
ƒ 230 words with byte addresses 0, 4, 8, ... 230 – 4
ƒ Words are aligned (alignment restriction)
ƒ words start at addresses that are multiple of 4
ƒ what are the least 2 significant bits of a word address?
8
4
Bytes order within a word
ƒ Which byte is first and which is last ?
ƒ There are two choices
ƒ Least significant byte is the at rightmost end (= little end)
ƒ Least significant byte is the at leftmost end (= big end)
ƒ MIPS uses Big Endian
0
4
3
7
2
6
1
5
0
4
Little Endian
0
4
0
4
1
5
2
6
3
7
Big Endian
9
MIPS data transfer instructions
ƒ load (it copies data from memory to a register)
ƒ store (copies data from a register to memory)
ƒ Memory address for load and store has two parts
ƒ A register whose contents is known (called base register or
index register)
ƒ An offset to be added to the base register content
ƒ This way the address is 32 bits
ƒ The offset can be positive or negative (2’s complement)
C code
MIPS code
lw $t0, 32($s3)
A[12] = h + A[8] add $t0, $s2, $t0
sw $t0, 48($s3)
Meaning
$t0 = Memory[$s3 + 32]
$t0 = $s2 + $t0
Memory[$s3 + 48] = $t0
10
5
Machine language
ƒ MIPS assembly instructions are translated into machine
instructions (“binary numbers”)
ƒ Instructions, like registers and words of data, are also 32
bits long
ƒ Example: add $t1, $s1, $s2
ƒ registers are represented as numbers:
$t1=9, $s1=17, $s2=18, …
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
ƒ The format above is called R-format (for register)
ƒ Can you guess what the field names stand for?
11
Machine language
ƒ Consider the load-word and store-word instructions
ƒ We must specify two registers and a constant (=immediate operand)
ƒ Regularity principle would suggest to use for the constant one of the
5-bit fields
ƒ Problem: the constant would be limited to only 32 !!!)
ƒ Solution: we introduce a new format called I-type (for immediate)
ƒ
The 16 bit number is in 2’s complement form
6 bits
5 bits
5 bits
16 bits
Design principle: good design demands good compromises
12
6
Examples
(op)
lw
sw
(op)
(rs)
$s2
$s3
(rs)
(rt)
$t0
$t0
(rt)
13
MIPS logical operations
Logical operation
Example
Meaning
shift left logical
sll $s1, $s2, 10
$s1 = $s2 << 10
srl $s1, $s2, 10
$s1 = $s2 >> 10
bit-by-bit and
and $s1, $s2, $s3
$s1 = $s2 & $s3
bit-by-bit or
or $s1, $s2, $s3
$s1 = $s2 | $s3
bit-by-bit nor
nor $s1, $s2, $s3
$s1 = ~ ($s2 | $s3)
shift right logical
The above instructions are all R-type
14
7
Example
ƒ sll $s1, $s2, 10
0
op
0
18
rt
17
rd
10
shamt
0
func
19
rt
17
rd
10
shamt
2
func
ƒ srl $s1, $s3, 10
0
op
0
15
Control flow
ƒ Decision making instructions
ƒ alter the program control flow,
ƒ i.e., change the "next" instruction to be executed
ƒ MIPS conditional branch instructions:
ƒ bne $t0, $t1, Label
ƒ beq $t0, $t1, Label
C code
if (i==j) h=i+j;
MIPS code
bne $s3, $s4, Label
add $s5, $s3, $s4
Label: …
16
8
Control flow
ƒ MIPS unconditional branch instruction (jump)
ƒ j Label
C code
if (i==j) f=g+h; else f=g-h
MIPS code
bne $t0, $t1, Else
add $s5, $s3, $s4
j Exit
Else: sub $s5, $s3, $s4
Exit: …
Can you build a
simple for loop?
17
Control flow
ƒ We have: beq (test for equality) and bne (test for inequality)
ƒ But, sometime is useful to see if a variable is less than
another one (branch-less-than)
ƒ MIPS provides the instruction set-on-less-than (slt)
ƒ The format is R-type
Meaning
MIPS code
if (s1<s2) t0=1; else t0=0
slt $t0, $s1, $s2
18
9
Control flow
ƒ Case switch statement
ƒ can be implemented as a chain of if-then-else
statements
ƒ or more efficiently as a table of addresses
ƒ MIPS provides a jump register instruction (jr)
ƒ It is an unconditional jump to the address specified in
a register
ƒ Example: jr $s0
19
Control flow – Instruction formats
ƒ slt and jr are R-format
slt $s1, $s2, $s3
0
op
18
rs
19
rt
17
rd
0
shamt
42
func
0
0
8
func
jr $s1
0
op
17
rs
0
20
10
Control flow – Instruction formats
ƒ beq and bne are I-format instructions
beq $s1, $s2, 100
4
op
17
rs
18
rt
25
16-bit number
ƒ The 16-bit number is in 2’s complement form
ƒ The 16-bit number specifies the # of instructions to be
skipped
ƒ Most branches are local [Principle of locality]
ƒ Next memory address = PC + (16-bit number x 4)
21
Control flow – Instruction formats
ƒ The unconditional jump instruction requires a new instruction format
(J-format)
ƒ Example: j 10000
2
op
2500
26-bit number
ƒ The address of the next instruction is obtained by concatenating
the 4 upper bits of the PC with the 26-bit address shifted left 2 bits
ƒ Next memory address = {PC[31:28], INS[25:0], 2’b00}
ƒ Address boundaries of 256 MB = (228)
22
11
MIPS Registers convention
Name Register number
$zero
0
$v0-$v1
2-3
$a0-$a3
4-7
$t0-$t7
8-15
$s0-$s7
16-23
$t8-$t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31
Usage
the constant value 0
values for results and expression evaluation
arguments
temporaries
saved
more temporaries
global pointer
stack pointer
frame pointer
return address
Register 1 ($at) reserved for assembler, 26-27 ($k0-$k1) for operating system
23
Constants
ƒ Small constant operands occur quite frequently in
programs (50% of operands)
ƒ By including constants inside instructions, execution
become much faster than if constants were loaded from
memory
w/o immediate instruction
lw $t0, AddrConstant4($s1)
add $s3, $s3, $t0
with immediate instruction
addi $s3,$s3,4
Design Principle: make the common case fast
24
12
Constants
Category
Instruction
Example
Meaning
Arithmetic
add immediate
addi $s1, $s2, 100
$s1 = $s2 + 100
and immediate
andi $s1, $s2,100
$s1 = $s2 & 100
or immediate
ori $s1, $s2, 100
$s1 = $s2 | 100
set less than
immediate
slti $s1, $s2, 100
If ($s2<100) $s1=1
else $s1=0
Logical
Conditional
branch
ƒ
ƒ
ƒ
ƒ
Why doesn’t MIPS have a subtract immediate operation ?
Constants are frequently short and fit into the 16-bit field
But, what if they are bigger ?
It would be convenient to have a 32-bit constant or address !!!!
25
How about large constants ?
The compiler or the assembler must break large constants into
pieces and then reassemble them into registers
ƒ We'd like to be able to load a 32 bit constant into a register
ƒ Must use two instructions, new "load upper immediate" instruction
lui $t0, 1010101010101010
filled with zeros
ƒ
1010101010101010
ƒ
0000000000000000
Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
1010101010101010
0000000000000000
1010101010101010
ori
1010101010101010
1010101010101010
26
13
Assembly Language vs.
Machine Language
ƒ Assembly provides convenient symbolic representation
ƒ much easier than writing down numbers
ƒ e.g., destination first
ƒ Machine language is the underlying reality
ƒ e.g., destination is no longer first
ƒ Assembly can provide 'pseudoinstructions'
ƒ e.g., “move $t0, $t1” exists only in assembly
ƒ would be implemented using “add $t0,$t1,$zero”
ƒ When considering performance you should count real
instructions
27
Translating and starting a program
28
14
Overview of MIPS
ƒ simple instructions all 32 bits wide
ƒ very structured
ƒ only three instruction formats
R
op
rs
rt
rd
I
op
rs
rt
16 bit number
J
op
shamt
funct
26 bit number
ƒ rely on compiler to achieve performance
29
Summary – MIPS operands
MIPS operands
Name
Example
Comments
$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
32 registers $a0-$a3, $v0-$v1, $gp,
arithmetic. MIPS register $zero alw ays equals 0. Register $at is
$fp, $sp, $ra, $at
reserved for the assembler to handle large constants.
Memory[0],
230 memory Memory[4], ...,
words
Memory[4294967292]
Accessed only by data transfer instructions. MIPS uses byte addresses, so
sequential w ords differ by 4. Memory holds data structures, such as arrays,
and spilled registers, such as those saved on procedure calls.
30
15
Summary – MIPS instructions
MIPS assembly language
Category
Arithmetic
Instruction
add
Example
add $s1, $s2, $s3
Meaning
$s1 = $s2 + $s3
Three operands; data in registers
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands; data in registers
$s1 = $s2 + 100
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
Used to add constants
addi $s1, $s2, 100
lw $s1, 100($s2)
sw $s1, 100($s2)
store word
lb $s1, 100($s2)
load byte
sb $s1, 100($s2)
store byte
load upper immediate lui $s1, 100
add immediate
load word
Data transfer
Conditional
branch
Unconditional jump
$s1 = 100 * 2
16
Comments
Word from memory to register
Word from register to memory
Byte from memory to register
Byte from register to memory
Loads constant in upper 16 bits
branch on equal
beq
$s1, $s2, 25
if ($s1 == $s2) go to
PC + 4 + 100
Equal test; PC-relative branch
branch on not equal
bne
$s1, $s2, 25
if ($s1 != $s2) go to
PC + 4 + 100
Not equal test; PC-relative
set on less than
slt
$s1, $s2, $s3
if ($s2 < $s3) $s1 = 1;
else $s1 = 0
Compare less than; for beq, bne
set less than
immediate
slti
jump
j
jr
jal
jump register
jump and link
$s1, $s2, 100 if ($s2 < 100) $s1 = 1;
Compare less than constant
else $s1 = 0
2500
$ra
2500
Jump to target address
go to 10000
For switch, procedure return
go to $ra
$ra = PC + 4; go to 10000 For procedure call
31
Addressing modes in MIPS
ƒ
Register addressing (e.g., add, sll, nor, slt, …)
ƒ the operand is a register
ƒ
Immediate addressing (e.g., addi, ori, …)
ƒ the operand is a constant within the instruction
ƒ
Base addressing (e.g. lw, sw)
[register+offset]
ƒ The operand is at the memory location whose address is
the sum of a register and a constant in the instruction
ƒ
PC-relative addressing (e.g., bne, beq) [PC + offset]
ƒ The address is the sum of the PC and a constant in the
instruction
ƒ
Pseudo-direct addressing (e.g., j)
[PC concatenation]
ƒ The address is the concatenation of a value in the
instruction with the upper bits of the PC
32
16
Addressing modes in MIPS
33
Alternative architectures
ƒ Design alternative:
ƒ provide more powerful operations
ƒ goal is to reduce number of instructions executed
ƒ danger is a slower cycle time and/or a higher CPI
ƒ RISC vs. CISC
ƒ virtually all instruction sets since 1982 are RISC
ƒ common architectures: 80x86, IA-32, PowerPC, …
34
17
“Spilling” registers
ƒ Many programs have more variables than computers
have registers
ƒ The compiler tries to keep the most frequently used
variables in registers and places the rest in memory
ƒ The process of putting less commonly used variables (or
those needed later) into memory is called spilling
registers
35
Supporting procedures
ƒ
Goal:
ƒ structure programs so that
ƒ it is easier to understand and reuse code
ƒ
Execution of a procedure
1. place parameters in a place where the procedure can access them
2. transfer control to the procedure
3. acquire the storage resources needed for the procedure
4. Place the result value in a place where the calling program can access it
5. Return control to the point of origin
ƒ
Basic MIPS facilities
ƒ $a0-$a3 Æ 4 argument registers in which to pass parameters
ƒ $v0-$v1 Æ 2 value registers in which to return values
ƒ $ra
Æ return address register to return to the point of origin
ƒ jal ProcedureAddress Æ jump-and-link (it saves PC+4 in $ra)
ƒ jr $ra
Æ jump register
36
18
What if we need more registers ?
ƒ A compiler may need more registers for a procedure than
the four argument and two return value registers
ƒ The local variables we need may not even fit in the MIPS
registers
ƒ also any register needed by the caller must be restored to
the values they contained before the procedure was
invoked
ƒ we need to spill the registers to memory
ƒ The ideal data structure for spilling registers is a stack
(last in first out)
ƒ push – place data on the stack
ƒ pop – remove data from the stack
37
The stack
ƒ MIPS allocate a register just for the stack: the stack pointer ($sp)
ƒ it points to the most recently allocated address in the stack
ƒ Stacks grow from higher addresses to lower addresses
ƒ push values on the stack by subtracting from the $sp
ƒ pop values from the stack by adding to the $sp
38
19
Example – compiling a leaf procedure
int leaf_example (int g, int h, int i, int j)
{
int f;
f = (g+h) – (i+j);
return f;
Memory
}
…
main
…
jal leaf_example
…
leaf_example
…
39
Example – compiling a leaf procedure
leaf_example:
addi $sp,$sp,-12
# adjust stack to make room for 3 items
sw $t1, 8($sp)
sw $t0, 4($sp)
sw $s0, 0($sp)
add $t0,$a0,$a1
add $t1,$a2,$a3
sub $s0,$t0,$t1
add $v0,$s0,$zer0
#
#
#
#
#
#
#
save
save
save
t0 =
t1 =
s0 =
v0 =
lw $s0, 0($sp)
lw $t0, 4($sp)
lw $t1, 8($sp)
addi $sp,$sp,12
jr $ra
#
#
#
#
#
restore $s0 for caller
restore $t0 for caller
restore $t1 for caller
adjust stack to delete 3 items
jump back to calling routine
$t1 for later us by the caller
$t0 for later us by the caller
$s0 for later us by the caller
g+h
i+j
t0–t1 = (g+h)-(i+j)
s0+0 (return f)
40
20
Reduce register spilling
ƒ To avoid saving and restoring a register whose value is
never used, MIPS separate temporary registers from
saved registers:
ƒ $t0-$t9: are not preserved by the callee (called
procedure)
ƒ $s0-$s7: must be preserved on a procedure call (if used,
the callee saves and restore them)
ƒ Thus, the assembly code generated for leaf_example by
a compiler can be more compact !!!
ƒ Can you guess how the code should look like ?
ƒ When a compiler finds a leaf procedure it exhaust all
temporary registers before using registers it must save
41
Nested procedures
ƒ procedures that do not call other procedures are called leaf
ƒ procedures that call other procedures are called nested
ƒ when a procedure call another procedure the solution is again to
push all the registers that must be preserved onto stack
ƒ the caller pushes any argument registers ($a0-$a3) or temporary
registers ($t0-$t9)
ƒ the callee (called procedure) pushes the return address $ra and
any saved registers ($s0-$s7)
42
21
Automatic and static variables
ƒ automatic variables are local to a procedure and are
discarded when the procedure exits.
ƒ static variables exist across exits from and entry to
procedures
ƒ variables outside of procedures and any variable
declared using the keyword static
ƒ MIPS reserve a register called global pointer ($gp) to
simplify access to static data
43
Allocating space for new data on
the stack
ƒ
ƒ
ƒ
ƒ
ƒ
The stack is also used to store variables that are local to the procedure that do
not fit in registers (e.g., local arrays or structures)
The segment of the stack containing a procedure’s saved registers and
variables is called a procedure frame
MIPS uses a frame pointer ($fp) to point to the first word of the frame
A stack pointer may move during the procedure, and so references to a local
variable in memory may have different offsets
A frame pointer offers a stable base register within a procedure
44
22
Allocating space for new data on
the heap
ƒ certain data structures (e.g., linked list) tend to grow and
shrink during their life time
ƒ the segment for such data structures is called heap
ƒ stack and heap grow toward each other
memory “leaks”
can use up
this segment
program code
for the OS
45
Text processing
ƒ Because of the popularity of text in some programs MIPS
provides instructions to move bytes and half words
ƒ C uses 8-bit to represent characters (ASCII = American
Standard Code for Information Interchange)
ƒ Java uses 16-bit to represent characters (Unicode)
ƒ load byte (lb) loads a byte from memory placing it in the
rightmost 8 bits of a register
ƒ store byte (sb) takes a byte from the rightmost 8 bits of a
register a writes it to memory
ƒ load half word (lh)
ƒ store half word (sh)
46
23
MIPS instructions and high level
programming languages
ƒ Arithmetic/logical instructions correspond to the
operations found in assignments
ƒ Data transfer are most likely to occur when dealing with
data structures like arrays or structures
ƒ Conditional branches are used in if statements and in
loops
ƒ Unconditional jumps are used in procedure calls and
returns and for case/switch statements
47
Concluding Remarks
ƒ Instruction complexity is only one variable
ƒ lower instruction count vs. higher CPI / lower clock
rate
ƒ Design Principles:
ƒ simplicity favors regularity
ƒ smaller is faster
ƒ good design demands compromise
ƒ make the common case fast
ƒ Instruction set architecture
ƒ a very important abstraction !
48
24
Common misconceptions and
mistakes
ƒ More powerful instructions mean higher performance
ƒ Write in assembly language give the highest performance
ƒ Forgetting that sequential word addresses in machines
with byte addressing do not differ by one
ƒ Using a pointer to an automatic variable outside its
defining procedure
49
25