International Journal of Engineering Research-Online
A Peer Reviewed International Journal
Articles available online http://www.ijoer.in
Vol.3., S2, 2015
ISSN: 2321-7758
ABSTRACT
In this paper the Universal Asynchronous Receiver / Transmitter i.e. UART which is also known as serial communication protocol allows the duplex communication in serial link for full duplex mode. High speed UART as well as efficient UART using VHDL will be main objective of this research. The UART controller design consists of three main components viz. transmitter, baud rate generator which divides frequency after each interval depending on the rate and receiver.
UART is also used for short distance communication, low speed, low cost data transmission and reception between CPU and other connected peripherals to the CPU. In industrial production, sometimes we do not need the full functioned UART, but we simply integrate its core part. The language used for the design will be
VHDL (VHSIC Hardware Description Language). The design will be synthesis and simulate on Xilinx ISE EDA tool.
Keywords- Asynchronous serial communication, Simulation, Synthesis, UART, VHDL, XILINX ISE.
INTRODUCTION
UART stands for Universal Asynchronous
Receiver/Transmitter. UART is generally used between the slow and the fast peripheral devices for example: CPU and Scanner or in between the
Microcontroller and Display. Hence, UART is used mostly for the short distance, low speed and is of low cost. Asynchronous serial communication is generally done by Universal Asynchronous Receiver
Transmitter. UART gives full-duplex communication in serial link, thus their applications are like data communications and control system. In actual applications, usually only a few key features of UART are required. Specific interface chip will cause waste of resources and increased cost. UART communication needs only two signal lines (TXD,
RXD) to complete full-duplex data communication.TXD is the transmit side, the output of UART; RXD is the receiver, the input of UART.
UART’s basic features are: There are two states in the signal line, using logic 1 (high) and logic 0 (low) to distinguish respectively. For example, when the transmitter is idle, the data line is in the high logic state. Otherwise when a word is given to the UART for asynchronous transmissions, a bit called the
"Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter.
These two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word.
After the Start Bit, the individual data bits of the word are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver “looks” at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a
0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on. When the entire data word has been sent, the transmitter may add a Parity Bit
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Proceedings of 4 th
International Conference On Quality Up-gradation in Engineering, Science & Technology
(ICQUEST_2015) Organized by Bapurao Deshmukh College of Engineering, Sevagram, Wardha – 442 102,
Maharashtra, India; 11 th
April.,2015

International Journal of Engineering Research-Online
A Peer Reviewed International Journal
Articles available online http://www.ijoer.in
that the transmitter generates. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter. When the receiver has received all of the bits in the data word, it may check for the Parity
Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be garbled and will report a
Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted. Regardless of whether the data was received correctly or not, the UART automatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host. If another word is ready for transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word has been sent. Because asynchronous data are “selfsynchronizing”, if there are no data to transmit, the transmission line can be idle. The UART frame format is shown in Fig. 1 [2].
Figure 1. UART Frame Format [2]
The processing steps of VLSI chips are extremely complex, and costly inducing vendors to stress on more and more testability as a requirement tool to assure the reliability and the functionality of each of their designed circuits. BIST technique has become as a boon to them, which helps to test a system automatically. Universal Asynchronous
Receive/Transmit (UART) has the objectives of firstly to satisfy specified testability requirements, and secondly to generate the lowest-cost with the highest performance implementation. UART has been an important input/output tool for decades and is still widely used. The additional BIST circuit that increases the hardware overhead increases designs time and size of the chip, which may degrade the performance [3].
Vol.3., S2, 2015
EXPERIMENTAL DETAILS
The three main components of the UART such as transmitter, receiver and the baud rate generator are described below:
A. Transmitter Module:
The function of the transmitter module is to convert the 8 bit serial data into the single bit data.
In this module, when our load signal is high the data_in is stored into the holding register. The data in the holding register is shifted to the intermediate register with the start bit of zero and this intermediate register is of 9 bits. Once the shift signal is high the least significant bit of the intermediate register i.e. the start bit comes at the output of the transmitter and served as the input to the receiver. When the entire data has been sent, the transmitter provides a parity bit which is served as the input to the receiver. To check the CRC error, we have to provide the divisor as the user input and once the entire data has been sent, the transmitter generates the remainder which is given as the input to the receiver and receiver provides us the crc_out.
B. Baud Rate Generator
The Baud rate generator is nothing but the frequency divider. In this UART we will apply the synchronized clock signal to both transmitter and the receiver. The clock signal applied to the receiver is 16 times to that of the transmitter.
C. Receiver Module
The function of the receiver module is that it will store the tx_out i.e. the output of the transmitter which is of single bit into the intermediate register with the start bit as the least significant bit and collectively provides the serial data of 8 it. When the load signal is high it will get the start bit from the transmitter which assures that the original data is now being send by the transmitter. Once the shift signal is becomes high with no load signal, the data coming from the transmitter gets shifted into the intermediate register of the receiver and provides the 8 bit serial data which we have given as an input to the transmitter. Once the entire data has been sent the parity error and the CRC errors has been checked out and are served as the input to the transmitter. If parity error and CRC errors occur or are at logic 1, it means that our transmission is having some errors [1].
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Proceedings of 4 th
International Conference On Quality Up-gradation in Engineering, Science & Technology
(ICQUEST_2015) Organized by Bapurao Deshmukh College of Engineering, Sevagram, Wardha – 442 102,
Maharashtra, India; 11 th
April.,2015

International Journal of Engineering Research-Online
A Peer Reviewed International Journal
Articles available online http://www.ijoer.in
Vol.3., S2, 2015
Figure 2. UART Module [2]
Functionally UART consist of (i) CPU intelogic,
(ii) Modem control section, (iii) trans (iv) receiver section.
Figure 5. UART Transmitter Internal Architecture
Block Diagram
The PISO block shown in Fig.5, takes 2 input signals: PISO_sel and Reg_load which are used for further processing of the UART operation.
Figure 3. UART Architecture Block Diagram
UART TRANSMITTER SECTION
Figure 4. UART Transmitter Architecture Block
Diagram
UART transmitter consists of an output register, a transmitter buffer register and transmitter control logic. The i/o pins are:
• TxD is the port for serial data output
• TxC bar is the transmitter clock input
• TxE is the transmitter control logic
• ACK & RST are two control inputs.
Figure 6. Port Mapping of UART Transmitter
Figure 6 shows the port mapping of UART transmitter which is used for connecting the devices.
Table1: Port Name and Functionality of UART
Transmitter
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Proceedings of 4 th
International Conference On Quality Up-gradation in Engineering, Science & Technology
(ICQUEST_2015) Organized by Bapurao Deshmukh College of Engineering, Sevagram, Wardha – 442 102,
Maharashtra, India; 11 th
April.,2015

International Journal of Engineering Research-Online
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Articles available online http://www.ijoer.in
FLOW CHART OF UART TRANSMITTER
Vol.3., S2, 2015
Table2: Port Name and Functionality of UART
Receiver
Figure 7. Flow Chart of UART Transmitter
UART RECEIVER SECTION
FLOW CHART OF UART RECEIVER
Figure 8. UART Receiver Architecture Block Diagram
Figure8 shows the architecture of UART receiver section. The followings are the brief description of each block.
Input Register: I/P register is a serial input and serial output register which consists of 8 D-flip flops to store and shift 8 bit input data. The input data of the register is the serially transmitted data from the transmitter.
Receiver buffer register: It is a 8 bit serial in parallel out register. The data of i/p register is shifted and enters bit by bit in every rising clock edge in Receiver Buffer Register. After entering 8 bit data, the buffer gets full.
Receiver Control Logic: This block decides when data is to be taken inside the receiver and when data is to be sent to peripheral device.
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Figure 9. Flow Chart of UART Receiver
CONCLUSION AND FUTURE SCOPE
This paper shows an efficient UART controller theory which includes transmitter section, receiver section and baud rate generation. Different architectures are shown here for different sections with flow charts and tables. In future work, we can design, synthesize and simulate the design using
VHDL. In VHDL type of language there is a concept called ease of description in different types of modelling which can be use to elaborate the design with respect to different parameters.
Proceedings of 4 th
International Conference On Quality Up-gradation in Engineering, Science & Technology
(ICQUEST_2015) Organized by Bapurao Deshmukh College of Engineering, Sevagram, Wardha – 442 102,
Maharashtra, India; 11 th
April.,2015

International Journal of Engineering Research-Online
A Peer Reviewed International Journal
Articles available online http://www.ijoer.in
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Dr. Garima Bandhawarkar Wakhle, Iti
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7695-4655-1/12 $26.00 © 2012 IEEE.
[2].
FANG Yi-yuan CHEN Xue-jun, Design and
Simulation of UART Serial Communication
Module Based on VHDL , 978-1-4244-9857-
[3].
4/11/$26.00 ©2011 IEEE.
Zou,Jie Yang,Jianning 。 Design and
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Suparjo, Design of a micro - UART for SoC application , Computers and Electrical
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[5].
HU Hua, BAI Feng-e. Design and Simulation of UART Serial Communication Module
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[6].
Frank Durda Serial and UART Tutorial. uhc
Vol.3., S2, 2015
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Proceedings of 4 th
International Conference On Quality Up-gradation in Engineering, Science & Technology
(ICQUEST_2015) Organized by Bapurao Deshmukh College of Engineering, Sevagram, Wardha – 442 102,
Maharashtra, India; 11 th
April.,2015