TM
UNITED STATES
CONFERENCE
PROGRAM
- AND -
EXHIBITION
GUIDE
The Premier Conference For
Functional Design & Verification
March 2-5, 2015 DVCon.org
NVERSA
O
C
&
S
IL
A
KT
TIONS
L
A
U
N
N
A
2
COC
ND
L
W
A
R
C
BOOTH
m
:00 - 7:00p
5
•
2
H
C
R
OR
NDAY, MA
MO
O
IBIT FL
ON THE EXH
CON
2
DV
5
01
VISIT THESE PARTICIPATING COMPANIES’ BOOTHS:
C
C o
on ckt
ve ails ns
rsatio
&
WIN $500!
• ATTEND THE BOOTH CRAWL
• GET AUTOMATICALLY ENTERED INTO A DRAWING FOR A $500 VISA GIFT CARD
• WINNER ANNOUNCED MONDAY AT 6:45PM ON THE EXHIBIT FLOOR!
(WINNER MUST BE PRESENT TO WIN)
TABLE OF CONTENTS
General Chair’s Welcome...... 4-5
Wednesday Agenda............... 28
General Information................... 6
Panel Session..............................29
Voting Instructions...................... 7
Sessions: 8 - 10...........................30
Conference Sponsor................... 8
Lunch Presentation..................31
Accellera Technical
Excellence Award......................... 9
Panel Session..............................32
Steering Committee.................10
Program Committee.................11
Monday Agenda....................... 13
Tutorials: 1 - 2.......................14-15
Lunch Presentation..................16
Sessions: 11 - 13...................33-34
Best Paper Award.................. 34
Thursday Agenda.................... 35
Tutorials: 5 - 7.......................36-38
Lunch Presentation..................40
Tutorials: 8 - 10.....................41-43
Tutorials: 3 - 4.......................17-18
Tuesday Agenda...................... 19
Sessions: 1 - 3..............................20
DVCon Expo............................... 44
Event Sponsors....................44-45
Exhibitor Listing.........................47
Session 4:
Poster Session.................. 21-23
Exhibitor Floorplan...................48
Lunch Presentation..................24
Exhibiting Companies........49-59
Keynote Address........................25
First Time Exhibitors................60
Sessions: 5 - 7........................26-27
DVCON.ORG
3
WELCOME TO DVCON
YATIN TRIVEDI
General Chair - Synopsys, Inc.
Welcome to DVCon 2015!
Networking. Technical discussions. Learning opportunities. Exciting exhibits of new
products and services. This is what DVCon attendees are used to, and you will find all of
this and more at DVCon 2015.
This year’s Accellera-sponsored DVCon promises to include many hot areas of Design and
Verification, with focus on Low Power, System Design, IP Reuse, Mixed-Signal, and Debug
Strategies.
Technical topics like these (among others) will be distributed throughout the four days
with lectures, discussions, and demos that promise to be intriguing and applicable for
every attendee and their projects. From the keynote address and panel discussions to
technical tutorials, papers and posters DVCon will offer many learning opportunities.
In fact, due to the large number of quality submissions, the technical program committee
members had quite a challenge narrowing down the papers and posters to a select few.
With this year’s outstanding program, I expect it will be difficult for attendees to allocate
where they spend their time, and an even greater challenge will be to pick the best paper
and the best poster from so many worthy candidates. Please be sure to cast votes for
your favorite papers and posters. Winners will be announced after the last technical
session on Wednesday.
Nothing beats learning from the industry practitioners. Monday’s four Accellera Day
tutorials and Thursday’s Industry Day six vendor-sponsored tutorials are a mustattend for those interested in picking up new skills. These tutorials are conducted by
subject-matter experts who have often participated in development and deployment of
standards-based tools and methodologies.
This year’s keynote address, Smart Design from Silicon to Software, will be delivered by
Synopsys’ Chairman and Co-CEO Dr. Aart de Geus. Many of us are designing chips for
tomorrow’s smart devices. In his presentation on Tuesday, Aart will address the business
and technology trends that are stretching designers’ concerns beyond the traditional
sand boxes of design and verification.
The two panel discussions on Wednesday will bring industry pundits to weigh in on the
verification strategies as well as the significance of System C as a design and verification
language of the future. These panel discussions are always lively and contain valuable
advice from many of the great pioneers of the industry. The keynote address and the
panel discussions are open sessions available to anyone with free registration.
Not to be missed, all the latest and greatest products in the exhibits bring reality check
to the geek talk! Back by popular demand, the “booth crawl” is where you want to be
Monday evening. You will have an opportunity to spend some casual networking time
with exhibitors and colleagues, and even have a chance to win some cool gifts.
4
DVCON.ORG
WELCOME TO DVCON
With the largest number of exhibitors ever hosted at DVCon, I strongly encourage you to
map out your three-day exhibit strategy to visit more than forty vendors without missing a
single one. See their product demonstrations, inquire about their IPs, or learn about their
latest service engagement. You be the judge if some of the products and services truly
help you solve the most challenging problems of your chips.
DVCon is a community networking event. Whether you are there to attend just one
tutorial on emulation, talk to an exhibitor about FPGA prototyping solution or listen to
the keynote, make sure to meet your peers. Stop by the posters, join us for sponsored
lunch, and mingle with colleagues at the reception. DVCon’s focus remains on the EDA
languages, tools, methodologies and standards. There will be something for everyone –
designers, verification engineers, semiconductor IP developers, EDA tool developers, and
service providers.
You may have noticed the new logo for this year’s conference: “DVCON 2015 United
States.” This exciting change is a result of the tremendous success of DVCons and its
predecessor events over the last 27 years. In addition to sponsoring the DVCon in US, in
2014 Accellera launched two new regional conferences: DVCon Europe and DVCon India.
Both conferences have been patterned after DVCon with a focus on highly technical
content and quality peer interactions. Best wishes to both sister conferences as they
follow in our footsteps. We will continue to collaborate and guide them in building strong
user communities just like ours.
I feel privileged to have the opportunity to make a small contribution to our wonderful
community. I am fortunate to have attended just about all of the DVCon and its
predecessor conferences, and each has had a significant contribution in shaping my
career. I hope this 2015 conference will make a positive contribution to your career as
well. As you participate in this year’s conference, please take a moment to acknowledge
the service offered to the industry by Accellera members, the financial support of our
sponsors, the tireless efforts by the volunteers of the Steering Committee, and the
professional execution by the very capable and energetic team at MP Associates. A warm
thanks to all of you – DVCon could not be a reality otherwise.
Welcome to DVCon 2015!
DVCON.ORG
5
DVCON DETAILS
REGISTRATION HOURS
Location: Bayshore Foyer
Monday, March 2
7:30am to 7:00pm
Tuesday, March 3
7:30am to 6:30pm
Wednesday, March 4
7:30am to 6:30pm
Thursday, March 5
7:30am to 4:00pm
EXPO HOURS
Location: Bayshore Ballroom
CON
2
DV
Tuesday, March 3
2:30 to 6:00pm
Wednesday, March 4
2:30 to 6:00pm
5
01
5:00 to 7:00pm
C
C o
on ckt
ve ails ns
rsatio
&
Monday, March 2
PARKING INSTRUCTIONS
Overnight self parking is $10.00 per day/per car with no in/out privileges.
Local Attendees are to scan their parking ticket at the designated DVCon validation area
(Bayshore Foyer). The scanner will beep 3 times to notify the attendee has validated their
tickets at the group discounted rate.
There are two pay stations inside the hotel. One is located near the convention entrance
(Bayshore Foyer) side and this machine accepts both cash and credit card. The second
pay station is located near the guest elevators near the South Parking Lot. This machine
accepts only cash.
WIRELESS INFORMATION
Enjoy free Wi-Fi at DVCon! Connect to the Conference Wi-Fi via:
Wi-Fi SSID: DVCon2015
No Password Required
TM
DVCON TUTORIALS & PROCEEDINGS DISTRIBUTION
DVCon Conference Papers and Tutorial presenter slides will be delivered electronically
online via a username and password.
To access: http://proceedings.dvcon.org
Username = Email address
Password = Registration ID (on your badge)
Please refer to your registration receipt to access the files you are eligible to view.
6
DVCON.ORG
SOCIAL MEDIA AT DVCON
Twitter: Follow @DVCon on Twitter and get hourly conference announcements.
Also, tweet #DVCon about your experience and highlights at the conference!
Facebook: Don’t miss DVCon on Facebook at facebook.com/DVCon.
BEST PAPER & POSTER VOTING INSTRUCTIONS
All Access, Conference Only and One-Day only registrants are entitled to vote for the
“DVCon Best Paper and Poster” awards. The Attendees are the judges!
Enjoy the convenience of voting from your PC and mobile device.
DVCon 2015
ote
Best Paper & Poster
Sponsored by:
VOTING PROCEDURES
1
Go to www.dvcon.org/2015/vote.
2
Vote on the papers and posters you have attended.
AWARDS PRESENTATION:
Wednesday, March 4th
4:45pm
Oak/Fir Ballroom
DVCON.ORG
7
CONFERENCE SPONSOR
About Accellera Systems Initiative
Accellera Systems Initiative, the proud sponsor of DVCon, is an independent organization
with the mission to provide design and verification standards required by systems,
semiconductor, IP and design tool companies to enhance a front-end design automation
process. We collaborate with our community of companies and organizations in
delivering the standards that lower the cost to design commercial EDA, IC and
embedded system solutions. As a result of its partnership with the IEEE, Accellera
standards are transferred to the IEEE Standards Association for formalization and
ongoing change control.
Accellera Systems Initiative: A New Synergy for Standards
System, software, and semiconductor design are converging to meet the increasing
challenges to create complex integrated circuits and system on chips. This convergence
has brought to the forefront the need for a single organization to facilitate the creation
of system-level, semiconductor design, and verification standards. Leading industry
standards associations Accellera Organization Inc. and the Open SystemC Initiative (OSCI)
merged in 2011 to form a single organization, Accellera Systems Initiative, to address the
needs of the system and semiconductor designers who must find new and smarter ways
to create and produce increasingly complex chips. The new organization will evolve to
create more comprehensive standards that benefit the global electronic
design community.
Membership
Accellera members directly influence development of the most important and widely
used standards in electronic design. Member companies protect and leverage their
investment in design languages through their funding of a proven, effective and
responsible organization. In addition, our members have a higher level of visibility in the
EDA industry as active participants in Accellera-sponsored activities and as contributors
to its decisions, which impact the EDA industry. For a full list of technical activities that
are supported by Accellera, and for information on how to join us, please visit our website
at www.accellera.org.
8
DVCON.ORG
ACELLERA SYSTEMS INITIATIVE
TECHNICAL EXCELLENCE AWARD
Accellera wishes to recognize the outstanding achievements of its Working Group
members by selecting outstanding contributors to our standards development process
as recipients of the Accellera Systems Initiative Technical Excellence Award.
This annual award recognizes major contributions to the development of Accellera
standards. Examples of such contributions may include leadership in standardization
of new technologies, assuring achievement of standards development goals, and
identifying opportunities to better serve the needs of the community through standards.
Any member of an Accellera Working Group is eligible for the award. Candidates can be
nominated by Working Group chairs and are endorsed and selected by participants of
the Accellera Technical Excellence Award Committee, which is a subcommittee of the
Technical Committee.
Past Recipients:
2014: Andrew Goodrich
2013: Janick Bergeron
2012: John Aynsley
For more information about Accellera awards programs and to find out how to submit a
nomination, visit accellera.org/about/awards.
Sponsored by:
DVCON.ORG
9
STEERING COMMITTEE
General Chair
Past Chair
700 East Middlefield Rd.
Mountain View, CA 94043
650-584-5000
Yatin.Trivedi1@synopsys.com
2655 Seely Ave.
San Jose, CA 95134
408-944-7260
stanleyk@cadence.com
Program Chair
Poster Chair
300 Brickstone Sq.
Andover, MA 01810
508-292-1681
ambar.sarkar@paradigm-works.com
700 East Middlefield Rd.
Mountain View, CA 94043
650-584-5000
SHemmady@Synopsys.com
Accellera Day Tutorial Chair
Sponsored Tutorial Chair
270 Billerica Rd.
Chelmsford, MA 01824
978-262-6389
asherer@cadence.com
18 Whistle Post Ln.
Groton, MA 01450
978-448-8797
tom_fitzpatrick@mentor.com
Yatin Trivedi
Synopsys, Inc.
Stanley J. Krolikoski, Ph.D.
Cadence Design Systems, Inc.
Shankar Hemmady
Synopsys, Inc.
Ambar Sarkar, Ph.D.
Paradigm Works, Inc.
Adam Sherer
Cadence Design Systems, Inc.
Accellera Representative
& Finance Chair
Panel Chair
Vanessa Cooper
Verilab, Inc.
8310 North Capital of Texas Hwy,
Ste 215
Austin, TX 78731
512-537-3136 ext. 7101
vanessa.cooper@verilab.com
Lynn Bannister
Accellera Systems Initiative
8698 Elk Grove Blvd. Ste 1, #114
Elk Grove, CA 95624
916-670-1056
Lynn@accellera.org
Publicity/Marketing Chair
Conference Manager
14359 SE Donatello Loop
Happy Valley, OR 97086
503-209-2323
barbara@hipcom.com
1721 Boxelder St., Ste. 107
Louisville, CO 80027
303-530-4562
kathy@mpassociates.com
Kathy Embler, CMP
MP Associates, Inc.
Barbara Benjamin
HighPointe Communications
10
Tom Fitzpatrick
Mentor Graphics Corp.
DVCON.ORG
TECHNICAL PROGRAM COMMITTEE
Poster Chair
Program Chair
Shankar Hemmady
Synopsys, Inc.
Ambar Sarkar, Ph.D.
Paradigm Works, Inc.
Mark Azadpour - Western Digital Corp.
Neyaz Khan - Maxim Integrated, Inc.
Amit Baranwal - Microsoft Corp.
Kelly Larson - NVIDIA
Dan Benua - Synopsys, Inc.
Kaowen Liu - MediaTek, Inc.
Shalom Bresticker - Intel Corp.
Paul Marriott - Verilab
Clifford Cummings - Sunburst Design, Inc.
Gordon McGregor - Nitero, Inc.
Charles Dawson
- Cadence Design Systems Inc.
Don Mills - Microchip Technology, Inc.
Nagi Naganathan - Avago Technologies
Joanne DeGroat - Ohio State Univ.
Karen Pieper - Tabula
Stephen D’Onofrio - Paradigm Works
Mitchell Poplingher - Microsemi Corp.
Jack Donovan - ARM, Inc.
Harry Foster - Mentor Graphics Corp.
Logie Ramachandran
- VeriKwest Systems Inc.
Manish Gajjar - Broadcom Corp.
Dave Rich - Mentor Graphics Corp.
Ning Guo - Advanced Micro Devices, Inc.
Imtiyaz Ron - Broadcom Corp.
Kaiming Ho - Fraunhofer IIS
Eric Seligman - Intel Corp.
Phu Huynh - Cadence Design Systems, Inc.
Stuart Sutherland - Sutherland Hdl, Inc.
Alfonso Iniguez
- Microchip Technology, Inc.
Robert Troy - On Semiconductor
Tor Jeremiassen - Texas Instruments, Inc.
Greg Tumbush - Tumbush Enterprises LLC
DVCON.ORG
11
THURSDAY TUTORIAL SPONSORS
LUNCHEON SPONSORS
12
MONDAY
TUESDAY
WEDNESDAY
THURSDAY
DVCON.ORG
MONDAY’S AGENDA
9:00am - 12:00pm
TUTORIAL 1: SystemVerilog Design: User Experience Defines Multi-Tool,
Multi-Vendor Language Working Set
Location: Oak
TUTORIAL 2: Automating Design and Verification of Embedded Systems
Using Meta-Modeling and Code Generation Techniques
Location: Fir
12:00 - 1:30pm
Sponsored by:
SPONSORED LUNCHEON: What is Needed to Drive
Design Efficiency?
Location: Pine/Cedar
2:00 - 5:00pm
TUTORIAL 3: Next Generation Design and Verification Today
Location: Oak
TUTORIAL 4: SystemC Update and Tutorial
Location: Fir
5:00 - 7:00pm
CON
2
DV
DVCON EXPO & BOOTH CRAWL
5
01
Location: Bayshore Ballroom
DVCon is doing it again! You won’t want to miss the
annual DVCon Booth Crawl on the exhibit floor.
Food and beverage will be provided by the participating
Booth Crawl Exhibitors.
&
C
C o
on ckt
ve ails ns
rsatio
By attending the Booth Crawl you’ll be automatically entered into a
drawing for a $500 VISA gift card. The winner must be present to win and
will be announced Monday night.
A Flag
Signifies
Participating
Companies
COFFEE BREAKS
Location: Gateway Foyer
• 8:00 - 11:00am
• 3:00 - 4:00pm
Parking Information: There are two pay stations inside the hotel. One is located near the convention
entrance (Bayshore Foyer) side and this machine accepts both cash and credit card. The second pay
station is located near the guest elevators near the South Parking Lot. This machine accepts only cash.
Overnight self parking is $10.00 per day/per car with no in/out privileges.
DVCON.ORG
13
MONDAY, MARCH 2
TUTORIAL 1 - SYSTEMVERILOG DESIGN: USER EXPERIENCE
DEFINES MULTI-TOOL, MULTI-VENDOR LANGUAGE WORKING SET
Time: 9:00am - 12:00pm | Room: Oak
Organizer:
Adam Sherer - Accellera Systems Initiative
It has been 10 years since standardization of SystemVerilog under IEEE 1800. In that
time it has experienced tremendous proliferation in the verification world. The language
is the heart of UVM reference library and is so well recognized as a necessary driver to
verification to efficiency that nearly every company recognizes they need to leverage it to
be competitive.
While SystemVerilog introduced many features specific to the verification world, it
also introduced many new capabilities for the design world. However, the usage of
SystemVerilog in design has been much slower to proliferate in the electronic design
industry. The main reason is the large number tools that the design code must
successfully navigate on its way to silicon. While SystemVerilog code in the test bench
will need to be handled by few tools in the verification space, SystemVerilog in the design
must by handled by many tools including synthesis, lint checking, formal, simulation, low
power, hardware, equivalence checking, etc. Some will be from multiple vendors, some
from point tool providers and some will be home grown tools. Translating the LRM into
the working set across multiple tools and vendors takes a mix of planning and testing.
This tutorial will bring together leading edge technology users who have
used SystemVerilog constructs in their design. They will describe their motivations for
using SystemVerilog, the success and failures they encountered along the way and the
productivity gains achieved.
The tutorial will be delivered by experts through real code, real examples, and real
improvements that were achieved on the way to tape out. It will also cover the negative
side, such as construct support limitations needed to use a common code base across
the tool set.
The attendee will take home a new perspective on SystemVerilog for design, an
understanding of what can work today, and a new stick to prod their tool vendors to
deliver a more complete support.
Speakers:
Stuart Sutherland - Sutherland HDL, Inc.
Mike Schaffstein - Qualcomm, Inc.
Junette Tan - PMC-Sierra, Inc.
14
DVCON.ORG
MONDAY, MARCH 2
TUTORIAL 2 - AUTOMATING DESIGN AND VERIFICATION OF
EMBEDDED SYSTEMS USING META-MODELING AND CODE
GENERATION TECHNIQUES
Time: 9:00am - 12:00pm | Room: Fir
Organizer:
Wolfgang Ecker - Infineon Technologies AG
The tutorial presents the application of the known SW development methodology
“Meta-Modeling and Code Generation” to the design of SOCs, mainly the semi-automated
generation of SystemC prototypes, firmware and hardware (RTL, Schematic) as well
as verification measures such as elements of a SystemVerilog UVM testbench or SVA
properties for those. Therefore, it fits the scope of DVCon exactly which covers the
mentioned description styles as well as testbench automation and high-level synthesis
and is therefore from high interest for the engineers attending DVCon. With IP-XACT and
UML it also covers standards widely used in ESL design.
Meta-Modeling opens a complete new modeling space for hardware designers. Instead
of thinking in models-of-computation or description languages, the designers think
and model in terms of things, attributes of these things and their relationships. The
description of involved things, attributes, and relationships is described in a so called
Meta-Model. A Model, being an instance of a Meta-Model describes one specific thing with
its sub-elements, attribute values and relation settings.
Also, parts of existing Meta-Model definitions as from UML, SysML, or IP-XACT can be used
to define the structure of the models. Often parts of the model can be extracted from
specification and thus consistency in the design process can be improved. When having
built a model, code can be generated from that model. This can be done via hand coded
generators or template engines.
The tutorial (a detailed structure available on request) starts with the introduction of
Meta-Modeling concepts and techniques and shows that Meta-Modeling has already over
20 years of history in hardware design. Next follows the presentation of standard MetaModels in the hardware domain and the discussion of their application. The tutorial ends
with a set of application examples, each of which can be directly utilized by attendees
since they are based on open-source Eclipse and XML technologies.
The tutorial is prepared and given by design, verification, as well as (meta-) modeling
experts, which work for globally known companies, research institutes, and universities.
This mix ensures a depth of engineering content and breadth of real-life examples and
thus provides a high value to the attendees.
Speakers:
Michael Velten - Infineon Technologies AG
Rainer Findenig - Intel Corp.
Daniel Müller-Gritscheneder - Technical Univ. of Munich
Wolfgang Mueller - C-Labs LLC
DVCON.ORG
15
MONDAY, MARCH 2
SPONSORED LUNCHEON - WHAT IS NEEDED TO DRIVE
DESIGN EFFICIENCY?
Time: 12:00pm - 1:30pm | Room: Pine/Cedar
Organizer:
Adam Sherer - Accellera Systems Initiative
John Aynsley - Doulos
The 2015 Accellera Systems Initiative day is bringing the “D” for design back into DVCon.
The tutorials through the day primarily focus on design issues including practical
examples of SystemVerilog for design, examples and new standards work for SystemC,
and even methods to apply UCIS for tracing design requirements.
This focus brings to light an important question – what is needed to further drive design
efficiency? During the Accellera sponsored lunch, we will ask a panel of technical experts
to discuss current practices and gaps with a focus on where the standards need to go.
This discussion will build on the tutorials you will see throughout the day so it should
be lively!
Panelists:
Stuart Sutherland - Sutherland HDL, Inc.
Mike Schaffstein - Qualcomm, Inc.
Pat Sheridan - Synopsys, Inc.
Andy Goodrich - Cadence Design Systems, Inc.
Bryan Bowyer - Calypto Design Systems, Inc.
Sponsored by:
16
DVCON.ORG
MONDAY, MARCH 2
TUTORIAL 3 - NEXT GENERATION DESIGN AND
VERIFICATION TODAY
Time: 2:00pm - 5:00pm | Room: Oak
Organizer:
Mike Bartley - Test and Verification Solutions
When standards are applied in interesting ways to push the electronics industry they
become much more than a language reference manual (LRM). The working groups
in Accellera are focused on solving specific problems key to raising the efficiency of
our industry forming a design and verification foundation for us all to use. However,
the problems we need to solve often need more than one technology. In that case,
the community applies the existing standards in novel ways by connecting them together
to solve next-generation problems today.
Mixed-signal verification is widely recognized as a growing challenge for modern
semiconductors. The tutorial will walk through a methodology that uniquely uses the
power and architecture of the SystemVerilog UVM_REG to provide the necessary hooks
to achieve constrained random stimulus during an AMS simulation thereby allowing the
verification engineers to collect coverage automatically. Specific examples and lessons
learned will be shared to emphasize how these techniques help in bridging the coverage
gap between analog and digital interfaces which are the most challenging areas in the
realm of mixed-signal verification.
Not only are huge projects in need of requirements-driven verification but some
industries, like automotive have codified the need into their standards. Requirementsdriven verification is similar to coverage-driven verification in the sense that it is metricdriven but differs significantly because the metrics derive from requirements rather than
verification goals. Requirements-driven verification is also required for compliance with
the increasing number of standards that control development of hardware for domains
such as automotive (ISO26262) and avionics (DO254). This tutorial will show how the
UCIS can be in an automotive example to cover the three main issues regarding standards
compliance and how they are covered through a requirements-driven verification
methodology.
Power management for RTL and gates via the UPF standard, now IEEE 1801-2013, is
widely used in the electronics industry. With an increasing number of projects already
moving to system level, or planning to in the near future, the P1801 working group is
examining the next abstraction level as well. This tutorial will examine this exciting next
step for power management.
Speakers:
Mike Bartley - Test and Verification Solutions
Kyle Newman - Texas Instruments, Inc.
Erich Marschner - Mentor Graphics Corp.
DVCON.ORG
17
MONDAY, MARCH 2
TUTORIAL 4 - SYSTEMC UPDATE AND TUTORIAL
Time: 2:00pm - 5:00pm | Room: Fir
Organizer:
Adam Sherer - Accellera Systems Initiative
The ever-increasing complexity of electronic systems isadding pressure to move to an
abstraction above RTL. Recognizing this need, Accellera Systems Initiative member
companies are evolving the IEEE 1666 SystemC standard to do just that.
Based itself on the ISO/IEC 14882-2003 standard, SystemCIEEE 1666-2011 provides
the language structure to implement transaction level modeling (TLM). As the user
community put this standard into practical use, it also realized that more could be done
to improve and expand the standard. Today, Accellera is working on standards for analog
modeling, a synthesizable subset, model-tool interface, and verification.
This tutorial will provide an update on the work in eacharea and user experiences
applying SystemC. If you want a glimpse of the future, attend this tutorial!
Speakers:
Andy Goodrich - Cadence Design Systems Inc.
Pat Sheridan - Synopsys, Inc.
18
DVCON.ORG
TUESDAY’S AGENDA
8:15 - 8:45am
OPENING SESSION
Location: Oak/Fir
9:00 - 10:30am
SESSION 1: Mixed Signal
Location: Oak
SESSION 2: Stimulus Generation
Location: Fir
SESSION 3: Design
Location: Monterey/Carmel
10:30am - 12:00pm
SESSION 4: Poster Session
Location: Gateway Foyer
12:00 - 1:15pm
Sponsored by:
SPONSORED LUNCHEON: Industry Leaders Verify with Synopsys
Location: Pine/Cedar
1:30 - 2:30pm
KEYNOTE: Smart Design from Silicon to Software
Aart de Geus, Chairman and co-Chief Executive Officer - Synopsys, Inc.
Location: Oak/Fir
2:30 - 6:00pm
DVCON EXPO
Location: Bayshore Ballroom
3:00 - 5:00pm
SESSION 5: Testbench Construction
Location: Oak
SESSION 6: Advanced Techniques
Location: Fir
SESSION 7: Multi-Language
Location: Monterey/Carmel
5:00 - 6:00pm
DVCON RECEPTION
Location: Bayshore Ballroom
DVCON.ORG
19
TUESDAY, MARCH 3
OPENING SESSION
Time: 8:15am - 8:45am | Room: Oak/Fir
Join us as we set the stage for the 2015 DVCon Conference and Exhibition.
DVCon’s Steering Committee will highlight the conference’s events.
SESSION 1 - MIXED SIGNAL
Time: 9:00am - 10:30am | Room: Oak
Chair: Neyaz Khan - Maxim Integrated
1.1Specification Driven Analog and Mixed-Signal Verification
Henry Chang, Kenneth Kundert - Designer’s Guide Consulting, Inc.
1.2 Advanced Digital-Centric AMS Methodology
David Lacey, Michael Kontz - Hewlett-Packard Co.
1.3 Mixed Signal Verification of UPF Based Designs. A Practical Example.
Andrew S. Milne, Damian Roberts - Synopsys, Inc.
SESSION 2 - STIMULUS GENERATION
Time: 9:00am - 10:30am | Room: Fir
Chair: Clifford Cummings - Sunburst Design, Inc.
2.1Reuse C Test and UVM Sequence Utilizing TLM2, Register Model and
Interrupt Handler
HongLiang Liu, TengFei Gao - Advanced Micro Devices, Inc.
2.2Automated Test Generation to Verify IP Modified for System Level
Power Management
Christophe Lamard - STMicroelectronics
Frederic Dupuis - Cadence Design Systems, Inc.
2.3 Engineered SystemVerilog Constraints
Jeremy Ridgeway - Avago Technologies
SESSION 3 - DESIGN
Time: 9:00am - 10:30am | Room: Monterey/Carmel
Chair: Stuart Sutherland - Sutherland HDL, Inc.
3.1 Design Guidelines for Formal Verification
Anamaya Sullerey - Juniper Networks, Inc.
3.2Methodology for Separation of Design Concerns Using Conservative
RTL Flipflop Inference
Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj - American Univ. of Beirut
Ali Elzein, Wolfgang Roezner - IBM Systems and Technology Group
3.3 Unleashing the Full Power of UPF Power States
Erich Marschner - Mentor Graphics Corp.
John Biggs - ARM Ltd.
20
DVCON.ORG
TUESDAY, MARCH 3
SESSION 4 - POSTER SESSION
Time: 10:30am - 12:00pm | Room: Gateway Foyer
Chair: Shankar Hemmady - Synopsys, Inc.
4.1Goldilocks and System Performance Modeling - A SystemVerilog Adaptive
Rate Control (ARC) Stimulus Generation Methodology
Rich Edelman, Shashi Bhutada- Mentor Graphics Corp.
4.2 Verification Environment Automation from RTL
Zhidong Chen, Yunyang Song, Wenting Hou, Junna Qiao, Junxia Wang,
Ling Bai, Kei-Wang Yiu - MediaTek, Inc.
4.3 Matrix Math Package for VHDL
David W. Bishop - Intrinsix Corp.
4.4 Closing Functional and Structural Coverage on RTL Generated by HLS
Bryan Bowyer - Calypto Design Systems, Inc.
4.5A Code Coverage Convergence Methodology to Speed-Up and Improve
Functional Verification of Complex Digital Designs
Sakthivel Pullagoundapatti, G. Chithambaranathan,
Shrinivas Sureban - Avago Technologies
Vasudev Srinivasan - Synopsys, Inc.
4.6 Testpoint Synthesis Using Symbolic Simulation
Kai-Hui Chang, Yen-Ting Liu, Chris Browy - Avery Design Systems, Inc.
4.7 Design and Verification of a Multichip Coherence Protocol
Shahid Ikram, Isam Akkawi, David Asher, Rick Kessler, Jim Ellis - Cavium, Inc.
4.8Jump-Start Software-Driven Hardware Verification with a Verification
Framework
Matthew Ballance - Mentor Graphics Corp.
4.9Not Just for Hardware Debug: Prototype Debuggers for System Validation
and Optimization
Michael Sachtjen, Joe Gaubatz - Mentor Graphics Corp.
4.11SystemVerilog Constraint Layering via Reusable Randomization Policy
Classes
John Dickol - Samsung Austin R&D Center
4.12 Versatile UVM Scoreboarding
Jacob S. Andersen, Peter Jensen, Kevin K. Steffensen - SyoSil ApS
DVCON.ORG
21
TUESDAY, MARCH 3
SESSION 4 - POSTER SESSION (CONTINUED)
Time: 10:30am - 12:00pm | Room: Gateway Foyer
4.13 Automatic Partitioning for Multi-Core HDL Simulation
Gaurav Kumar, Sandeep Pagey, Mohit Sinha, Manu Chopra
- Cadence Design Systems, Inc.
4.15Want a Boost in Your Regression Throughput? Simulate Common Setup
Phase Only Once
Rohit K. Jain, Shobana Sudhakar - Mentor Graphics Corp.
4.16Virtual Test: Simulating ATE Vectors in a System Verilog Testbench for
Faster Time to Market
Matthew Borto, Cecil Stone, David Brownell, Courtney Fricano, John Mackintosh
- Analog Devices, Inc.
4.17 Designing Portable UVM Test Benches for Reusable IPs
Xiaoning Zhang, Terry Li, Baosheng Wang, Karl Whiting - Advanced Micro Devices, Inc.
4.18 Taming a Complex UVM Environment
Manjunath Shetty, Ramamurthy Gorti - Broadcom Corp.
4.19Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in
Customized UVM VIP Using Abstract Classes
Roman Wang, Thomas Bodmer - Advanced Micro Devices, Inc.
4.20A Simplified and Reusable UVM Config DB Methodology for Environment
Developers and Test Writers Alike
Robert D. Oden - Mentor Graphics Corp.
4.21 Are You Smarter Than Your Testbench? With a Little Work You Can Be
Rich Edelman, Raghu Ardeishar - Mentor Graphics Corp.
4.22 Randomizing UVM Config DB Parameters
Jeremy Ridgeway - Avago Technologies
4.23 Coverage Data Exchange Is No Robbery, Or Is It?
Darron K. May, Samiran Laha, Thom Ellis - Mentor Graphics Corp.
4.24Conditional Delays for Negative Limit Timing Checks in
Event Driven Simulation
Nadeem A. Kalil, David Roberts - Cadence Design Systems, Inc.
REMEMBER TO VOTE!
ote
22
Best Paper & Poster
Deadline:
Wednesday, March 4, 4:30pm
DVCON.ORG
TUESDAY, MARCH 3
4.26 Git For Hardware Designers
Sanjeev P. Singh, Jeffery Scott - Juniper Networks, Inc.
4.27 The Big Brain Theory - Visualizing SoC Design & Verification Data
Gordon Allan - Mentor Graphics Corp.
4.28 Meta Design Framework: Building Designs Programmatically
Jonathan Sadowsky, Sanjeev P. Singh - Juniper Networks, Inc.
4.29 Highly Configurable UVM Environment for Parameterized IP Verification
HongLiang Liu, Karl Whiting - Advanced Micro Devices, Inc.
4.31 Debug Challenges in Low-Power Design and Verification
Jitesh Bansal, Madhur Bhargava, Jitesh Bansal - Mentor Graphics Pvt. Ltd., India
Chuck Seeley - Mentor Graphics Corp.
4.32The UPF 2.1 Library Commands: Truly Unifying the Power
Specification Formats
Amit Srivastava, Awashesh Kumar, Vinay Singh - Mentor Graphics Pvt. Ltd., India
4.33 Next-generation Power Aware CDC Verification – What Have We Learned?
Kurt Takara, Chris Kwok - Mentor Graphics Corp.
Anindya Chakraborty, Naman Jain, Ashish Hari - Mentor Graphics Pvt. Ltd., India
4.34 Automation of Power On Reset Assertion
Shang-Wei Tu, Penny Yang - MediaTek, Inc.
Joydeep Gangopadhyay, Amol Herlekar - Synopsys (India) Pvt. Ltd.
4.35 PA-APIs: Looking Beyond Power Intent Specification Formats
Amit Srivastava, Awashesh Kumar - Mentor Graphics Pvt. Ltd., India
4.36 Let’s DisCOVER Power States
Pankaj K. Dwivedi, Amit Srivastava, Veeresh Singh - Mentor Graphics Pvt. Ltd., India
DVCON.ORG
23
TUESDAY, MARCH 3
SPONSORED LUNCHEON - INDUSTRY LEADERS VERIFY
WITH SYNOPSYS
Time: 12:00pm - 1:15pm | Room: Pine/Cedar
Organizers:
Michael Sanie - Synopsys, Inc.
Helene Thibieroz - Synopsys, Inc.
Synopsys has worked with SoC leaders to define and deploy breakthrough technologies
that not only increase the speed and throughput of verification but also offer innovative
approaches to avoid bugs altogether, detect them as early as possible and debug more
efficiently, as well as advanced technology to accelerate software bring up and validation.
At this luncheon, you will hear industry experts share their viewpoints on what is driving
SoC complexity, how their teams have achieved success, how you can apply their
insights on your next project as well as discussions about the latest developments in the
verification landscape and groundbreaking technology.
Sponsored by:
24
DVCON.ORG
TUESDAY, MARCH 3
KEYNOTE - SMART DESIGN FROM SILICON TO SOFTWARE
Time: 1:30pm - 2:30pm | Room: Oak/Fir
In our current semiconductor design community, the word
“change” is, to say the least, an understatement. From a dizzying
array of emerging “smart” niche end-products to major market
trend shifts to ecosystem reconfigurations at every level, the world
around us is morphing at an unprecedented pace. The challenge
for IC designers to keep pace has never been greater. The good
news is that we’re up for it!
Aart de Geus
Chairman &
co-Chief
Executive
Officer
- Synopsys, Inc.
In his presentation, Aart will address the business and technology
trends that are stretching designers’ concerns beyond the traditional
sand boxes of design and verification.
Since co-founding Synopsys in 1986, Dr. de Geus has expanded
Synopsys from a start-up synthesis company to a global
high-tech leader.
Long considered a pioneer in our industry, he’s been recognized for
his technical, business and community achievements with multiple awards, including:
• Electronic Business Magazine’s “CEO of the Year”
• The IEEE Robert N. Noyce Medal,
• The GSA Morris Chang Exemplary Leadership Award,
• The Silicon Valley Engineering Council Hall of Fame Award, and
• The SVLG Lifetime Achievement Award
He serves on the Boards of the Silicon Valley Leadership Group, Applied Materials, the
Global Semiconductor Alliance, and the Electronic Design Automation Consortium.
DVCON.ORG
25
TUESDAY, MARCH 3
SESSION 5 - TESTBENCH CONSTRUCTION
Time: 3:00pm - 5:00pm | Room: Oak
Chair: Dave Rich - Mentor Graphics Corp.
5.1 Automatic SOC Test Bench Creation
David Crutchfield - Cypress Semiconductor Corp.
5.2Application Abstraction Layer: The Carpool Lane on the
SoC Verification Freeway
Subramanian Kuppusamy - Qualcomm, Inc.
Varun Sundaran, Abhisek Verma - Synopsys, Inc.
5.3 An Easy VE/DUV Integration Approach
Uwe Simm - Cadence Design Systems, Inc.
5.4A Unified Testbench Architecture Solution for Verifying Variants
of the PLL IP
Deepa Ananthanarayanan, Malathi Chikkanna - Advanced Micro Devices, Inc.
SESSION 6 - ADVANCED TECHNIQUES
Time: 3:00pm - 5:00pm | Room: Fir
Chair: Dave Rich - Mentor Graphics Corp.
6.1Parameterized and Re-Usable Jitter Model for Serial
and Parallel Interfaces
Malathi Chikkanna, Amlan Chakrabarti - Advanced Micro Devices, Inc.
6.2 SVAssertions for CDC Data
Don Mills - Microchip Technology, Inc.
6.3Automated Performance Verification to Maximize Your ARMv8
Pulling Power
Nicholas A. Heaton - Cadence Design Systems, Inc.
Simon Rance - ARM Ltd.
6.4 Addressing the Challenges of Reset Verification in SoC Designs
Chris Kwok, Priya Viswanathan, Ping Yeung - Mentor Graphics Corp.
26
DVCON.ORG
TUESDAY, MARCH 3
SESSION 7 - MULTI-LANGUAGE
Time: 3:00pm - 5:00pm | Room: Monterey/Carmel
Chair: Karen Pieper - Tabula, Inc.
7.1 Co-Simulating Matlab/Simulink Models in a UVM Environment
Neal H. Okumura, Paul Yue - Raytheon Company
Glenn Richards - Mentor Graphics Corp.
7.2 Portable Stimulus Models for C/SystemC, UVM and Emulation
Mike Andrews - Mentor Graphics Corp.
Boris Hristov - Ciena, Corp.
7.3Parameter Passing from SystemVerilog to SystemC for Highly
Configurable Mixed-Language Designs
Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, ChandraSekhar Katuri,
Pradipta Laha - Cadence Design Systems, Inc.
7.4Methodology to Port a Complex Multi-Language Design and Testbench
to Simulation Acceleration
Horace Chan, Brian Vandegriend, Jason Kwan - PMC-Sierra, Inc.
Efrat Shneydor - Cadence Design Systems, Inc.
DVCON.ORG
27
WEDNESDAY’S AGENDA
8:30 - 9:30am
PANEL: Art or Science?
Location: Oak/Fir
10:00 - 11:30am
SESSION 8: Low Power Verification
Location: Oak
SESSION 9: Verification Process & Resource Management
Location: Fir
SESSION 10: User Perspectives
Location: Monterey/Carmel
11:30am - 12:45pm
SPONSORED LUNCHEON: From Tightly Coupled (Loosely
Bolted) to Verification Convergence!
Sponsored by:
Location: Pine/Cedar
1:00 - 2:00pm
PANEL: SystemC –– Forever a Niche Player or Rising Star of Chip Design?
Location: Oak/Fir
2:30 - 6:00pm
DVCON EXPO
Location: Bayshore Ballroom
2:30 - 4:30pm
SESSION 11: Formal and Semi-Formal Techniques
Location: Oak
SESSION 12: UVM
Location: Fir
SESSION 13: Coverage
Location: Monterey/Carmel
4:45 - 5:00pm
Best Paper & Poster Awards Presentations
Location: Oak/Fir
5:00 - 6:00pm
DVCON RECEPTION
Location: Bayshore Ballroom
28
DVCON.ORG
Sponsored by:
WEDNESDAY, MARCH 4
PANEL - ART OR SCIENCE?
Time: 8:30am - 9:30am | Room: Oak/Fir
Moderator:
Brian Bailey - Semiconductor Engineering
Organizer:
Liz Massingill - Lee Public Relations
The amount of time spent on verification has steadily risen such that it now consumes
more time and resources than the design itself. The primary reason cited for this is that
verification is a larger problem than design and can never be completed. At the same
time, there are many aspects of the verification flow that are manual and these require
significant knowledge and experience both of verification methodologies and the design.
This has led to the perception that verification is an art and one which is difficult
to master.
With the emergence of the Internet of Things, and in particular the embedded edge
devices to support the IoT, many aspects of the design flow and its economics are
changing, creating an opportunity to rethink the verification process. In addition, the
maturing of formal methods is providing a richer tool suite than we have had in the past.
Is it possible to take some of the art out of verification, or to provide additional tools that
would help engineers to master the art?
Panelists:
Janick Bergeron - Synopsys, Inc.
Harry Foster - Mentor Graphics Corp.
JL Gray - Cadence Design Systems, Inc.
Ken Knowlson - Intel Corp.
Bernard Murphy - Atrenta Inc.
DVCON.ORG
29
WEDNESDAY, MARCH 4
SESSION 8 - LOW POWER VERIFICATION
Time: 10:00am - 11:30am | Room: Oak
Chair: Dan Benua - Synopsys, Inc.
8.1 Multi-Domain Verification: When Clock, Power and Reset Domains Collide
Ping Yeung, Erich Marschner - Mentor Graphics Corp.
Kaowen Liu - MediaTek, Inc.
8.2Successive Refinement: A Methodology for Incremental Specification of
Power Intent
Adnan Khan, Eamonn Quigley, John Biggs - ARM Ltd.
Erich Marschner - Mentor Graphics Corp.
8.3UPF Code Coverage and Corresponding Power Domain
Hierarchical Tree for Debugging
Shang-Wei Tu - MediaTek, Inc.
Tom Lin, Archie Feng, Ya Ping Chen - Synopsys, Inc.
SESSION 9 - VERIFICATION PROCESS & RESOURCE
MANAGEMENT
Time: 10:00am - 11:30am | Room: Fir
Chair: Harry Foster - Mentor Graphics Corp.
9.1 Standard Regression Testing Does Not Work
Daniel Hansson - Verifyter AB
9.2Advanced Usage Models for Continuous Integration in
Verification Environments
John Dickol - Samsung Austin R&D Center
9.3 Mining Coverage Data for Test Set Coverage Efficiency
Monica C. Farkash, Balavinayagam Samynathan - Univ. of Texas at Austin
Bryan Hickerson, Michael Behm - IBM Corp.
SESSION 10 - USER PERSPECTIVES
Time: 10:00am - 11:30am | Room: Monterey/Carmel
Chair: Logie Ramachandran - VeriKwest Systems Inc.
10.1 I Created the Verification Gap
Ram Narayan, Tom Symons - Oracle Labs
10.2 Lies, Damned Lies, and Coverage
Mark Litterick - Verilab, Inc.
10.3 Whatever Happened to AOP?
James P. Strober - Ciena, Corp.
Corey Goss - Cadence Design Systems, Inc.
30
DVCON.ORG
WEDNESDAY, MARCH 4
SPONSORED LUNCHEON - FROM TIGHTLY COUPLED
(LOOSELY BOLTED) TO VERIFICATION CONVERGENCE!
Time: 11:30am - 12:45pm | Room: Pine/Cedar
Speakers:
Harry Foster - Mentor Graphics Corp.
Stephen Bailey - Mentor Graphics Corp.
This session will discuss the state of verification past, present and future while examining
the results from a recent industry world-wide verification study. The talk will examine
how advanced techniques are taking hold in mainstream design and provide insights on
the recent convergence of verification solutions to meet today’s growing challenges.
Sponsored by:
DVCON.ORG
31
WEDNESDAY, MARCH 4
PANEL - SYSTEMC -- FOREVER A NICHE PLAYER OR RISING STAR
OF CHIP DESIGN?
Time: 1:00pm - 2:00pm | Room: Oak/Fir
Moderator:
Bryon Moyer - EE Journal
Organizer:
Dave Kelf - OneSpin Solutions GmbH
Although SystemC, as well as C, C++ and OpenCL, has seen success for niche
opportunities at a number of semiconductor companies, its adoption as the language of
choice for entire designs remains rare. C derivative languages appear to have advantages
in such applications as DSP algorithm development, transaction-level design, and virtual
platform models. Some FPGA vendors have realized C-based design flows for a number of
their devices. Some ASIC tool vendors support C based design flows as well.
Yet, barriers to adoption remain for the generalized usage of these languages. Is it
immature verification methodologies, fundamental flaws in the language specification, or
simply the inertia of the standard HDLs that holds back SystemC? SystemC may be good
for describing a block at an abstract level, but it is good for IP assembly? Most IP exists
at RTL, so a high level language has to be able to fully incorporate that if it wants to plat
at the top. Should Accellera be urged to do more to encourage SystemC adoption? Is the
industry overlooking the perfect application for SystemC?
Let’s check with technology leaders driving the state-of-the-art in SystemC Verification,
Synthesizable Intellectual Property, FPGA Design Flows and Virtual Platforms. They
will attempt to determine if there is a consensus on adoption requirements, or a
disagreement on flow deficiencies.
Panelists:
Raik Brinkmann - OneSpin Solutions GmbH
Michael McNamara - Adapt-IP
Victoria Mitchell - Altera Corp.
Bill Neifert - Carbon Design Systems, Inc.
32
DVCON.ORG
WEDNESDAY, MARCH 4
SESSION 11 - FORMAL AND SEMI-FORMAL TECHNIQUES
Time: 2:30pm - 4:30pm | Room: Oak
Chair: Erik Seligman - Intel Corp.
11.1Detecting Harmful Race Conditions in SystemC Models Using
Formal Techniques
Dominik Strasser, Sven Beyer - OneSpin Solutions GmbH
11.2 Automatic Generation of Formal Properties for Clock Gating Related Logic
Shuqing Zhao, Shan Yan - Broadcom Corp.
11.3 Every Cloud - Post-Silicon Bug Spurs Formal Verification Adoption
Blaine Hsieh - Faraday Technology Corp.
Stewart Li, Mark Eslinger - Mentor Graphics Corp.
11.4Double the Return From Your Property Portfolio: Reuse of Verification
Assets From Formal to Simulation
Jonathan Bromley - Verilab Ltd.
SESSION 12 - UVM
Time: 2:30pm - 4:30pm | Room: Fir
Chair: Mark Azadpour - Western Digital Corp.
12.1 UVM Rapid Adoption: A Practical Subset of UVM for Design Verification
Stuart Sutherland - Sutherland HDL, Inc.
Tom Fitzpatrick - Mentor Graphics Corp.
12.2 UVM’s MAM to the Rescue
Michael Baird - Willamette HDL, Inc.
12.3 Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?
John Aynsley - Doulos
12.4 UVM Sans UVM - An Approach to Automating UVM Testbench Writing
Rich Edelman, Shashi Bhutada - Mentor Graphics Corp.
REMEMBER TO VOTE!
ote
Best Paper & Poster
Deadline:
Wednesday, March 4, 4:30pm
DVCON.ORG
33
WEDNESDAY, MARCH 4
SESSION 13 - COVERAGE
Time: 2:30pm - 4:30pm | Room: Monterey/Carmel
Chair: Imtiyaz Ron - Broadcom Corp.
13.1 Table-Based Functional Coverage Management for SOC Protocols
Shahid Ikram, Isam Akkawi, Jack Perveiler, Jim Ellis, David Asher - Cavium, Inc.
13.2 Coverage Driven Generation of Constrained Random Stimuli
Marat Teplitsky, Amit Metodi, Raz Azaria - Cadence Design Systems, Inc.
13.3Method for Generating Unique Coverage Classes to Enable Meaningful
Covergroup Merges Across Testbenches
Eldon G. Nelson - Micron Technology, Inc.
13.4Navigating the Functional Coverage Black Hole: Be More Effective at
Functional Coverage Modeling
Paul Marriott, Jason Sprott - Verilab, Inc.
Matt Graham - Cadence Design Systems, Inc.
BEST PAPER & POSTER AWARDS PRESENTATIONS
Time: 4:45pm - 5:00pm | Room: Oak/Fir
2015 Recipients of the Best Paper and Poster are announced by
Technical Program Chair, Ambar Sarkar.
Sponsored by:
34
DVCON.ORG
THURSDAY’S AGENDA
8:30 - 12:00pm
TUTORIAL 5: Advanced, High-Throughput Debug from
Architectural Modeling Through Post-Silicon SoC Validation
Sponsored by:
Location: Donner
TUTORIAL 6: Applying “Re-Use” Principles with an Open
Debug Environment to Shrink SoC Schedules and Budgets
Sponsored by:
TUTORIAL 7: Verification 501: Graduate-Level
Debug Tutorial
Sponsored by:
Location: Siskiyou
Location: Cascade
12:00pm - 1:30pm
SPONSORED LUNCHEON: Mastering Verification and
Debug Productivity
Sponsored by:
Location: Bayshore Ballroom
2:00 - 5:30pm
TUTORIAL 8: Dead or Alive: Using Automated Formal
Techniques to Characterize Dead Code, Reveal Paths to
Hit Uncovered States, and Reach Coverage Closure Faster
Sponsored by:
TUTORIAL 9: High Performance Emulation for SoC
Verification and Early Software Bring-Up
Sponsored by:
Location: Donner
Location: Siskiyou
TUTORIAL 10: Verification Solutions for ARM v7/v8
Based Systems on Chips
Sponsored by:
Location: Cascade
COFFEE BREAKS
Location: Gateway Foyer
• 8:00 - 11:00am
• 3:00 - 4:00pm
Parking Information: There are two pay stations inside the hotel. One is located near the convention
entrance (Bayshore Foyer) side and this machine accepts both cash and credit card. The second pay
station is located near the guest elevators near the South Parking Lot. This machine accepts only cash.
Overnight self parking is $10.00 per day/per car with no in/out privileges.
DVCON.ORG
35
THURSDAY, MARCH 5
TUTORIAL 5 - ADVANCED, HIGH-THROUGHPUT DEBUG
FROM ARCHITECTURAL MODELING THROUGH POST-SILICON
SOC VALIDATION
Time: 8:30am - 12:00pm | Room: Donner
Organizer:
Rebecca Granquist - Mentor Graphics Corp.
Ongoing improvements in verification compute engine performance have unintentionally
created a whole new verification challenge: dealing with an avalanche of data for D&V
engineers to process. While methodologies like coverage-driven test ranking and
sophisticated checkers can help focus the verification results on the most high-value
data points, a real live person must still sift through the all output and navigate the failure
analysis – bug identification – fix – validate cycle. In a nutshell, the debug challenge is
big and is only growing. Indeed, based on semi-annual customer surveys debug is now
exceeding 36% of an engineer’s time, which is more than any other single verification
task. Clearly, improving debug productivity from block to system pre-silicon verification,
virtual prototyping, emulation, as well as post-silicon validation is critical to stay on
schedule and simultaneously meet quality goals.
In this tutorial we show how you can significantly improve debug productivity in the
context of the following recommendations:
1 - Leverage new debug technologies to expedite causality discovery
2 - Raise the level of abstraction whenever possible - Find bugs as early as possible before
time-consuming, resource-intensive regressions are launched
3 - Apply low-power debug techniques in every D&V phase
4 - Employ advanced tools for multi-core embedded SW/HW debug and
performance tuning
5 - Extend these debug techniques to Post-Silicon validation
Throughout the tutorial, live demos and customer case studies will be employed to
illustrate the effectiveness of these recommendations in real world projects.
Speakers:
Tom Fitzpatrick - Mentor Graphics Corp.
Ellie Burns - Mentor Graphics Corp.
Russ Klein - Mentor Graphics Corp.
Eric Rentschler - Mentor Graphics Corp.
Sponsored by:
36
DVCON.ORG
THURSDAY, MARCH 5
TUTORIAL 6 - APPLYING “RE-USE” PRINCIPLES WITH AN
OPEN DEBUG ENVIRONMENT TO SHRINK SOC SCHEDULES
AND BUDGETS
Time: 8:30am - 12:00pm | Room: Siskiyou
Organizer:
Steve Chappell - Synopsys, Inc.
Re-use of IP and VIP is now universally recognized as necessary to handle the ever
increasing content and complexity of today’s SOCs. The question now becomes whether
we can apply “re-use” to boost productivity in other areas of an SOC project. When we look at what engineers do on a day-to-day basis, we find that there is one
thing that dominates the efforts of practically all engineers – hardware, software, analog,
digital, verification, or design – and that’s debug. Engineers spend roughly 50% of their
time doing debug, and if you add in “analysis,” the percentage of effort approaches
65%. It also turns out that across domains, job functions, languages, and engines, there
are commonalities that can be leveraged in the debug and analysis efforts to boost
productivity of all engineering teams.
In this tutorial, we will look at how a common and open platform for debug and analysis
can shrink the overall engineering time and effort required to produce a complex SOC. We will walk through examples of how this bridges the gaps in the process - including
moving from virtual prototyping to formal analysis to simulation to emulation to
prototyping - as well as the knowledge and language gaps between teams – including
architecture, analog/mixed-signal, design, verification, and software teams. We will also
share examples of how this creates a productive eco-system by providing open APIs to
enable custom script and 3rd party tool integrations.
Speakers:
Joerg Richter - Synopsys, Inc.
Archie Feng - Synopsys, Inc.
Sponsored by:
DVCON.ORG
37
THURSDAY, MARCH 5
TUTORIAL 7 - VERIFICATION 501: GRADUATE-LEVEL
DEBUG TUTORIAL
Time: 8:30am - 12:00pm | Room: Cascade
Organizer:
Kishore Karnane - Cadence Design Systems, Inc.
Welcome returning students! In last year’s “Revolutionary Debug Techniques to Improve
Verification Productivity” tutorial we focused on moving beyond printf to use interactive
and post-processing techniques to make debugging environments like those built with
UVM more efficient. This year’s tutorial will concentrate more on complex RTL, TB, and
SoC level debugging tasks.
RTL debug continues to grow in complexity as the design becomes larger and utilizes
more SystemVerilog design constructs. In addition, software executing on the processors
in a design, becomes more important both as functional content and part of the
testbench. Often, the gap between the actual failure and the failure detection is very large
in terms of clock cycles and distance through the design. Users need advanced tools to
trace signals, to go-to-the root cause of the failure, and to apply formal techniques to
identify the bugs. Today, with all of these complexities, it is critical that debug automation
is in place to guide users in the debug process through the TB and RTL to find the root
cause of an issue.
Additionally, the fast-growing application of assertion-based formal verification presents
its own unique debug challenges. Rather than debug traces from a testbench, users
need to ask “what if” questions to understand the design, and be able to efficiently trace
through a property’s cone of influence to understand issues.
The tutorial session will also cover topics including:
• RTL debug using simulation and formal engines
• UVM debug
• HW/SW debug using simulation and hardware engines
We will explore novel debug methodologies that will allow you to:
• Step forward or backward through the simulation, or jump to a specific point in the
simulation in a single click
• Be more efficient debugging UVM environments
• Clearly visualize, explore and debug your formal environment
• Debug HW and SW using the same debugger on multiple engines
Speakers:
Kishore Karnane - Cadence Design Systems, Inc.
Corey Goss - Cadence Design Systems, Inc.
Sponsored by:
38
CONNECT WITH DVCON SOCIAL MEDIA
FOLLOW US ON TWITTER
HOURLY UPDATES DURING
CONFERENCE KEEP YOU
POSTED ON ALL THE ACTION!
#DVCON
LIKE US ON FACEBOOK
TAP INTO THE LATEST DVCON NEWS
FACEBOOK.COM/DVCON
DVCON.ORG
39
THURSDAY, MARCH 5
SPONSORED LUNCHEON - MASTERING VERIFICATION AND
DEBUG PRODUCTIVITY
12:00pm - 1:30pm | Room: Bayshore Ballroom
In this luncheon session, we will invite industry verification experts to join us in a panel
discussion to highlight their overall SoC verification and debug challenges as well as
some of the solutions/debug methodologies that they have adopted to improve their
overall productivity, including SoC level verification.
As we all know, SoC debug is becoming a very challenging verification effort. It is critical
that debug automation is in place to guide users in the debug process through the
TB, RTL, VIP, Formal and HW/SW debug to find the root cause of an issue. Users need
advanced tools and methodologies to trace signals, to go-to-cause, and to apply formal
techniques to identify the bugs.
Also, on the VIP Debug front, visualization and abstraction of the protocol traffic and
events captured like transactions, packages, queues, states, is needed to be able to
make sense of complex protocol bugs. Users need to debug protocol context-specific
information as well as be able to filter debug info per user’s preference.
Generation of tests needs to take into account top-down SoC integration aspects.
Verification environments need to be reused vertically from IP to sub-system to SoCs.
Scenarios are to be exchanged between architects, hardware, software, verification and
post silicon validation engineers. And verification stimulus needs to be portable across all
validation engines from virtual through RTL, emulation, FPGA and the actual silicon.
The panelists will debate the changing verification landscape and how to verify SoCs
top down, their best practices, methodologies and solutions to debug their digital,
mixed-signal, low-power, embedded software and their VIP all integrated in a unified
debug environment.
Panelists:
John Goodenough - ARM Ltd.
David Lacey - Hewlett-Packard Co.
Normando Montecillo - Broadcom Corp.
Sponsored by:
40
DVCON.ORG
THURSDAY, MARCH 5
TUTORIAL 8 - DEAD OR ALIVE: USING AUTOMATED FORMAL
TECHNIQUES TO CHARACTERIZE DEAD CODE, REVEAL
PATHS TO HIT UNCOVERED STATES, AND REACH COVERAGE
CLOSURE FASTER
Time: 2:00pm - 5:30pm | Room: Donner
Organizer:
Rebecca Granquist - Mentor Graphics Corp.
Achieving coverage closure goals on time and under budget is one of the most visible and
challenging assignments in functional verification today. Complicating this task is the
increasing popularity of platform-based design, where IPs are extensively parameterized
to enable end-user customization and differentiated derivatives. Unfortunately, this
design style can inadvertently create hundreds, thousands, even tens of thousands of
pockets of dead code. But how can you be sure a given block of DUT RTL code is properly
dead due to a legal configuration choice, should be alive but is actually unreachable by
any means, or just hasn’t been illuminated by coverage yet?
Fortunately, the exhaustive nature of formal analysis can be employed to help verifiers
address these challenges – simultaneously staying on schedule as well as improving end
product quality. Specifically, in this tutorial we will describe how a mix of formal apps
and methodology can be applied to characterize acceptable and unacceptable dead DUT
RTL code, quickly show how to hit uncovered DUT states, and to reach overall coverage
closure faster. Topics will include:
• A level-setting primer on all coverage types
• A brief review of how various forms of coverage are recorded in the Unified Coverage
Database (UCDB), as per the Accellera Unified Coverage Interoperability Standard (UCIS)
• Dead code and “unreachability” analysis for highly configurable DUTs
• SystemVerilog CoverGroup coding: striking the right balance
• Approximating the ideal assertion density for simulation& formal
Each topic will be described in the context of a real-world case study.
Speakers:
Joe Hupcey III - Mentor Graphics Corp.
Mark Eslinger - Mentor Graphics Corp.
Kurt Takara - Mentor Graphics Corp.
Nguyen Le - Microsoft Corp.
Thomas Ellis - Mentor Graphics Corp.
Balasubramani Chandrashekaran - Micron Technology, Inc.
Sponsored by:
DVCON.ORG
41
THURSDAY, MARCH 5
TUTORIAL 9 - HIGH PERFORMANCE EMULATION FOR SOC
VERIFICATION AND EARLY SOFTWARE BRING-UP
Time: 2:00pm - 5:30pm | Room: Siskiyou
Organizer:
Tom Borgstrom - Synopsys, Inc.
As SoCs have grown in size and complexity, so has the challenge of verifying them.
The emergence of Internet of Things and the proliferation of mobile devices and cloud
infrastruture have made early software bring-up as well as power and performance
validation necessary components of the SoC design process. In addition, large SoC
designs often need long-running tests that cannot be divided up and run on traditional
software simulators in a reasonable amount of time. These trends have made highperformance emulators an indispensable part of today’s verification toolkit, providing a
simulator-like environment capable of running and debugging software and verification
workloads for full SoC and subsystems.
This tutorial is targeted at SoC verification architects and engineers looking to take
advantage of multi-megahertz emulation performance for their next project. We will
explore how the ZeBu Server-3 emulation system can be used to speed SoC software
bring-up and accelerate the overall SoC verification process. We will cover several
emulation use cases in depth such as simulation acceleration, power-aware emulation
and hybrid emulation with virtual prototypes. In addition, we’ll present practical case
studies of how high-performance emulation has been used on recent customer designs.
Speakers:
Per Edstrom - Synopsys, Inc.
Shantanu Ganguly - Synopsys, Inc.
Nathan Womack - Synopsys, Inc.
Sponsored by:
42
DVCON.ORG
THURSDAY, MARCH 5
TUTORIAL 10 - VERIFICATION SOLUTIONS FOR ARM
V7/V8 BASED SYSTEMS ON CHIPS
Time: 2:00pm - 5:30pm | Room: Cascade
Organizer:
Frank Schirrmeister - Cadence Design Systems, Inc.
Developers are facing ARM® based processor architectures in a large variety of devices,
from sensors through mobile and consumer devices all the way to networking and servers
enabling cloud based applications. ARM based designs include more and more processor
cores, more IP, complex power control, coherent interconnect, and complex software
controlled operations.
As a result, verification is undergoing a transformation to novel software driven approaches,
introducing unique challenges in terms of writing tests for the complex interactions at
the subsystem and SoC level. Ensuring that expected performance targets are achieved
is becoming more and more difficult due to the number of processors and the expanding
configuration choices of system interconnect. Developing hardware and software in
parallel is often facing significant barriers: suitable models for all the IP blocks may not be
available and when they are available then they may be in RTL only, lacking corresponding
transaction-level models.
This tutorial will take a close look at state-of-the-art solutions to address these SoC
level challenges and demonstrate a comprehensive flow on how to optimize, verify and
accelerate hardware and software development for ARM based systems, illustrated through
use of case studies where these approaches have been utilized in practice.
We will introduce innovative approaches to software driven verification, building on proven
model based software testing approaches, allowing to capture system actions, preconditions, post conditions and resource requirements to validate SoC level features and
generate portable stimuli including coverage analysis.
We will also discuss how you can achieve 10X faster SoC performance analysis and
verification of ARM CoreLink IP-based systems with Cadence Interconnect WorkBench and
our expanded verification IP portfolio, featuring support for ARM AXI4/ACE and
AMBA ® 5 CHI for all simulators and Palladium® XP II, as well as assertion-based Intelligent
Proof Kits for formal verification.
Finally, we will cover ARMv8 64-bit and v7 32-bit Cortex® based embedded OS and above
OS software development, testing and validation with the Palladium® Hybrid solution.
Speakers:
Frank Schirrmeister - Cadence Design Systems, Inc.
Larry Melling - Cadence Design Systems, Inc.
Sharon Rosenberg - Cadence Design Systems, Inc.
Nick Heaton - Cadence Design Systems, Inc.
Raj Mathur - Cadence Design Systems, Inc.
Leonard Drucker - Cadence Design Systems, Inc.
DVCON.ORG
Sponsored by:
43
THANK YOU TO OUR EVENT SPONSORS!
NAME-BADGE LANYARD
paradigm-works.com
BEST PAPER & POSTER SPONSOR
verilab.com
MEDIA SPONSORS
chipdesignmag.com
edacafe.com
intelligentsystemssource.com
44
DVCON.ORG
BOOTH CRAWL SPONSORS
cadence.com
amiq.com
cliosoft.com
oskitechnology.com
smart-dv.com
s2cinc.com
synopsys.com
testandverification.com
zocalo-tech.com
xpeerant.com
DVCON.ORG
45
EXPO INFORMATION
DVCON EXPO 2015
Collaborate with vendors at the pinnacle of innovation!
Learn about new, cutting-edge technology, network with vendors well-tuned to today’s
verification needs, and see how collaboration can take your design to the next level.
CON
2
DV
5
01
&
C
C o
on ckt
ve ails ns
rsatio
EXHIBIT HOURS
Monday, March 2, 5:00 - 7:00pm
Join us for the 2nd annual booth crawl!
Tuesday, March 3, 2:30 - 6:00pm
Wednesday, March 4, 2:30 - 6:00pm
DVCON 2015 EXHIBITORS
Agnisys, Inc.
302
PRO DESIGN Electronic GmbH
Aldec, Inc.
401
Real Intent, Inc.
602
AMIQ EDA
405
305
Atrenta Inc.
704
*Rocketick, Inc.
S2C Inc.
Avery Design Systems
904
Semifore Inc.
502
Sibridge Technologies
304
*SmartDV Technologies
*Sunburst Design
404
*Sutherland HDL, Inc. Synopsys, Inc.
902
Blue Pearl Software
1005
Breker Verification Systems, Inc.
905
Cadence Design System, Inc.
505
Calypto Design Systems
402
*ClioSoft Inc.
Dini Group
805
Doulos, Inc.
501
604
EDACafe1101
1103
*Magillem SA
*Mathworks804
Mentor Graphics Corp.
801
OneSpin Solutions GmbH
701
Oski Technology
205
Paradigm Works, Inc.
601
1102
504
902
101
*Test and Verification Solutions
Limited1004
Truechip Solutions Pvt. Ltd.
1002
*VeriFast1105
Verific Design Automation
802
Verification Academy
301
*Verifyter1104
*Xpeerant1207
Zocalo Tech
702
* Denotes first-time exhibitor
DVCON.ORG
47
EXHIBITOR FLOORPLAN
NETWORKING RECEPTIONS
CON
2
DV
5
01
C
C o
on ckt
ve ails ns
rsatio
&
Monday, March 2, 5:00 - 7:00pm
2nd Annual Booth Crawl
Tuesday, March 3, 5:00 - 6:00pm
Networking Reception
Wednesday, March 4, 5:00 - 6:00pm
Networking Reception
One of the main reasons you came to DVCon: NETWORKING!
Introduce yourself and leave DVCon with a deeper professional network!
48
DVCON.ORG
EXHIBITOR LISTING
Agnisys, Inc.
Booth: 302 • Agnisys.com
Agnisys products help semiconductor companies create correct-by-construction
hardware specifications and code that lead to an error-free, fast and simple development
process.
IDesignSpec helps create correct Registers, Sequences and Ports and generate VHDL,
Verilog, UVM, C/C++ API and datasheets.
IVerifySpec helps teams manage verification projects with self-updating verification plans.
DVinsight is a smart-editor with a built in linter for SV/UVM that helps novice and expert
engineers find their way around UVM and avoid spending time chasing silly errors in
the code.
Aldec, Inc.
Booth: 401 • Aldec.com
Established in 1984, Aldec is global industry leader in Electronic Design Verification.
Aldec offers a patented technology suite including: RTL Design, RTL Simulators,
Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP
Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/
Aerospace solutions.
AMIQ EDA
Booth: 405 • Amiq.com, Dvteclipse.com
AMIQ EDA provides design and verification engineers with platform-independent software
tools that enable them to increase the speed and quality of new code development,
simplify legacy code maintenance, accelerate language and methodology learning,
improve testbench reliability, extract automatically accurate documentation, and
implement best coding practices.
Its solutions, DVT Eclipse IDE, Verissimo SystemVerilog Testbench Linter, and Specador
Documentation Generator have been adopted worldwide. AMIQ strives to deliver high
quality solutions and customer service responsiveness, while maintaining a friendly and
flexible environment.
DVCON.ORG
49
EXHIBITOR LISTING
Atrenta Inc.
Booth: 704 • Atrenta.com
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and
electronic systems industries. Patented solutions provide early design insight into the
demanding performance, power and area requirements of SoC’s. More than two hundred
and seventy five companies and thousands of design engineers worldwide rely on
SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the
addition of BugScope™, verification efficiency is also enhanced, allowing engineers and
managers to find the fastest and least expensive path to silicon for complex SoCs.
Avery Design Systems
Booth: 904 • Avery-design.com
Avery is a leader in functional verification solutions. SimXACT is a comprehensive,
patented solution to automatically detect X bugs in RTL and gate-level simulation due to
X-optimism and X-pessimism issues. Reset Optimization (ResetOPT) minimizes routing
and area overhead by automatically selecting a subset of registers to reset while ensuring
deterministic (non-X) hardware/software reset state.
Avery is a leader in Verification IP providing robust models, protocol checking, compliance
testsuites, advanced UVM environment, and verification services for advanced protocols
including PCI Express, USB/xHCI, UAS/BOT, UFS/UFSHCI, NVMe, SOP/PQI, SATA Express,
SATA, UniPro, Soundwire, eMMC, SDIO, DDR4/LPDDR3, HMC, ONFI/Toggle, CAN FD, and
ACE/AXI3/AXI4/AHB.
Blue Pearl Software
Booth: 1005 • Bluepearlsoftware.com
Blue Pearl Software accelerates IP and FPGA verification. Its User Grey Cell™ methodology
for CDC analysis fills holes in current IP-based design flows, and together with Advanced
Clock Environment (ACE) ™ identifies CDC issues that induce metastability.
The Blue Pearl Software Suite checks RTL designs for functional errors and automatically
generates SDC constraints to improve quality of results. The Blue Pearl suite is integrated
with FPGA vendor flows, is easy to use and runs on Windows® and Linux®.
For more information about Blue Pearl Software, please visit Bluepearlsoftware.com.
50
DVCON.ORG
EXHIBITOR LISTING
Breker Verification Systems, Inc.
Booth: 905 • Brekersystems.com
Breker’s Trek family of products and apps automatically generates multi-threaded test
cases that verify your chip design more quickly and more thoroughly. These test cases
are portable from IP to full multiprocessor system-on-chip (SoC), and from simulation
and in-circuit emulation (ICE) to silicon. They verify all aspects of chip functionality, with
a focus on cache coherency, system stress, and performance. Your verification engineers,
embedded programmers, and bring-up team no longer have to hand-write throw-away
tests, freeing them for revenue-generating tasks.
Cadence Design System, Inc.
Booth: 505 • Cadence.com
Cadence is a global leader in software, hardware, design and verification IP, and services
that are transforming the semiconductor industry. Cadence embraces the entire
spectrum of the electronic design process and develops technologies that enhance
productivity and end-product profitability. Our apps-driven approach to creating,
integrating, and optimizing electronic designs helps customers develop innovative silicon
chips, system-on-chip devices, and complete systems at lower cost and with higher
quality.
Calypto Design Systems
Booth: 402 • Calypto.com
Calypto® Design Systems is a leading provider of tools for high-level synthesis, RTL
power analysis and optimization, and sequential logic equivalency checking. High-level
synthesis is an essential methodology
for IP development where algorithms and implementations must evolve at a rapid
pace, as often occurs in applications such as HEVC, image processing, and advanced
communication products amongst many others. Calypto’s patented, deep sequential
analysis technology finds low-power optimizations in RTL that other solutions miss,
resulting in optimal power-efficient RTL. Calypto has offices in Europe, India, Japan,
Korea, and North America with representation in China, Israel, and Taiwan.
DVCON.ORG
51
EXHIBITOR LISTING
ClioSoft Inc.
Booth: 805 • Cliosoft.com
The SOS Design Collaboration Platform from ClioSoft is the leading SoC design data and
IP management platform for digital, analog, RF and mixed-signal designs. SOS provides
a sophisticated multi-site development environment that enables global team design
collaboration and efficient management of design data from concept through tape-out.
SOS is integrated with leading design flows –Cadence’s Virtuoso® technology, Keysight
Technologies’ Advanced Design System (ADS), Mentor Graphic’s Pyxis Custom IC Design,
Synopsys’ Galaxy Custom Designer® and Laker3™ Custom Design. SOS also includes
enterprise IP management which enables companies to improve design reuse within their
company by efficiently managing the IPs. IP Management from ClioSoft comes equipped
with an easy to use administration and user cockpit to manage the process of creating IPs
and its derivatives, their lineage, IP licensing, security, issue and defect tracking. Support
for different work models, including ECO flows & IP Management, makes SOS most
suitable to manage all design data from RTL to GDSII.
Dini Group
Booth: 604 • Dinigroup.com
Located in La Jolla, California, The Dini Group is a professional hardware and software
engineering firm specializing in high performance digital circuit design and application
development focused on FPGA platforms for ASIC Prototyping, Algorithmic Acceleration,
High Performance Computing and High Speed/Low Latency Networking.”
Doulos, Inc.
Booth: 501 • Doulos.com
For over 20 years, Doulos has set the industry standard for developing and delivering
high quality training and KnowHow in electronic system design and verification, covering
languages and methodologies for system, hardware, and embedded software designers.
The essential choice for more than 2000 companies across over 50 countries, Doulos
provides scheduled classes across North America and Europe, and delivers on-site, teambased training and interactive online learning worldwide.
Find out more at Doulos.com
EDACafe
Booth: 1101 • Edacafe.com
EDACafe.Com is the #1 EDA web portal. Thousands of IC, SoC, FPGA, PCB, System
designers and top level decision-makers visit EDACafe.Com daily to learn about the latest
industry trends, design tools and services. Sign up for the industry’s best daily newsletter
at http://www10.edacafe.com/nl/newsletter_subscribe.php .
Contact sanjay@edacafe.com to book a video interview at the conference. Visit our booth
to sign up for a chance to win a KindleFire.
52
EXHIBITOR LISTING
Magillem SA
Booth: 1103• Magillem.com
Since its creation in 2006, Magillem has been the pioneer in leveraging business content
in top tier accounts worldwide and is a leading provider of front-end design xml solutions,
best-in-class tools to reduce the global cost of complex designs.
Magillem has been listed on Euronext Paris since 2009 (FR0010827741) and is trusted by
numerous clients like Altera, Renesas, Samsung, Qualcomm, NXP, ST Microelectronics,
Texas Instruments, Thales, NSN and Maxim integrated.
Magillem has 45 employees, including 40 engineers and PhDs in Research & Development
alone. It also has an office in Tokyo, 4 agencies in the United States (New York, Austin and
the San Francisco Bay area) and 8 distributors in Asia and Israel.
Mathworks
Booth: 804 • Mathworks.com
MathWorks is the leading developer of mathematical computing software. Engineers and
scientists worldwide rely on its products to accelerate the pace of discovery, innovation,
and development. MATLAB and Simulink are used throughout the automotive,
aerospace, communications, electronics, and industrial automation industries as
fundamental tools for research and development. They are also used for modeling and
simulation in increasingly technical fields, such as financial services and computational
biology. For more information visit mathworks.com
Mentor Graphics Corp.
Booth: 801 • Mentor.com
Mentor Graphics delivers the most comprehensive Enterprise Verification Platform (EVP),
which combines Questa® for high performance simulation, verification management and
coverage closure, low-power verification with UPF, CDC, Formal Verification, accelerated
functional coverage, and processor-based hardware verification, Veloce® OS3 global
emulation technology, and the Visualizer™ debug environment, to deliver performance
and productivity improvements ranging from 400X to 10,000X. For more information visit
www.mentor.com.
OneSpin Solutions GmbH
Booth: 701 • Onespin-solutions.com
OneSpin Solutions’ is a pioneer of advanced formal techniques to solve practical verification
challenges. The company’s award winning, leading technology enables a versatile range of
verification solutions. Products include easy to use, automated apps for the early detection
of design issues and targeted problems, comprehensive coverage-driven property analysis
for rigorous testing, and high accuracy equivalency checking for large FPGAs. OneSpin
solutions may be found at many of the leading electronics companies worldwide.
DVCON.ORG
53
EXHIBITOR LISTING
Oski Technology
Booth: 205 • Oskitech.com
Oski Technology is the world’s only dedicated formal verification service provider. Oski’s
Formal Sign-off Methodology™ uses end-to-end checkers, constraints, Oski Abstraction
Models™ and formal coverage metrics to catch corner case bugs, replace simulation
for the blocks verified, and improve overall verification efficiency. Oski has provided
formal verification services to many leading semiconductor companies including Cisco,
Cypress, NVIDIA, Rambus and Xilinx to tape out critical projects, establish formal sign-off
methodology and develop customer formal expertise. Oski is a formal sign-off company.
Paradigm Works, Inc.
Booth: 601 • Paradigm-works.com
Paradigm Works is a recognized provider of Chip Development Consulting Services
(Design and Verification), as well as Electronic Design Automation Free Open Source
Software (EDA FOSS) and Supported EDA Software. Paradigm Works Software and
Services can reduce development costs, quicken time-to-revenue, and reduce schedule
risk. Paradigm Works serves leading Systems and Semiconductor Companies worldwide.
PRO DESIGN Electronic GmbH
Booth: 1102 • Profpga.com
PRO DESIGN Electronic GmbH is creator of the proFPGA ASIC & IP Prototyping systems.
The proFPGA product family is a modular, highly flexible, scalable and high performance
multi FPGA solution. It is scalable in increments of 1 FPGA supporting different FPGA
types in one system (from Xilinx Virtex 7, Zynq and UltraScale) offers unlimited scalability
and max. FPGA IO flexibility guaranteeing highest performance. PRO DESIGN has over 80
employees, with various facilities for design, production and sales in Germany.
Real Intent, Inc.
Booth: 602 • Realintent.com
Real Intent is the leading provider of EDA software to accelerate Early Functional
Verification and Advanced Sign-off of digital designs. It provides comprehensive clockdomain crossing verification, advanced RTL analysis and sign-off solutions to eliminate
complex failure modes of SoCs. The Meridian and Ascent product families lead the
market in performance, capacity, accuracy and completeness.
54
DVCON.ORG
EXHIBITOR LISTING
Rocketick, Inc.
Booth: 305 • Rocketick.com
Rocketick is a leader in software-based simulation acceleration. Its product RocketSim
seamlessly plugs into all leading simulators (VCS, IES, Questa) and accelerates them by
3-10X. This enables to run regressions faster and shorten debug cycles, while leaving
IT farms and source codes untouched. RocketSim features unlimited design capacity,
4-state support, 80% memory savings and fast compilation time. RocketSim’s compiler
maps designs into data-flow graphs, partitioning them into independent threads which
run in parallel on any multi-core server.
S2C Inc.
Booth: 504 • s2cinc.com
S2C, a world-wide leader of FPGA prototyping solutions for today’s innovative designs,
provides:
• Rapid FPGA-based prototyping hardware and automation software
• Prototype Ready™ IP, interfaces and platforms
• System-level design verification and acceleration tools
Over 800 systems have been installed by leaders in consumer electronics,
communications, computing, image processing, data storage, research, defense,
education, automotive, medical, design services, and silicon IP. Headquartered in San
Jose, CA, S2C has offices in Israel, UK, China, Taiwan, Korea, and Japan.
For more information, visit S2cinc.com.
Semifore Inc.
Booth: 502 • Semifore.com
Semifore Inc., “The Addressmap Experts,” provides the CSRSpec language and the
CSRCompiler, a complete register design solution for hardware, software, verification, and
documentation. Collaboratively manage your design from a single source specification.
CSRSpec, SystemRDL, IP-XACT, or Spreadsheet inputs generate: Verilog and VHDL RTL;
Verilog, or C headers; Perl, IEEE IP-XACT; System Verilog for UVM, VMM and OVM; HTML
web pages; and Word or Framemaker documentation. Only Semifore gives your entire
team a complete, correct, up-to-date register design ecosystem.
DVCON.ORG
55
EXHIBITOR LISTING
Sibridge Technologies
Booth: 304 • Sibridgetech.com
Sibridge Technologies provides innovative value-added IP-based solutions for design,
verification, and embedded systems development to worldwide semiconductors and
electronic product companies. The company offers unique blend of critical components
in the development of SoCs and embedded products. The company has a large portfolio
of design and verification IP portfolios; comprehensive chip design, integration, and
verification expertise. The product design vertical offers embedded systems hardware &
software design for streaming media, wireless, and networking and mobility applications.
For more information please contact marcom@sibridgetech.com or visit Sibridgetech.com
SmartDV Technologies
Booth: 404 • Smart-dv.com
SmartDV creates high quality standard and custom protocol verification intellectual
property (IP) products designed to work with coverage-driven verification flows. SmartDV
currently offers 70+ verification IPs. Each verification IP (VIP) is shipped with a compliance
test suite and complete functional coverage model. Each VIP also is independently
developed and verified against external design IP for highest quality.
SmartDV VIPs are 2-4x faster to compile and simulate than competitive VIPs. SmartDV
has 60+ customers from wireless/mobile, storage, automotive, memory, networking and
other domains.
For more information on SmartDV’s VIP portfolio, see Smart-dv.com/products.html
Sunburst Design
Booth: 902 • Sunburst-design.com
“Life is too short for bad or boring training!” Sunburst Design provides the best, high
energy, World Class SystemVerilog & UVM Verification Training at very fair prices. All
Sunburst Design training materials were developed by world renown, award-wining
author and presenter, Cliff Cummings. To freely download multiple award-winning
SystemVerilog and UVM papers, visit: sunburst-design.com. To request a training quote,
send email to cliffc@sunburst-design.com. If you want your team to thank you for the
training, contact Cliff! We customize for free.
56
DVCON.ORG
EXHIBITOR LISTING
Sutherland HDL, Inc.
Booth: 902 • Sutherland-hdl.com
Sutherland HDL, Inc. – Training engineers to be Verilog, SystemVerilog and UVM Wizards!
Sutherland HDL provides onsite and online training, as well as licensed training
materials for in-house training programs. Our eTutored™-live online training is offered
as open-enrollment public workshops and as private (your company only) workshops.
Stuart Sutherland of Sutherland HDL has trained engineers throughout the world. Visit
sutherland-hdl.com (or shdl.co) for a description of our training workshops and openenrollment schedules, as well as whitepapers authored by Stuart Sutherland.
Synopsys, Inc.
Booth: 101 • Synopsys.com
Synopsys supplies the global electronics market with the software, IP, prototyping and
services used in semiconductor design, verification and manufacturing.
Synopsys’ comprehensive verification solutions deliver powerful capabilities to solve
increasingly difficult challenges across numerous verification domains and provide
critical links to higher levels of verification at all levels in the process.
This winning mix of technology, models, integrators, best practices and ecosystem helps
you to accelerate productivity and bring compelling, innovative products to market more
rapidly than ever before.
Test and Verification
Solutions Limited
Booth: 1004 • TestAndVerification.com
TVS (Test and Verification Solutions Ltd) provides products and services to make
hardware verification and software testing efficient and predictable. Our goal is to enable
the delivery of fully working first time silicon within the quality, costs and schedule
constraints of our customers. TVS services cover SystemC modeling and verification, RTL
verification for Si and FPGA, AMS modeling and verification, post-Si validation, software
testing. TVS offers custom-made Verification IPs in native SystemVerilog/UVM or e/eRM
and its own Verification signoff tool.
DVCON.ORG
57
EXHIBITOR LISTING
Truechip Solutions Pvt. Ltd.
Booth: 1002 • TrueChip.net
Truechip is a Verification IP specialist and its portfolio of plug-and-play VIPs include
USB3.x, PCIe Gen3/4, DDR3/4, LPDDR, AMBA family, MIPI Family, etc.. All of Truechip’s VIPs
are natively developed in System Verilog, provide 100% functional coverage, includes
assertions compatible with formal/dynamic simulation. All these VIPs are in production
use across customers worldwide, and support all industry leading simulators and
emulators. To try out any of these high quality VIPs and experience Truechip’s industry
leading 24X5 support, please visit Truechip.net
VeriFast
Booth: 1105 • Verifasttech.com
VeriFast is a verification technology company providing industry leading EDA tools,
verification training programs such as SystemVerilog / UVM, and verification consulting
services. At DVCon 2015 we are showcasing our latest enterprise cloud platform “vPivotal
- an ASIC Project Management and Development Platform” along with our state of the art
self learning training platform.
Verific Design Automation
Booth: 802 • Verific.com
Build your own RTL tools with Verific’s industry standard (System)Verilog and VHDL
parsers ! Verific Design Automation has provided (System)Verilog and VHDL front-ends to
EDA and semiconductor computers for many years. With more than 60 active licensees
worldwide, Verific’s parsers are found everywhere. Recently we have added support for
UPF as well. And all our APIs are available in Python, Perl or C++ alike.
Verification Academy
Booth: 301 • VerificationAcademy.com
The Verification Academy is the most comprehensive online resource for verification
training. Organized into a collection of free online courses, resources and forums,
the Verification Academy focuses on key aspects of advanced functional verification,
including: UVM, Coverage, Assertion-Based Verification, Verification Management, CDC,
Acceleration, Low Power, FPGA Verification and more. Join us in the Verification Academy
Booth to meet with Harry Foster and other prominent Verification experts and see the
latest from the Academy.
58
DVCON.ORG
EXHIBITOR LISTING
Verifyter
Booth: 1104 • Verifyter.com
Verifyter was founded 2010 with the mission to transform the development process
by automating debug of regression test failures, especially targeting the ASIC market.
PinDown, Verifyter’s automatic debugger, is currently used by both ASIC and ASIC IP
companies and has proven to speed-up the bug fixing cycle by up to
400% and bring in the project release date by as much as 10%.
Xpeerant, Inc
Booth: 1207 • Xpeerant.com
Winning the race to the market window is the challenge of every design manager. At
mission critical times, Xpeerant engages by providing highly experienced design and
verification engineers with the skills needed from concept to silicon including advanced
verification methodologies such as (UVM/OVM/VMM) and the latest design skills.
Xpeerant can help fill out your pit crew, and put you behind the wheel to win the race to
the market window.
Zocalo Tech.
Booth: 702 • Zocalo-tech.com
Zocalo Tech’s Zazz product allows users to simulate and debug assertions outside of the
design/verification environment. Zazz does this by creating a constrained randomized
testbench around the assertion so that engineers can see the full range of behaviors
allowed by the assertion rather than the limited range of behaviors that might be seen in
an actual simulation. This is critical to creating effective assertions, since assertions that
never fail or that fail inappropriately can actually slow the verification process.
DVCON.ORG
59
WELCOME THESE
EXHIBITOR
FIRST-TIME
LISTINGEXHIBITORS
Stop by these companies’ booths to learn more about their products and services!
Booth 805
Booth 1103
Booth 804
Booth 305
Booth 902
Booth 404
Booth 1004
Booth 902
Booth 1105
Booth 1104
Booth 1207
60
DVCON.ORG
SAVE THE DATE!
DVCON 2016
February 29 - March 3
EXHIBITING COMPANIES
VERIFICATION COMPILER
Comprehensive, best-in-class verification in one product
Design Team
Planning & Coverage
Debug
Static &
Formal
Simulation
Verification Team
Verification planning
Verification Compiler
Complete access
• New technology
• Native integrations
• 3X productivity
•
Static &
Formal
Verification
IP
Simulation
Debug
VIP, Models & Databases
Coverage closure
For more information, please visit www.synopsys.com/vc