Part IA Engineering
Contents of Handout 2
Section A
Binary Numbers.
This section covers the material
for questions 6 and 7 on
examples paper 2.
Section B
Section C
Bistables.
Applications of bistables.
These sections cover the material
for questions 8 – 11 on
examples paper 2.
Section D
Synchronous logic design.
This section covers the material
for questions 1 – 7 on
examples paper 3.
Section E
Analogue conversion & adder circuits.
This section covers the material
for question 8 and 9 on examples
paper 3.
Digital Circuits &
Information Processing
Handout 2
Sequential Logic
Richard Prager
Tim Flack
January 2009
1
2
Binary Numbers
Binary is base 2. Each digit is either 0 or 1.
Handout 2 Section A
Binary Numbers
Sequential logic is used to construct counters, and sequence detection circuits. In order to design satisfactory counters we need to understand the binary number system fully. In this section we therefore introduce
binary, octal and hexadecimal numbers.
1
32
25
MSB
0
16
24
1
8
23
0
4
22
1
2
21
0
1
20
LSB
= 4210
Binary
coefficients
0
32
25
MSB
0
16
24
1
8
23
0
4
22
1
2
21
1
1
20
LSB
= 1110
Binary
coefficients
A binary digit is called a bit.
In computers, binary numbers are often 8 bits long.
An 8 bit binary storage location is called a byte.
A byte can store numbers from 0 to (28 − 1) = 255.
The 2’s-complement and sign-magnitude techniques
for representing negative numbers are then described.
MSB Most significant bit.
LSB Least significant bit.
3
4
Octal: Base 8
Decimal to Binary Conversion
Use the remainders from successive division by 2.
Just as base 2 only uses two digits (0 & 1), base 8
only uses 8 digits: 0, 1, 2, 3, 4, 5, 6 and 7.
0
64
82
MSB
(a) Convert 4210 into binary:
42/2 = 21 remainder 0
21/2 = 10 remainder 1
10/2 = 5
remainder 0
5/2 = 2
remainder 1
2/2 = 1
remainder 0
1/2 = 0
remainder 1
So the answer is 1010102 (reading upwards).
5
8
81
28
1
80
LSB
= 4210
Octal
coefficients
To convert from decimal to base 8 either use successive division by 8:
42/8
5/8
=5
=0
remainder 2
remainder 5
So the answer is that 4210 = 528 (reading upwards).
Or alternatively, convert to binary, divide the binary
number into three-bit groups and work out the octal
digit to represent each group. We have shown that
(b) Convert 1110 into binary:
11/2 = 5 remainder 1
5/2 = 2 remainder 1
2/2 = 1 remainder 0
1/2 = 0 remainder 1
So the answer is 10112 (reading upwards).
4210 = 1010102 so:
1
5
5
0
1
28
0 1 0
= 4210
6
Hexadecimal: Base 16
For base 16 we need 16 different digits. We therefore
need new symbols for the digits to represent 10–15.
10102 = 1010 = A16
10112 = 1110 = B16
11002 = 1210 = C16
0
256
162
MSB
2
16
161
A16
1
160
LSB
11012 = 1310 = D16
11102 = 1410 = E16
11112 = 1510 = F16
Decimal to Hex Conversion
To convert from decimal to hex either use successive
division by 16:
42/16
2/16
=2
=0
remainder A
remainder 2
So the answer is 2A16 (reading upwards).
= 4210
Hexadecimal
coefficients
Or alternatively, convert to binary, divide the binary
number into four-bit groups and work out the hex digit
to represent each group. We have shown that 4210 =
1010102 so:
Labelling Hex Numbers
2
Hex numbers are indicated 5916 or 59H when they
occur in text. In assembler programming the convention $59 is often used. Two hexadecimal digits are often used as a convenient way to specify the contents
of a byte.
7
0
0
1
0
1
A16
0 1
0
= 4210
You can also do the conversion automatically on your
calculator.
8
Negative Numbers
Changing Sign
So far we can only represent positive numbers. In an
8-bit byte we can represent the decimal numbers from
0 to 255 (255 = 28 − 1 = FFH).
The rule for changing a positive 2’s complement number into a negative 2’s complement number (or vice
0
255
0H
FFH
What happens when we do this to an 8 bit binary number x.
Whatever we do, there are still only 256 different combinations of bits in a byte so if we want to represent
negative numbers we have to give up some of the
range of positive numbers we had before. We choose
the following strategy which is called 2’s complement.
0
0H
positive
127
-128
7FH
80H
negative
versa) is:
Invert all the bits and add 1.
• Invert all the bits: x → (255 − x)
• Add one: (255 − x) → (256 − x)
But 256 (= 100H) will not fit into an 8 bit byte. It
equals 00H and causes the carry flag to be set. If
we choose to ignore the carry flag then 256 − x will
behave just like 00 − x.
-1
FFH
We can therefore use normal binary arithmetic to manipulate the 2’s complement of x and it will behave just
like −x.
All negative numbers have the MSB set.
9
10
2’s Complement Addition
0
0
0
(0)
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
2’s Complement Addition
7
+4
11
To subtract, negate the second argument, then add.
0 0 0 0 0 1 1 1
7
1 1 1 1 1 0 0 1
+−7
(1) 0 0 0 0 0 0 0 0
0
(1)
(0)
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0 1
0 1
1 0
0 0
0 1
0 1
9
+−7
2
2AH
F5H
(1)1FH
0
4
+−7
−3
127 -128
-1 0
127 -128
-1
positive
negative
positive
negative
42
31
0
-11
0
(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0 1
0 1
1 0
42
+ −11
31
Answer
positive
negative
127 -128
-1
−7
+−7
−14
11
12
2s Complement Overflow
Signed vs. Unsigned 8 Bit Numbers
2s Complement
Signed 8 bit numbers
With signed numbers we are deliberately ignoring the
carry flag so we need a new rule to detect when the
answer is out of range.
(127, 127)
7FH
Unsigned
8 bit numbers
(0, 0)
0H
When working with unsigned numbers we use the carry
from the 8th bit to show when the number has got too
big.
The rule is: 2s complement overflow occurs when
(255, -1)
FFH
the carry into the MSB
(128, -128)
80H
6=
the carry out from the MSB.
13
14
Sign and Magnitude Representation
MSB indicates the sign: (0 ⇒ +, 1 ⇒ −). Remaining
7 bits contain the magnitude.
(0)
0
0
0
0
0
0
0
0
0
0 1
0 1
1 1
1
1
1
1
1
1
1
1
0
15
+15
30
overflow (0)
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
127
+1
−128
OK
OK
(1)
1
1
1
1
1
1
1
1
1
1
0
0
1 0
1 0
0 0
0
0
0
0
0
1
1
1
0
−15
+ − 15
−30
Sign and Magnitude
8 bit numbers
(127, 127)
7FH
Unsigned
8 bit numbers
(0, 0)
0H
(129, -1)
81H
FFH
(255, -127)
overflow (1)
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
−127
+−2
127
15
Not often used. Separate circuits are required for adding
positive and negative numbers. Note that +0 has a
different representation to −0.
16
Binary Coded Decimal
Alphanumeric Character Codes
Each decimal digit of a number is coded as a four bit
binary quantity.
ASCII:
American Standard Code for Information Interchange.
BCD is used in some business computers and cash
registers. It is not an efficient way of storing the numbers, but is easy to code and decode.
In the standard version this is a 7 bit code with the
remaining bit being set to zero or used for parity. The
first 32 numbers are ‘control codes’ originally used for
controlling modems. The rest are upper case letters,
lower case letters, numbers and punctuation.
124810 = 0001 0010 0100 1000BCD
123410 = 0001 0010 0011 0100BCD
This is 8421 BCD because the bits have these weightings. As we don’t need numbers above 9 another alternative is 2421 BCD, where the top bit only has a
weight of 2. Another variant, called ‘Excess-3 code’
is to record each digit value plus 3 using the 8421
weights.
17
An extended version of ASCII uses all 8 bits to provide
128 additional graphics characters. These vary from
computer to computer.
Other systems: EBCDIC — an IBM system, not much
used. Unicode — a 16 bit system, to include Chinese
characters etc.
18
Handout 2 Section B
Parity
Bistables
Parity is the simplest sort of error detection coding
used for transferring binary data through an imperfect
data channel.
In the transmission circuitry, it involves setting a particular bit in each binary number so as to ensure that
an even number of bits are always on.
In the receiver circuitry we count the number of bits
that are on in each number and reject any that have
an odd number.
Parity can only detect 1-bit errors. More serious errors
may go undetected.
In this section we describe the construction of circuits
which have two internal states. They are called bistables. We gradually build up more sophisticated bistables from simple ones.
Bistables circuits are the building blocks of computer
memory chips, sequencers and counters.
We start by describing the set-reset (SR) bistable.
A gated-SR bistable is built using an SR bistable.
A master-slave bistable is built using two gated-SR
bistables.
A D-type latch is built from a master-slave bistable.
A JK bistable is built from a master-slave bistable.
19
20
Set Reset Bistable
S
• If R turns on then Q2 turns on.
Q1
• Q1 will be off as Q2 is on and S is off.
R
Q2
• Therefore, even if R turns off, Q2 will stay on. (As
long as S does not turn on).
So:
Q1 = S.Q2 = S + Q2
S turns Q1 on and Q2 off. They then stay in this state
until R turns on.
Q2 = R.Q1 = R + Q1
R turns Q2 on and Q1 off. They then stay in this
state until S turns on.
Assume initially that S = R = 1 is not allowed.
• If S turns on then Q1 turns on.
We therefore have memory. The circuit state depends
not only on the current values of S and R but also on
their values in the past.
• Q2 will be off as Q1 is on and R is off.
• Therefore, even if S turns off, Q1 will stay on. (As
long as R does not turn on).
21
22
State Diagram of SR Bistable
Contact Debouncing
The complete operation of the bistable, including what
happens when S = R = 1, can be described using
a state diagram.
+5V
R
S=0
R=0
Q1=1
Q2=0
s
all
f
s
S
ise
r
S
S=1
R=0
Q1=1
Q2=0
R falls
Sr
B
Rr
ise
S=1
R=1
Q1=1
Q2=1
R rises
A
s
S rises
es
s
Q1
Q2
0V
S falls
is
Rr
ise
R
R
S=0
R=1
Q1=0
Q2=1
A
B
ls
fal
S=0
R=0
Q1=0
Q2=1
Q1
23
24
Gated SR Bistable
Master-Slave Bistable
S
S
Q1
Q1
G
G
Q2
Q2
R
R
S
R
Set
S
Clock
G
Reset
R
Q1
S
Q1
Output
Q2
Output
G
Q2
R
G
When clock is low
first bistable is sensitive to input signal.
Q1
The bistable can change state whenever the gate input is high.
25
When clock rises
state of first bistable is transfered to second bistable.
26
Asynchronous Inputs
PRESET
Master Slave Symbol
Set
S
Clock
G
Reset
R
Set
Q1
Q1
Output
S
Clock
G
Reset
R
Q1
Output
Q2
Output
G
Q2
S
R
Q
Q2
Output
R
CLEAR
Output
PR
CK
Clock
Reset
S
Set
S
Q
Output
Q
CK
Q
R
CLR
27
28
JK Bistable
Preset
D-type Latch
PR
S
J
D
S
Q
D
Output
Q
Output
CK
CK
K
Q
Q
R
CLR
CK
CK
R
CK
Q
Q
Clear
A D-type (delay) latch has only one data input: D.
PR
J
Q
CK
K
Q
CLR
29
30
Building a JK Bistable
Operation of JK Bistable
• Start with simple SR bistable.
• Add gate input: bistable can only change when
gate is high.
In the Master-Slave bistable the input state S = R =
1 is prohibited. In the JK bistable this state is allowed
and performs a new and useful function: it toggles the
bistable (i.e. inverts its previous state).
• Put two SR bistables together: create masterslave bistable. Output only changes when clock
input rises.
• Add asynchronous inputs: preset and clear.
• Add AND gates to prevent S = R = 1 at input to
first SR bistable of master-slave pair. Create JK
bistable.
31
Inputs when
clock low
Input J Input K
0
0
0
1
1
0
1
1
Output after
clock rises
Q(n + 1)
Q(n) (unchanged)
0
1
Q(n) (toggles)
32
Characteristic Table
Handout 2 Section C
The characteristic (or excitation) table of the JK bistable
defines what inputs are required to achieve a particular output change.
Applications of Bistables
Output
before → after
Q(n) Q(n + 1)
0
0
0
1
1
0
1
1
Required
inputs
Input J Input K
0
×
1
×
×
1
×
0
In this section we introduce a number of circuits using
bistables. They fall into two groups.
• Counter circuits: divide by n counters, ripple counter,
synchronous counter, Johnson counter.
× ⇒ “don’t care”
• Memory circuits: shift register, parallel loading shift
register.
If at any time when the clock is low a signal exists
at the input encouraging the bistable to change state,
that change will take place as the clock rises.
33
Counters and sequencers are used in the design of
control logic inside microprocessors.
34
Ripple Counter
Divide by 2 Counter
QD
1
QA
Q
J
CK
CK
Q
CLR
Q
J
PR
PR
PR
PR
Q
K
QB
1
PR
J
QC
Q
J
Q
J
CK
CK
CK
CK
Q
K
CLR
Q
K
CLR
Q
K
CLR
Q
K
CLR
Clear
Run
Reset
Clear
CK
QD
QC
CK
QB
Q
QA
time
time
35
36
Ripple Counter States
Synchronous Counter
QD
QC
QB
QA
1
QA
0
0
0
0
0
0
Correct
States
QB QC
0
0
0
0
0
0
1
1
1
1
0
0
QD
0
1
Transitory
States
QA QB QC QD
K
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
Q
K
Q
J
CK
CK
Q
K
Q
J
Q
K
Q
CK
0
1
CK
QD
0
1
1
0
0
QC
0
1
QB
0
0
0
1
Q
J
CK
CK
0
0
0
Q
J
1
1
0
1
0
0
0
0
0
QA
time
0
37
38
Shift Register
Q1
Din
D
CK
Q
Q2
D
CK
Q
D
Q
Parallel Loading
Q4
Q3
D
CK
Q
Q1
Q2
Q3
Q4
CK
PR
Din
D
CK
CK
PR
D
Q
PR
PR
Q
D
Q
D
Q
CK
CK
CK
CK
CLR
CLR
CLR
CLR
CK
Din
Q1
Load
Q2
Q3
I1
I2
I3
I4
Q4
time
39
40
Serial Data Link
Johnson Counter
Application of shift registers.
A parallel loading shift register is used to send one
data bit at a time across the serial link. Benefit: less
wires are needed for the link than would be required
for a fully parallel link.
A twisted ring Johnson counter uses a shift register of
length N to produce a sequence of length 2N .
Q1
I1 I2 I3 I4
D
Data
Parallel Loading
Shift Register
Ground
CK
Q
Q2
D
CK
Q
Q3
D
CK
Q
Q4
D
Q
CK
Shift Register
CK
Q1 Q2 Q3 Q4
Clock
41
42
Divide by Five
Divide by Five
QC
1
QB
QA
Synchronous design.
QC
J
Q
J
Q
J
QB
QA
Q
CK
CK
CK
K
Q
CLR
K
Q
CLR
K
Q
CLR
CK
J
Q
CK
Asynchronous clear can be used to produce divide by
N counters for N not equal to a power of 2.
K
J
Q
CK
Q
K
J
Q
CK
Q
K
Q
CK
Problem: glitch as 101 appears briefly before the counter
clears to zero.
43
44
Synchronous Design
Handout 2 Section D
Generate sequences. For example: traffic lights.
Synchronous Logic Design
Detect sequences. For example: electronic combination lock inside burglar alarm.
In this section we describe how to design synchronous
sequential logic circuits.
There are 5 stages: state diagram, bistable allocation,
state transition table, Karnaugh maps, and finally the
circuit diagram.
The technique is introduced using the design of a divideby-three counter. Further examples based on a sequence generator for a boiler ignition system and a
sequence detector are then described. Sequence detectors are used in the construction of digital communication systems.
45
• State diagram.
• Bistable allocation.
• State transition table.
• Karnaugh maps for each input.
• Full circuit.
46
Divide by 3 counter
State diagram with bistable allocation:
Outline Synchronous Circuit
AB
0 0
Output
Input
J
Q
Output
Input
CK
Input
K
AB
0 1
J
AB
1 0
Q
CK
Q
Input
K
State transition table:
Q
Current
state
QA QB
0
0
0
1
1
0
Clock
1
47
1
Next
state
QA QB
0
1
1
0
0
0
0
0
JA
0
1
×
×
Required
inputs
KA JB KB
×
1
×
×
×
1
1
0
×
1
×
1
48
Karnaugh Maps
JK Reminder
If at any time when the clock is low a signal exists
at the input encouraging the bistable to change state,
that change will happen as the clock rises.
A
JA
1
0
1
B
A
JB
J Permission to turn Q on.
1
KA = 1
A
KB
0
B
B
JB = Q A
49
1
B
JA = Q B
K Permission to turn Q off.
A
KA
1
1
KB = 1
50
Circuit
Sequence Generator with Inputs
A boiler control unit has a ‘run’ input R.
QB
QA
When R goes to 1, turn on the air blower (A = 1) the
pilot light gas supply (P = 1) and the igniter (I = 1).
J
Q
CK
1 K
J
Q
CK
Q
1 K
When the signal from the pilot light thermocouple indicates the pilot light is on (T = 1), turn off the igniter
and turn on the main gas supply (G = 1).
Q
Clock
If R goes to 0 or T goes to 0, turn everything off.
51
52
State Diagram
Check the State Diagram
State 1 (off)
Air blower A = 0
Main gas G = 0
Pilot gas P = 0
Igniter I = 0
R=0
T=X
You must make sure that there is a path leaving each
state for every combination of possible inputs.
R=1
T=X
R=0
T=X
In this case we have two inputs R and T . There are
therefore 4 possible combinations. (R.T , R.T , R.T ,
and R.T )
State 2 (pilot)
R=0
or
T=0
Air blower A = 1
Main gas G = 0
Pilot gas P = 1
Igniter I = 1
R=1
T=0
We need to make sure that there are 4 paths leaving
every state.
R=1
T=1
Note that “R = 1, T = ×” counts for two paths (R.T
and R.T ) also “R = 0 or T = 0” counts for three
paths (R.T , R.T and R.T )
State 3 (on)
Air blower A = 1
Main gas G = 1
Pilot gas P = 1
Igniter I = 0
R=1
T=1
53
54
State Transition Table
Inputs
Bistable Allocation
State 1
State 2
State 3
off
pilot
on
UNUSED
Bistable
Outputs
QA QB
0
0
0
1
1
0
1
1
55
Current
state
QA QB
0
0
0
0
0
0
0
0
Next
state
QA QB
0
0
0
0
0
1
0
1
Required
bistable inputs
JA KA JB KB
0
×
0
×
0
×
0
×
0
×
1
×
0
×
1
×
R
0
0
1
1
T
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
0
0
0
0
1
×
×
×
×
×
×
×
×
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
×
×
×
×
1
1
1
0
0
0
0
0
×
×
×
×
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
×
×
×
×
1
1
1
1
×
×
×
×
1
1
1
1
56
Karnaugh Maps
Concise State Transition Table
Inputs
Current
state
QA QB
0
0
0
0
Next
state
QA QB
0
0
0
1
Required
bistable inputs
JA KA JB KB
0
×
0
×
0
×
1
×
R
0
1
T
×
×
0
1
1
×
0
1
0
0
0
1
1
1
0
0
1
0
1
0
0
0
1
×
×
×
×
×
×
1
0
1
0
1
1
×
0
1
1
1
1
0
0
0
0
0
1
0
0
0
×
×
×
1
1
0
0
0
0
×
×
×
×
×
1
1
0
0
×
1
×
QA
0
0
0
0
QA
1
1
1
1
1
0
1
1
T
0
1
0
0
R
T
R
QB
QB
KA = R . T. QB
JA = R . T . Q B
KA = R . T. QB
QA
QA
0
0
0
0
1
1
1
1
1
1
0
1
T
1
0
1
0
R
T
R
1
QB
JB = R . Q A
QB
KB = R . T . QA
KB = T . JB
57
58
Output Logic
Partial Circuit
From the state diagram we have:
T
QB
R
J
QA
K
State 1
State 2
State 3
Q
R
off
pilot
on
UNUSED
Bistable
Outputs
QA QB
0
0
0
1
1
0
1
1
P
0
1
1
0
Control
Signals
A I
0 0
1 1
1 0
0 0
G
0
0
1
0
Thus:
J
R
T
QA
CK
T
QB
Q
Q
QB
P = QA ⊕ QB
CK
K
A = QA ⊕ QB
Q
I = QA.QB
G = QA.QB
Clock
59
60
Revision
Complete Circuit
T
QB
R
J
QA
Bistable Allocation: n bistables provides 2n states.
Assign code to each state. Note the unused states.
K
Q
R
J
R
T
QA
CK
T
QB
Q
State Diagram: Define output in each state. Define
transitions for all combinations of inputs.
Q
State Transition Table: Work out bistable inputs required to perform correct state transitions. Remember to include a separate line in the table for
every combination of current state and input variables. Handle unused states.
QB
CK
K
Q
Karnaugh Maps: Work out logic to implement the functions required by state transition table.
Clock
P,A
G
I
61
Circuit: Remember that all the bistables should be
clocked synchronously (together).
62
Sequence Detector
Detect the received sequence 101 on an input I. When
the sequence is detected Y = 1. Only respond to
non-overlapping sequences. The sequence 10101 should
give an output after bit 3, but not after bit 5.
State 1 (start)
Output Y=0
Bistable Allocation
We have 4 states therefore we need 2 bistables and
there are no unused states.
I=0
I=1
State 2 (got 1)
Output Y=0
I=1
I=0
State 1
State 2
State 3
State4
I=0
I=0
I=1 State 3 (got 10)
Output Y=0
start
got 1
got 10
got 101
Bistable
Outputs
QA QB
0
0
0
1
1
0
1
1
I=1
State 4 (got 101)
Output Y=1
63
64
Karnaugh Maps
State Transition Table
Input
I
0
1
0
1
Current
state
QA QB
0
0
0
0
0
0
1
1
Next
state
QA QB
0
0
0
1
1
0
0
1
QA
Required
bistable inputs
JA KA JB KB
0
×
0
×
0
×
1
×
1
0
×
×
×
×
0
1
0
0
QA
I
1
1
0
0
0
1
0
1
×
×
1
0
0
1
×
×
0
1
1
1
1
1
0
0
0
1
×
×
1
1
×
×
1
0
1
0
QB
JA = I . Q B
KA = I . QB
I
KA = I . QB
QA
QA
0
0
1
1
I
1
1
0
0
QB
JB = I
65
1
QB
1
0
0
1
1
I
QB
KB = I
66
Circuit Diagram
Output Logic
QB
J
Q
QA
I
CK
From the state diagram we have:
State 1
State 2
State 3
State4
start
got 1
got 10
got 101
Bistable
Outputs
QA QB
0
0
0
1
1
0
1
1
I
K
Q
QB
Output
Y
0
0
0
1
I
J
Q
QB
CK
I
K
Q
Thus Y = QA.QB
Clock
Y
67
68
Handout 2 Section E
Weighted Resistor DAC
LSB
Analogue Conversion &
a0
a1
Adder Circuits
D-type latches
D0
D1
Q0
Q1
R
R’
R/2
I
This section we introduce a number of circuits, using both combinational and sequential logic, that are
used in the construction of microprocessor systems.
It therefore provides background information for handout 3 on microprocessors as well as using techniques
from handouts 1 and 2.
Circuits for digital to analogue and analogue to digital
conversion are described. These types of circuit are
often used to interface microprocessors to external instrumentation.
A binary adder circuit is then introduced. Binary adders
form the heart of the arithmetic logic units inside microprocessors.
69
R/(2
an-2
D n-2 Q n-2
an-1
D n-1 Q n-1
MSB
n-2
+
)
Vo
R/(2 n-1 )
0V
Assume the op-amp is ideal. Therefore the inverting
input is a virtual earth and Vo = −IR′. Let the latch
output voltage be A for each Q = 1, and 0 for each
Q = 0.
a0A
2a A
2n−1an−1A
+ 1 + ... +
R
R
R
! n−1
′
X
−AR
Vo =
am2m
R
m=0
I =
70
R-2R Ladder DAC
Drawbacks
R
A Volts
Limitations of the weighted resistor DAC.
in-1
an-1
0
• A wide range of resistor values are required. These
will need to be made from different materials so
the way they change with temperature will be different. The output of the circuit will probably drift
as it warms up.
71
R
in-2
i1
2R
• Lots of resistance values which are difficult to implement.
• If the LSB is 5% accurate then the MSB must be
5% . If n = 8 this comes to 0.04% which is time
2n−1
consuming and expensive to achieve.
R
2R
2R
an-2
1
0V
i0
1
0
0V
a0
1
0V
I
+
0
2R
0V
1
0V
R’
Switched
by MSB
2R
a1
0
i0
Switched
by LSB
Vo
0V
Assume the op-amp is ideal. Therefore the inverting
input is a virtual earth and Vo = −IR′.
72
R
R
i0
Resistance
equals 2R
i1
i0
2R
R
Resistance
equals 2R
2R
i0
2R
i0
2R
0V
0V
R
i1
R
i0
2R
i0
2R
2R
i1
i2
2R
R
2R
0V
i0
2R
i0
2R
2R
0V
The resistance of the three resistors shown above is
equal to 2R.
Therefore i1 = 2i0.
The resistance of the five resistors shown above is
equal to 2R.
Therefore i2 = 2i1.
73
74
R
R
R
i1
i2
Resistance
equals 2R
2R
i0
2R
i0
2R
2R
0V
R
i3
2R
i1
2R
So in−1 = 2n−1i0 and for the left-most resistor
A = 2n−1i0 × 2R ⇒ i0 = 2A
nR
R
R
i2
We have shown that im+1 = 2im so im = 2mi0
i0
2R
i0
2R
I =
2R
=
0V
The resistance of the seven resistors shown above is
equal to 2R.
n−1
X
amim
m=0
n−1
X
A
am2m n
2 R
m=0
X
A n−1
= n
am2m
2 R m=0
X
−AR′ n−1
⇒ Vo =
am2m
n
2 R m=0
Therefore i3 = 2i2.
75
76
Analogue to Digital Conversion
Vout = Gain × (Vref − Vin), but when the gain is very
large:
Vin > Vref ⇒ Vout = V−
Vin < Vref ⇒ Vout = V+
1-bit ADC (comparator) without hysteresis.
V+
Vin
Vout
Vref
Vin
+
Vref
Vtime
Symbol:
Vout
+
time
77
78
1-bit ADC (comparator) with hysteresis.
Vin > V ′ ⇒ V ′ =
1+n
which gives the lower threshold
nVref + V+
Vin < V ′ ⇒ V ′ =
1+n
which gives the upper threshold
Schmidt trigger.
V+
Vin
Vref
nVref + V−
R
Vout
V’ +
Vin
nR
Vtime
Symbol:
Vout
+
time
79
80
Flash ADC
+Vref
Analogue input
Transfer characteristics of the comparator with hysteresis.
R
R
R
Vout
R
R
R
Vin
R
R
81
+
−
+
−
+
−
+
−
+
−
7
6
5
4
3
2
1
Parallel
binary
output
Enable
+
−
+
−
Sampling
pulses
82
• 8 bit flash ADC requires 256 comparators.
Full Adder
• 12 bit flash ADC requires 4096 comparators!
• Alternative is to have a ramp that gradually rises
created by a DAC and a single comparator to detect the value at which the input becomes less
than the ramp value. This is called the stair-step
ramp or counter method.
• The stair-step ramp method is much slower than
the flash ADC.
Analogue input
+
−
DAC
Divide by 8
Counter
Control
Logic
Ai
0
0
0
0
1
1
1
1
Bi
0
0
1
1
0
0
1
1
Ci
0
1
0
1
0
1
0
1
Ci+1
0
0
0
1
0
1
1
1
Si
0
1
1
0
1
0
0
1
Ci+1 = Ai.Bi + Ai.Ci + Bi .Ci
Si = Ai ⊕ Bi ⊕ Ci
Parallel
Binary
Output
83
84
Ripple Carry Adder Circuit
Full Adder Circuit
C0 A0
A
C i+1
B0
A1 B1
A2 B2
A3 B3
B
A
A
A
B
B
B
C in C out
C in C out
C in C out
C in C out
S
S
S
S
S0
S1
S2
S3
C4
What happens if A0, A1, A2 and A3 are fed to the A
Si
inputs and C0 is set to 1?
In this case S = B − A because we have changed
the sign of A by inverting it and adding 1 (using C0).
Ai Bi Ci
85
86