ELEC ENG 4CL4:
Control System Design
Notes for Lecture #31
Monday, March 29, 2004
Dr. Ian C. Bruce
Room: CRL-229
Phone ext.: 26984
Email: ibruce@mail.ece.mcmaster.ca
Chapter 13
©
Goodwin, Graebe, Salgado , Prentice Hall 2000
Minimum Time Dead-Beat Control
The basic idea in dead-beat control design is similar
to that in the minimal prototype case: to achieve
zero error at the sample points in a finite number of
sampling periods for step references and step output
disturbances (and with zero initial conditions).
However, in this case we add the requirement that,
for this sort of reference and disturbance, the
controller output u[k] also reach its steady state
value in the same number of intervals.
Chapter 13
©
Goodwin, Graebe, Salgado , Prentice Hall 2000
The design involves cancelling the open loop poles
in the controller. Thus, the system is (for the
moment) assumed to be stable. We see that the result
is achieved by the following control law
αA0 q ( z )
Cq ( z ) = n
; α= 1
B 0 q ( 1)
z − αB 0 q ( z )
The resulting closed loop complementary sensitivity
function is
C q ( z ) G 0 q ( z ) αB 0 q ( z )
T (z) =
=
1+ C q ( z )G0 q ( z )
zn
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
Example
Consider the servo system
1
Go (s) =
s(s + 1)
Synthesize a minimum time dead-beat control with
sampling period ∆ = 0.1[s].
Cq ( z ) =
αA0 q ( z )
z n −αB0 q ( z )
z −95.47
= 105z.49
+0.4910
The next slide shows the simulated response.
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
Figure 13.7: Minimum time dead-beat control for a
second order plant
1.4
Plant response
1.2
1
0.8
0.6
y(t)
y[k]
0.4
0.2
0
0
0.1
0.2
0.3
0.4
Time [s]
0.5
0.6
0.7
0.8
Chapter 13
©
Goodwin, Graebe, Salgado , Prentice Hall 2000
From the above result we see that the intersample
problem has been solved by the dead-beat control
law.
Note, however, that this is still a very widebandwidth control law and thus the other problems
discussed in the slides for Chapter 12 (i.e. noise,
input saturation and timing jitter issues) will still be
a problem for the dead-beat controller.
Chapter 13
©
Goodwin, Graebe, Salgado , Prentice Hall 2000
The controller presented above has been derived for
stable plants or plants with at most one pole at the
origin. Thus cancellation of A0q(z) was allowed.
However, the dead-beat philosophy can also be
applied to unstable plants, provided that dead-beat is
attained in more than n sampling periods. To do
this we simply use pole assignment and place all of
the closed loop poles at the origin.
Indeed, dead-beat control is then seen to be simply a
special case of general pole-assignment. We study
the general case below.
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
Digital Control Design by Pole
Assignment
Minimal prototype and dead-beat approaches are
particular applications of pole assignment. Indeed,
all can be derived by solving the usual pole
assignment equation:
A ( q ) L ( q ) + B ( q ) P ( q ) = Acl ( q )
for particular values of Acl ( q ).
The general pole assignment problem is illustrated
below.
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
Example
Consider a continuous time plant having a nominal
model given by
Go (s) =
1
(s + 1)(s + 2)
Design a digital controller, Cq(z), which achieves a
loop bandwidth of approximately 3[rad/s]. The loop
must also yield zero steady state error for constant
references.
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
We first use the MATLAB program c2del.m to obtain
the discrete transfer function in delta form representing
the combination of the continuous time plant and the
zero order hold mechanism. This yields
0.0453γ + 0.863
D {Gho (s)Go (s)} = 2
γ + 2.764γ + 1.725
We next choose the closed loop polynomial Aclδ(γ) to
be equal to
Aclδ (γ) = (γ + 2.5)2 (γ + 3)(γ + 4)
Chapter 13
©
Goodwin, Graebe, Salgado , Prentice Hall 2000
The resulting pole assignment equation has the form
(γ 2 + 2.764γ + 1.725)γLδ (γ) + (0.0453γ + 0.863)Pδ (γ) = (γ + 2.5)2 (γ + 3)(γ + 4)
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
The MATLAB program paq.m is then used to solve
this equation, leading to Cδ(γ), which is finally
transformed into Cq(z). The delta and shift
controllers are given by
29.1γ 2 + 100.0γ + 87.0
Pδ (γ)
Cδ (γ) =
=
γ 2 + 7.9γ
γLδ (γ)
29.1z 2 − 48.3z + 20.0
Cq (z) =
(z − 1)(z − 0.21)
and
Finally, the closed loop response is as shown on the
next slide.
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
Figure 13.8: Performance of digital control loop
Plant output and ref.
1.5
1
0.5
0
y(t)
−0.5
−1
−1.5
0
0.5
1
1.5
2
2.5
Time [s]
3
3.5
4
4.5
5
©
Chapter 13
Goodwin, Graebe, Salgado , Prentice Hall 2000
Summary
❖
There are a number of ways of designing digital control
systems:
◆
◆
❖
design in continuous time and discretize the controller prior to
implementation;
model the process by a digital model and carry out the design in
discrete time.
Continuous time design which is discretized for
implementation:
◆
◆
◆
Continuous time signals and models are utilized for the design;
Prior to implementation, the controller is rep0laced by an
equivalent discrete time version;
Equivalent means to simply map s to δ (where δ is the delta
operator);
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Chapter 13
◆
◆
❖
Goodwin, Graebe, Salgado , Prentice Hall 2000
Caution must be exercised since the analysis was carried out in
continuous time and the expected results are therefore based on the
assumption that the sampling rate is high enough to mask sampling
effects;
If the sampling period is chosen carefully, in particular with
respect to the open and closed loop dynamics, then the results
should be acceptable.
Discrete design based on a discretized process model:
◆
◆
◆
First the model of the continuous process is discretized;
Then, based on the discrete process, a discrete controller is designed and
implemented;
Caution must be exercised with so called intersample behavior: the
analysis is based entirely on the behavior as observed at discrete points in
time, but the process has a continuous behavior also between sampling
instances;
©
Chapter 13
◆
❖
Goodwin, Graebe, Salgado , Prentice Hall 2000
Problems can be avoided by refraining from designing solutions
which appear feasible in a discrete time analysis, but are known to
be unachievable in a continuous time analysis (such as removing
non-minimum phase zeros from the closed loop!).
The following rules of thumb will help avoid intersample
problems if a purely digital design is carried out:
◆
◆
◆
◆
Sample 10 times the desired closed loop bandwidth;
Use simple anti-aliasing filters to avoid excessive phase shift;
Never try to cancel or otherwise compensate for discrete sampling zeros;
always check the intersample response.