Automatic Matrix
Verification Platform
Gary Garo, Junhao Zheng(Spreadtrum)
Yanping Sha(Cadence)
CDNLive, Beijing
August 5, 2014
Outline
Why We Need Bus Matrix
Verification Automation?
Cadence VIP Introduction
Verification Environment
Automation
Summary
.2
Why We Need Bus Matrix
Verification Automation?
Cadence VIP Introduction
Verification Environment
Automation
Summary
.3
Why We Need Bus Matrix Verification
Automation?
 The SoC Is Becoming More Complicated
– The SoC will integrate more and more different IPs
– More CPU/DSP cores and complex functional IPs are integrated
to one SoC.
.4
Why We Need Bus Matrix Verification
Automation?
 Bus Matrix Is The Core of SoC
– All components are connected to matrix and communicate with other
components via matrix
– The correctness and performance of matrix mandate the correctness
and performance of the SoC
.5
Why We Need Bus Matrix Verification
Automation?
 How To Verify Bus Matrix In SoC?
– The key of the verification is SoCs connection routes, not
matrix’s basic functions
– We need to make sure that every path between
input/output is verified
– Bus matrix is internally similar, input routed to output port,
the burst remain similar
– The automatic flow for matrix verification is feasible
.6
Why We Need Bus Matrix
Verification Automation?
Cadence VIP Introduction
Verification Environment
Automation
Summary
.7
Cadence VIP Introduction
 AMBA VIPs: AHB, AXI, APB, ACE
– Active mode: generates all kinds of burst
– Passive mode: checks protocol and collects data
 ICM(Interconnect Monitor)
– Scoreboard for bus matrix
– Check data integration and matrix connected relation
– Support ID translation, address remapping, burst re-
construct(upsizing, downsizing)
.8
Cadence VIP Introduction
 IWB(Interconnect Workbench)
– Analyze the performance of the matrix
– Data collected by ICM
– Generated all kinds of analysis data/chart/report
– Automatically generate verification environment and test
case using matrix specification in xml format
– We didn’t deploy this automation flow, the flow don’t fit
our existing environment: local bus design, lack of system
matrix description based xml
.9
Why We Need Bus Matrix
Verification Automation?
Cadence VIP Introduction
Verification Environment
Automation
Summary
. 10
Verification Environment Automation
 Bus Matrix Excel Based Specification
– Matrix name
– Number of masters/slaves
Name
ap_ main_ mat rix
Mas t ers
2
Slav es
3
VFile
#AXI
ap_ main_ mat rix . v
Ins t anc e
– Protocol type: AHB/AXI/APB
`HIER_ AP_ SYS
0x 0FC0_ 0000 ~
GPV Addres s (2MB)
0x 0FCF_ FFFF
Arbitration
– Verilog file for masters/slaves
ID Bitwidth
Data Bitwidth
Protocol
– Instance hierarchical path
Clock
Function
Port Name
– Width for id and data
– Clock/Reset name
NA
NA
NA
NA
32
32
AHB
AHB
arm_mclk
arm_mclk
ARMI
ARMD
armi
armd
M0
def.
NA
def.
def.
32
4 32
NA
32
M1
St art Addr
EndAddr
AHB
arm_hclk
arm_ahb ahb
S0
0x0000_0000
0x0000_FFFF
AXI
arm_xclk
arm_axi
S1
0x1000_0000
0x1FFF_FFFF
APB
arm_pclk
arm_apb apb
S2
0x2000_0000
0x2FFF_FFFF
axi
– Function: channel name, master and slave with same name will be
connected to build up the matrix interconnect
– Port name: support simple pattern match
– Channel ID: master use M0-Mn, slave using S0-Sn
– Active/Passive flag & Memory/Register flag
. 11
Verification Environment Automation
 Configuration Files Generation
– Script parser the excel file, analyze the topology
– Calculate all possible data path based on the topology and
address mapping. Used for test case auto-generation
– Configuration files used for RTL generation
– Configuration files used for verification environment
generation
. 12
Verification Environment Automation
 Verification Environment Configuration Files
– VIP configuration files describe the chip bus topology and matrix details
information
– Project includes one top config file, list all the matrix config files name in
the top file
. 13
Verification Environment Automation
 Verification Environment Configuration Files
– Matrix configuration files describe the
matrix config information and masters/
slaves detail information
. 14
Verification Environment Automation
 Verification Environment Generation
– Take the VIP configuration files then generate UVM
environment using Cadence VIPs
– Instantiation of Cadence VIP
• Instantiation active masters/slaves and connect to DUT
• Instantiation passive masters/slaves and connect DUT
– UVM environment generations
• spdMtrxActTopSve: environment for active components
• spdMtrxPasTopSve: environment for passive components
– Test cases generations
. 15
Verification Environment Automation
 Based Class
– Based class for AHB, APB, AXI, ICM, matrix configuration
and matrix environment
– AHB, APB, AXI, ICM classes are pre-generated and not
changed over project
– Matrix configuration and matrix environment classes are
generated with script
. 16
Verification Environment Automation
 Verification Environment
. 17
Verification Environment Automation
 spdMtrxActTop
– Instantiated and config active master VIPs
– Connected active master VIPs
. 18
Verification Environment Automation
 spdMtrxPasTop
– Instantiated and config passive master/slave VIPs
– Connected passive master/slave VIPs
– Override cdnIcmUvmInsatnce and cdnIcmUvmMonitor
– Instantiated ICM to check the matrix data integration and
generate performance analysis statistics
. 19
Verification Environment Automation
 Function Coverage Monitor
– Functional coverage monitor generated for passive environment
. 20
Verification Environment Automation
 Test Cases Generates
– All masters to slaves address mapping traverse
– All size and burst type traverse
– Direct cases to fill the function coverage holes: no covered
connection route
. 21
Why We Need Bus Matrix
Verification Automation?
Cadence VIP Introduction
Verification Environment
Automation
Summary
. 22
Summary
 An automatic flow for bus matrix verification using
Cadence VIPs
 Quickly build verification environment for matrix
 Complete verification for matrix connection
 Statistics analysis for matrix performance
 Greatly speed up project progress
 Help Cadence to improve their products and add
new features to next version
. 23
Thank you!