P09311: Interface for Multi-purpose Driver/data Acquisition System Test Plan By: Adam Van Fleet, David Howe, TJ Antonoff, Mike Doroski, Andrew Weida MSD I & II: TEST PLAN 1.1. Introduction The goal of this project is to design and implement a functional interface for the field-programmable gate array (FPGA)-based multi-purpose driver/data acquisition system developed in MSD P08311. This interface will allow for data acquisition via several different communication channels: USB, Bluetooth, wireless USB, and Ethernet. Motivation for this work stems from the desire for real-time data acquisition of critical systems in robotics. Major goals to be achieved include re-design of interface between data acquisition board and FPGA, evaluation and implementation of the above-mentioned communication channels between personal computer (PC) and FPGA, and design of a graphical user interface (GUI) on a PC. The project team will be divided into subgroups to accomplish these goals. 1.2. Sub-Systems/ Critical Components Being Tested 1.3. Approval Approved by: Team Members – A. Van Fleet, M. Doroski, A. Weida, D. Howe, TJ Antonoff. Guide – Professor George Slack Sponsor – Dr. Marcin Lukowiak 1.4. Test Strategy 1.4.1. Product Specifications and Block Diagram Engr. Spec. # Importance Source Unit of Measure Margin al Ideal Value Value ES1 MED CN5 ES2 MED CN6 ES3 MED CN7 Specification (description) USB Transfer rate min of 1.5Mbits/s and max 12Mbits/s Bluetooth Transfer rate min 1.2 kb/s and max 921.6 kb/s 100% message transfer percentage (no lost packets) ES4 ES5 ES6 LOW MED HIGH Packets 0 100% # of Currently disregarded, until CN17 Option for Multiple Bluetooth Connections modules 3 3 1 module working. CN4 FPGA Programming Language Language VHDL VHDL CN16 Analog Data Resolution Bits 12 12 ES7 ES8 HIGH HIGH CN16 CN16 Number of Analog Data Channels Number of Digital Data Channels Channels Channels 16 12 16 12 ES9 HIGH CN16 Analog Sampling Rate kS/s 20 20 ES10 HIGH CN16 Digital to Analog Data Supply Rate kHz 20 20 ES11 HIGH CN16 Digital Sampling Rate kS/s 10 10 ES12 HIGH CN16 Digital Data Supply Rate kHz 10 10 Mb/s 8 8 kb/s 200 921.6 Comments/Status Analog Input should be no more than 10 KHz Analog Output will be updated at the same rate as input is taken As fast as necessary for ASIC As Fast as necessary for ASIC Functions (hardware) and Features (software, customer needs) Test 1 – DAQ Operation *Notes: The Data file used in testing is generated using ARBExpress, and contains values comparable to a 0-5V sin wave. I) Analog Testing (Basic Functionality) o Attach sin-wave generator to Analog input of DAQ, the produced output is looped through the FPGA and fed into the Digital-Analog converters of the DAQ. This converted output is viewed on an oscilloscope to compare against input signal. o Run input signal at 2.5Vpp and 9-11 kHz frequency, checking various increments. o Run input signal at 3.3Vpp and 2-10 kHz frequency, checking various increments. o Run input signal at 5Vpp and 2-10 kHz frequency, checking various increments. o Run input signal at +/- 12Vpp and 9-11 kHz frequency, checking various increments. o If the amplitude and frequency of the output profile match that of the input profile, it is confirmed that the number of data channels and resolution match specification values. II) Digital Testing (Basic Functionality) o Attach square-wave generator to Digital input of DAQ, the produced output is looped through the FPGA and fed into the digital outputs of the DAQ. The output is viewed on an oscilloscope to compare against the input signal. o Run input signal at 3.3Vpp and 9-11 kHz frequency, checking various increments. o If the amplitude and frequency of the output profile match that of the input file, the test passes. III) Digital Testing (FPGA as ASIC stand-in) o To simulate the ASIC controller, connect a second Spartan-3 FPGA to ports A1, A2 or B1 of the DAQ. Load a digital counter, “DigCounter.VHD” to this FPGA. The counter will count from 0 to 255 in binary, to represent the full range of 8bit values which can be transmitted by the system. Utilizing the Bluetooth device, receive the data generated by the counter at the maximum data transfer rate allowable by the device, and save it to the data file “BT_Dig_Check”. Repeat this process for the USB device, with data saved to “USB_Dig_Check”. Compare the files to the known binary counting sequence (00000000 to 11111111) to verify results. IV) Analog Inputs o Pass 12Vpp sin wave into each analog input, one at a time. o Using an oscilloscope, measure the corresponding ‘test point’, integrated into the PCB. o Match the o-scope waveform to the function generator input. V) Analog Inputs (Full Load) o To test the analog inputs under full load, we require a function generator signal applied to each of the 16 analog inputs. The use of 16 function generators is impractical. Therefore, split two function generator outputs (set to the maximum derived channel frequency and 10Vpp) into two sets of 8 parallel signals by use of wire. Generator 1 will output a square wave, while generator 2 will output a ramp. This will make debugging of inputs an easier task. Run each input line of the sin-wave generator to an even numbered analog input port, as mapped out in the documentation. Run each input line of the ramp-wave generator to an odd numbered analog port, as mapped out in the documentation. Monitor the output of each channel on the oscilloscope, as well as verify the inputs at the ports to ensure proper connection. Collect the transferred data and save to file “Analog_Check”. Review the file to ensure data was properly transferred. o We expect the current outputs of the DAQ to be on the order of milliamps. Use a digital multi-meter at each current output node to check the value, and record it in a test-value table. Choose a resistor on the scale of kilo-ohms to ensure an output reading in the volts range. A value of 1kOhm is selected for P09311 testing. VI) Digital Inputs o Pass 3.3Vdc (confirmed with o-scope) to each digital input, one at a time. o Jumper J11/J12 to J7 in order to correctly measure output. o Using an oscilloscope, measure the corresponding test points at the ZIF socket pin at J15. VII) Power Supply o Plug in 12V (250w) power supply to AC outlet. o Attach Oscilloscope probes to pins 1 and 2 to test the +3.3Vdc signal. Expect a flat line @ 3.3V. o Attach o-scope probes to pins 4, 6, 19 and 20 to test the +5Vdc signal and pin 18 for the -5Vdc signal. Expect flat lines at +/- 5Vdc respectively. o Use o-scope probes to pin 10 to measure +12Vdc signal, and pin 12 for -12Vdc. Expect flat lines at +/-5Vdc respectively. o Use o-scope probes on pins 3, 5, 7, 13, 15, 16 and 17 to test the Ground. Expect 0Vdc flat line for each. o Attach power supply to DAQ board and power on. LED Indicators will illuminate if power is correctly passing from the power supply to the board. Examine all LEDs for illumination. Test 2 – FPGA Operation I) Component level testing via ModelSim. a. Shift Register b. 2-1 Mux c. 1-2 DeMux d. 48-24 Mux e. 24-48 DeMux f. Control Logic g. Buffers h. Dual buffer i. Input/Output Finite State Machines j. UART Transfer/Receive State Machines k. USB Read/Write State Machines II) Integration level testing via ModelSim a. Combine components to test system compatibility. III) System level testing a. Combine all components of the system to test system performance. Test 3 – USB Module o Attach USB module from PC to FPGA. o Utilizing a VHDL loop program, send a 1-byte signal from the PC to the FPGA through the USB module, which will be looped back to the PC. o Check the received packet against the sent packet for any bit errors. o Transfer data file of known size via USB port, utilizing a clock to monitor transfer time. Calculate the transfer rate using the known data size and time elapsed, and compare to the specification of 1.5Mb/s to 12Mb/s. Test 4 -- UART (Bluetooth) Module o o o Connect UART transmit/receive module to a Processing/Forwarding Block as shown in the above diagram. The Processing/Forwarding Block directly receives the RX data from the RS232 line and alters the data in a predictable fashion (for example convert numerical ASCII characters to spaces) before forwarding the data back to the UART block to be sent out over the TX data line. Connect the programmed UART module to a PC via RS232. Use a communication terminal program such as HyperTerminal in windows to send ASCII data to the FPGA. If the UART component is functioning correctly the data sent should be echoed back out on the terminal screen (while numerical characters are not if data processing is used) Transfer a data file of known size, containing data corresponding to a 10Vpp sin wave, via the Bluetooth module, utilizing a clock to monitor transfer time. Calculate the data transfer rate using the known data size and time elapsed, and compare to the specification value of 1.2kb/s to 921.6kb/s. This should be dependent on Baud rate. Test 5 – GUI Interface o Attach both BT and USB modules from the PC to the FPGA. o Select (via the GUI) which module is operational, and can begin to send pre-developed bit data from an input file on the PC. Confirm the connection status correctly displays the selected device. Send a test byte through the loop to confirm that the connection status is operating correctly. o The pre-developed input data file will contain a large (over 1,000) sequence of known numbers to be later received and reviewed to test for lost bits, using a program such as WinMerge. If the input and output files match, no data loss occurred.. o Run a VHDL counter (on rising edge of each clock cycle) to determine time elapsed during data transfer. Also record the amount of bit-data transferred. Calculate the transfer rate and compare to GUI display. o Compare transfer rate and lost packets to specification table for pass/fail criteria. Determine if measured transfer rate = Baud Rate. o Repeat process for alternate module. Test 6 – System Testing I) Forward Testing o Assemble system with Bluetooth switch enabled (later retest with USB switch enabled). o Transfer vectors from stored data file (PC) to the DAQ, monitoring the output on an oscilloscope from the Digital and DAC outputs. o Compare output data against known input file. II) Reverse Testing o Assemble system with Bluetooth/USB switch enabled. o Attach function generator to DAQ, sending a known digital or analog signal of 1-5Vpp and 2-10kHz. o Store the received values in a file on the PC, and graph them using MatLab. o III) IV) V) Compare the graph of the saved file values against the input waveform. o Repeat process for analog or digital respectfully. Full System Test o Assemble full system with Bluetooth or USB enabled. o Transfer vectors from PC through DAQ back to PC, and store in data file. o Compare the received data file against the PC output data file for consistency. o Repeat the process for the USB/Bluetooth device as necessary. This will check for the system transferring data without lost bits, as well as the rates of transfer. o Additionally, transfer a large data file for an allotted time of 10 seconds. Upon completion, calculate the number of bits transferred over the time elapsed, to calculate the sampling rate. Check these values for both Analog and Digital against the specification table. Resolution Test o Pass a known analog sin wave from the function generator through the ADC. o Pass the ADC output through the DAC, and monitor the output on an oscilloscope. o If the output matches the input, test confirmed. Sampling Rate Test (Analog & Digital) o Perform the Resolution Test at 9 kHz, 10 kHz and 11 kHz frequencies. Continue ramping in 1 kHz increments up until aliasing is observed in the output. o Multiply the frequency of the first signal to show aliasing by 2 to obtain the approximate sampling rate of the system. o If this sampling rate ~20 kHz, test passes. 1.4.2. Test Equipment available o Digital Oscilloscope: Agilent 54622D o Function Generator: Agilent 33250A o Digital Multimeter: Agilent 34401A o PC: Personal Computer (EE Lab) o ModelSim software – FPGA sub-components 1.4.3. Risks and Contingencies o Risk: Data Acquisition board does not work, or does not work as specified by P08311. o Test board in early testing stages. Troubleshoot for broken components and replace as able. A scrapped board will result in project termination. Risk: FPGA board is damaged or otherwise becomes nonoperational. This risk applies to all other hardware components including USB and Bluetooth modules. o Risk: Data rates do not match ideal values provided by manufacturer. 1.5. Purchase another FPGA (or other component), expecting 5-7 business days shipping. Purchase a faster device, loosen design specifications with customer approval or evaluate running multiple devices in parallel to improve speed. Definitions Forward Testing Testing the data flow from the PC to the DAQ, through the FPGA and selected interface. Reverse Testing Testing the data flow from the DAQ to the PC through the FPGA and selected interface. 1.6. References Spartan-3 Board Reference Material http://www.digilentinc.com/products/detail.cfm?prod=s3board&nav1=products&n av2=programmable USB Adapter (DLP-USB245M) http://www.dlpdesign.com/usb/usb245.shtml Bluetooth Development Kit (Parani ESD1000SK) http://www.rfphone.com/files/esd110.pdf Digital to Analog Converter http://www.analog.com/static/imported-files/data_sheets/ad5308_5318_5328.pdf Analog to Digital Converter http://cache.national.com/ds/dc/adc121s101.pdf