The term project is to design a VLSI circuit for a tiny chip. There are a few choices listed in part II. If you prefer some other topic, please stop by to discuss on it. Please let me know by Dec. 1st what your design topic is. Also, you are supposed to work individually.
The goal of the project is to design a realistic circuit in various contexts, such as a miniversion computer processor, digital signal processor and other application-specific processors.
The technology we will use is TSMC025 micron process with a standard cell library as we used in Homework 4. The standard cell library contains both schematic view and layout view for each basic cell. Similar to Homework 4, you need to design your whole circuit using the basic cells in the library without designing any of your own cells. Also, please make sure that the total layout area for the circuit does not exceed 5000 Lambda by 5000 Lambda, where Lambda = 0.13 micron. The layout is supposed to fit into a tiny chip, or pad frame, which has 40 pads. 2 pads are for VDD and GND, and the rest 38 pads are bi-directional pads used for input/output signal and other signal such as reset signal. The number of pads is usually less than the total number of input/output signals for your design. So, you will have to share some pads when loading or transmitting data.
For example, for a 32-bit adder, there are 64 input signals, which means that you can not supply all input signals in parallel once.
For some examples of standard cell design and tiny chip frame, please go to: http://www.enee.umd.edu/vdal/magic_rangers_cpu.html
http://vlsi.cornell.edu/~rajit/474/F01/ http://www.owlnet.rice.edu/~elec422/1998/wakin/vlsi/report.html
Project includes a final report, which will be due on 4pm of Dec 15th . In the last class of semester, which is Dec 10th, you need to present your project during the class time.
Please prepare 10-20 slides for your project. Detailed instructions for presentation and project report will be posted when time comes.
Please start early . Think about design at schematic level and layout level through carefully so that you do not run into unanticipated problems. For some challenging and interesting design, you may need to look into more reference books.

There are 9 candidate topics listed below. You can select any of them based on your preference.
But note that due to the differences between the projects, each project is rated based on its difficulty, which will be one of the factors for project grades.
In the following, L denotes relatively low difficulty, M moderate difficulty and H high difficulty. Finally note that the final project accounts for 40% of the final grade.
P1: A 32-bit binary tree comparator design (L)
A binary tree comparator consists of a binary tree in which each leaf node is capable of comparing two one-bit numbers Ai and Bi and generating a 2-bit output indicating whether Ai is equal to, greater or less than Bi. Each internal node is capable of receiving the partial comparison results from the left and right children (corresponding to the left and right substrings) and propagating the effective comparison result to its own parent.
Eventually, the root node generates a 2-bit result which indicates the result of comparing the N-bit numbers A and B. N is usually assumed to be a power of 2. The binary tree comparator has the advantage of comparing two n-bit numbers in O(logN) times as opposed to the O(N) time taken by a linear array comparator. The following figure is merely illustrative of the idea.
In the example, comparison of 0110 and 0101 on a 4 leaf binary tree is shown. The notation L/R is used to denote which of the numbers covered by a node is larger.
0 0
=
= =
1 1
L
1 0
L
R
L
0 1
Performance requirements: your comparator should support at least 500Mhz clock frequency.
P2: A 32-bit carry-look-ahead adder design (M)
Please check Chapter 11 out in the textbook for this topic.

P3: An 8-bit MIPS Processor design (M)
You can check into any computer architecture book on a MIPS processor. Note that the
8-bit here means that your input data width, not necessarily the width for the instruction.
Also, you should use a clock to fetch instructions stored in a small memory (such as some
DFFs) for this project and be able to show the execution results.
P4: A 32-bit radix-4 or radix-2 booth encoding multiplier design (M-H)
Please refer to the other recommended textbook Weste, Page 698-702 or stop by to ask
Performance requirements: the delay from the input to output should be less than 10ns when outputs are attached with load capacitor of 100fF.
P5: A 32-bit divider design (M- H)
Please refer to a separate detailed description posted on course webpage.
P6: Digital FIR (Finite Impulse Response) filter for DSP Processor (M-H)
Please talk to me if you are interesting in working on such a design. I have a reference book on this.
P7: Butterfly Unit Design of Fast Fourier Transform Algorithm for DSP Processor
(M-H)
P8: Decimation Comb filter design for a DSP Processor (M-H)
P9: A Viterbi decoder for DSP processor (H)
Please refer to a separate detailed description posted on course webpage.
Note:
(1) for Project 5 and 9, please look into the detailed descriptions. Your design need to meet the design requirements stated on the descriptions. But disregard some irrelevant information such as the technology and model used, since we will use
TSMC025 in Cadence environment.
(2) The priority goal is to make your design as fast as possible (minimized delay or fastest clock)
(3) All projects needs to have a working schematic. The design should be verified using schematic simulations.
(4) To reduce your workload, again layout with correct DRC and LVS is optional with 20 bonus points.