DESIGN AND VALIDATION OF NTRU PUBLIC-KEY CRYPTOSYSTEM
A Project
by
Preeti Kamat
Jaykumar Patel
Approved by:
__________________________________, Committee Chair
John Balachandra, Ph.D.
__________________________________, Second Reader
Preetham Kumar, Ph.D.
____________________________
Date
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Students: Preeti Kamat and Jaykumar Patel
I certify that these students have met the requirements for format contained in the
University format manual, and that this project is suitable for shelving in the Library and
credit is to be awarded for the project.
___________________________, Graduate Coordinator
Preetham Kumar, Ph.D.
Department of Electrical and Electronic Engineering
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___________________
Date
Abstract
of
DESIGN AND VALIDATION OF NTRU PUBLIC-KEY CRYPTOSYSTEM
NTRU cryptosystem is a relatively new Public Key Cryptosystem. Public Key
Cryptography or Asymmetric Cryptography is used in areas of digital signatures and key
exchange. RSA is an acclaimed Public Key cryptosystem that is in use since 1977.
However, it is very slow in comparison with Symmetric Cryptography systems in
processing bulk data encryption and decryption. In contrast, NTRU runs much faster on
large data systems than RSA and has become a very popular algorithm today in terms of
data encryption and decryption. The key generation process in NTRU is much faster than
that in RSA, and this process is one of the most important processes in Public Key
Cryptography.
FPGAs are one of best hardware used for implementing reconfigurable
computing. Reconfigurable computing is very popular because it is capable of computing
many different applications with a great speed. An important feature of reconfigurable
computing is that computations are performed in hardware, but the flexibility of a
solution in software is maintained at the same time.
The purpose of this project is to initially explain the NTRU algorithm which is a
proprietary algorithm patented by NTRU Cryptosystems. NTRU Crptosystems has
recently become a part of Security Innovations, a leading provider of security solutions.
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This project advocates a hardware implementation of the NTRU public-key cryptosystem
which is made of three important phases- Key Creation, Encryption and Decryption. The
system has been implemented in Verilog HDL, simulated using Synopsys from VCS and
synthesized using Xilinx ISE Design Suite.
________________________________________________, Committee Chair
John Balachandra, Ph.D.
________________________
Date
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ACKNOWLEDGEMENTS
We would like to acknowledge and extend our heartfelt gratitude to the following persons
who have made the completion of this project a reality.
Our Project advisor, Dr. John Balachandra, for his valuable advice on the many
algorithms needed to understand and implement NTRU and his constant guidance and
encouragement.
A very sincere thank you, to our Graduate advisor, Dr. Preetham Kumar, for his
continued guidance and support throughout the course of this project
A note of gratitude to our friends, for helping us in the many times we needed a different
point of view than our own
Finally, we would like to extend gratitude to families, for supporting us all through and
most of all God, for giving us the strength and opportunities to be what we are today
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TABLE OF CONTENTS
Page
Acknowledgements……………………………………………………………………....vi
List of Tables…………………………………………………………………………….. x
List of Figures………………………………………………………………………….... xi
Chapters
1. INTRODUCTION ……………………………………………………………………1
1.1 Overview…………………………………………………………………....... 1
1.2 Private Key Cryptosystem ………………………………………………....... 4
1.3 Public Key Cryptosystem ………………………………………………….... 5
1.4 NTRU Public Key Cryptosystem ………………………………………......... 6
2. POLYNOMIAL ALGEBRA AND NUMBER THEORY ………………………….... 8
3. DESIGN OF NTRU PKCS ..………………………………………………………… 11
3.1 NTRU Multiplier Design………………………………………………........ 11
3.2 Processing Unit ………………………………………………………..…… 14
3.3 NTRU Multiplier or PM (Polynomial Multiplier) ……………………......... 19
3.3.1 COEFF……………………………………………………………. 19
3.3.2 SHIFTER AND COUNTER…………………………………........ 20
3.4 Key Creator…………………………………………………………………. 20
3.5 NTRU Encryptor………………………………………………………......... 21
3.6 NTRU Decryptor………………………………………………………........ 22
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3.7 NTRU PKCS ……………………………………………………………….. 24
4. VALIDATION OF NTRU PKCS ……………………………………………............ 25
4.1 Design Verification ………………………………………………………… 25
4.2 NTRU PKCS – Testbench …………………………………………………. 27
5. SIMULATION RESULTS AND WAVEFORMS ..………………………………… 32
5.1 Low level of security, parameters N=107, q=64, p=3 ……………………... 32
5.2 Small example parameters N=11, q=32, p=3 ……………………………… 37
6. SYNTHESIS FIGURES ……………………………………………………………. 45
6.1 NTRU_Decryptor_Blk ………………………………………………. 45
6.2 NTRU_Decryptor ................................................................................. 46
6.3 NTRU_Encryptor_Blk ......................................................................... 47
6.4 NTRU_Encryptor ................................................................................. 48
6.5 NTRU_Key .......................................................................................... 49
6.6 Mult_Mod............................................................................................. 50
6.7 Polynomial_Mult ................................................................................. 50
6.8 Barrel_shift ………………………………………………………….. 51
6.9 Coeff ……………………………………………………………….... 51
6.10 Bit4_Cnt ………………………………………………………….... 52
6.11 Proc_Unit …………………………………………………………... 52
6.12 Const_Mult ………………………………………………………… 53
7. CONCLUSIONS AND FUTURE WORK…………………………………………. 54
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Appendix A. RTL Code ………………………………………………………………... 57
A.1 Parameters N=107, q=64, p=3 …………………………………………….. 57
A.2 Parameters N=11, q=32, p=3 …………………………………………........ 77
Appendix B. Synthesis Reports ………...……………………………………………… 96
B.1 NTRU_Key ………….…………………………………………………….. 96
B.2 NTRU_Encryptor ………………………………………………………… 108
B.3 NTRU_Decryptor ………………………………………………………… 123
Appendix C. The NTRU Public Key Cryptosystem (PKCS) ……………...………..... 137
C.1 NTRU PKCS Parameters………………………………………………..... 137
C.2 Key Creation……………………………………………………………… 138
C.3 Encryption………………………………………………………………… 140
C.4 Decryption………………………………………………………………… 141
References…….……………………………………………………………………….. 144
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LIST OF TABLES
Page
1. Table: 1 PU Truth Table...….………………..…………………………………. 15
2. Table: 2 PU Integer Value..…..………………………………………………… 16
3. Table: 3 PU K-Map..……………………………………………………………. 17
4. Table: 4 NTRU Security Parameters………………………………………….. 138
5. Table: 5 Small Security Parameters ................…………………………........... 138
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LIST OF FIGURES
Page
1.
Figure 1: Private Key Cryptosystem.…………………………………………….. 4
2.
Figure 2: Public Key Cryptosystem….…….…………………………………….. 5
3.
Figure 3: Polynomial Multiplication ...…….…………………………………… 12
4.
Figure 4: Partial Product Array………….……………………………………… 13
5.
Figure 5: Processing Unit………….………………………………………......... 14
6.
Figure 6: 8 - Bit Full Adder………….…….………………………………........ 17
7.
Figure 7: Coefficient Multiplier….. ...…….……………………………………. 18
8.
Figure 8: NTRU Multiplier Design.…..…………………………………............ 19
9.
Figure 9: Key Creator…………..……….…………………………………........ 21
10.
Figure 10: NTRU Encryption..…….………………………………………........ 21
11.
Figure 11: Mult_Mod……………….…….……………………………….......... 22
12.
Figure 12: NTRU Decryptor…….........…….…………………………………... 23
13.
Figure 13: NTRU PKCS…………...…….……………………………………... 24
14.
Figure 14: NTRU_Decryptor_Blk Top Level…………………………………... 45
15.
Figure 15: NTRU_Decryptor_Blk Logic Block……………………………....... 45
16.
Figure 16: NTRU_Decryptor Top Level..….………………………………....... 46
17.
Figure 17: NTRU_Decryptor Logic Block....………………………………....... 46
18.
Figure 18: NTRU_Encryptor_Blk Top Level………………………………....... 47
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19.
Figure 19: NTRU_Encryptor_Blk Logic Block……..………………………..... 47
20.
Figure 20: NTRU_Encryptor Top Level…….………………………………...... 48
21.
Figure 21: NTRU_Encryptor Logic Block….………………………………….. 48
22.
Figure 22: NTRU_Key Top Level.......…….…………………………………... 49
23.
Figure 23: NTRU_Key Logic Block…….....…………………………………… 49
24.
Figure 24: Mult_Mod Logic Block…..…….………………………………........ 50
25.
Figure 25: Polynomial_Mult Logic Block....…………………………………… 50
26.
Figure 26: Barrel_Shift Logic Block...…….…………………………………… 51
27.
Figure 27: Coeff Logic Block…..... ...…….…………………………………..... 51
28.
Figure 28: Bit4_Cnt Logic Block........…….………………………………….... 52
29.
Figure 29: Proc_Unit Logic Block.......…….…………………………………… 52
30.
Figure 30: Const_Mult Logic Block ...…….………………………………….... 53
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