4 Bit SQF Multiplier Based On Booth Encoder
ABSTRACT:
We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and
Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding
method is one of the algorithms to obtain partial products. With this method, the number of
partial products decreases down to the half compared to the AND array method. We have
fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a
processing frequency of 20 GHz with the bias margin 25%. The frequency of this circuit
increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The
circuit area of the multiplier designed with the Booth encoder method is compared to that
designed with the AND array method.
Key-Words: FFT, multiplier, SFQ, superconductive circuits.
INTRODUCTION:
DRIVING technologies of low power consumption are required as the world trend,
because high integration causes increase of power dissipation. Single-Flux-Quantum (SFQ) logic
circuits attract much attention because of low power dissipation and high throughput. Although
the superconductive circuits need a refrigerator system, SFQ circuits have higher advantage
compared to semiconductor circuits. The advantages of the SFQ logic are the operation speed
and the power dissipation. This technology is adopted at various scenes that require high speed
operation. The Fast Fourier Transform (FFT) is among the best field to adopt this technology.
The FFT circuit is one of the core components in digital signal processing. We have already
developed plural parallel multipliers that contain serial parallel multipliers, a multiplier with
ripple carry adder. Another serial parallel multiplier was also designed and integrated. The AND
array method and the Booth encoding method are algorithms for partial product generation.
The reduction of partial products is required for higher-bit multiplication, because the addition
of partial products stage occupies a large circuit area. In this paper we present test chips for
signed parallel 4-bit multipliers with an AND array or a Booth encoder that are designed for a 4bit FFT processor with target clock frequency of over 20 GHz. Test chips are designed by using
cell-based techniques and tools (CONNECT cell library [6]) and fabricated through the ISTEC chip
foundry system.
BLOCK DIAGRAM:
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Fig: The structure of the 4-bit parallel multiplier. “X” and “Y” denote input data. “P” denotes
results of multiplier.
PPG: Partial Product Generator (PPG),
PPA: Partial Product Accumulator (PPA),
FSA: Final Stage Adder (FSA)
A 2-bit Booth encoder, a CSA tree and a 6-bit carry look-ahead adder are used for a multiplier
operation in the PPG block, the PPA block and FSA block, respectively. Fig. shows the diagram of
the designed multiplier with the PTLs, and Table III shows its specifications. The target
frequency is over 20 GHz that corresponds to the throughput, and the data length is signed 4bit. The multiplier has a 9-stage structure where the PPG block, the PPA block and the FSA block
consist of 3 stages, 1 stage and 5 stages, respectively.
HARDWARE AND SOFTWARE REQUIREMENTS:
Software Requirement Specification:

Operating System: Windows XP with SP2

Synthesis Tool: Xilinx 12.2.

Simulation Tool: Modelsim6.3c.
Hardware Requirement specification:
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
Minimum Intel Pentium IV Processor

Primary memory: 2 GB RAM,

Spartan III FPGA

Xilinx Spartan III FPGA development board

JTAG cable, Power supply
REFERENCES:
[1] Y. Horima, T. Onomi, M. Kobori, I. Shimizu, and K. Nakajima, “Improved design for parallel
multiplier based on phase-mode logic,” IEEE Trans. Appl. Supercond., vol. 13, pp. 527–530,
2003.
[2] T. Onomi, Y. Horima, M. Kobori, I. Shimizu, and K. Nakajima, “Implementation of phasemode arithmetic elements for parallel signal processing,” IEEE Trans. Appl. Supercond., vol. 13,
pp. 583–586, 2003.
[3] T. Onomi, K. Yanagisawa, M. Seki, and K. Nakajima, “Phase-mode pipelined parallel
multiplier,” IEEE Trans. Appl. Supercond., vol. 11, no. 1, pp. 541–544, Mar. 2001.
[4] Y. Horima, I. Shimizu, M. Kobori, T. Onomi, and K. Nakajima, m“Comparison between and
AND array and a booth encoder for large scale phase-mode multipliers,” IEICE Trans. Electron.,
vol. E86-C, pp. 16–23, 2003.
[5] A. Akahori, M. Tanaka, A. Sekiya, A. Fujimaki, and H. Hayakawa, “Design and demonstration
of SFQ pipelined multiplier,” IEEE Trans. Appl. Supercond, vol. 13, no. 2, pp. 559–562, 2003
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