N14
Serial Protocols
device level
RS-232
RS-422
RS-485
USB
CAN
IEEE 1394 Firewire
chip level (all chips on same board with common GND)
SPI
I2C
Layers
electrical layer
1) voltages
a) logic high, logic low
b) single ended, differential
c) distance
d) supply power to another device
2) read/write/tri-state
3) connectors
4) pinouts
5) collision arbitration
byte layer
1) bits per byte, parity
2) lsb first, msb first
3) bit speed
a) fixed baud (start bit, number of stop bits)
b) clocked
4) character encoding (ASCII)
packet layer
1) address
a) receiver device
b) sender device
2) number of bytes
3) checksum
4) collision arbitration
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EIA RS-232
between DTE (data terminal equipment) and a DCE (data communication equipment = modem)
originally current loop driven, later changed to voltage level driven
UART (universal asynchronous receiver transmitter)
software UART emulation
hardware UART buffer size
inverted logic
logic HI = 1 = mark = -3V to -25V
logic LO = 0 = space = +3V to +25V
originally D25 connectors
point-to-point connections use one receiver per transmitter
no collision detection needed
DTE = D9 male
TD pin 3
RD pin 2
signal GND pin 5
DCE = D9 female
TD pin 2
RD pin 3
signal GND pin 5
chassis GND pin 9
chassis GND pin 9
handshaking lines
DCD (data carrier detect) into DTE pin 1
DTR (data terminal ready) from DTE pin 4
DSR (data set ready) into DTE pin 6
RTS (request to send) from DTE pin 7
CTS (clear to send) into DTE pin 8
most common is 8 data bits, no parity bit, 1 stop bit (8N1) = 10 bits / byte (1 start, 8 data, 1 stop)
fixed baud rate (bits per second) = 300, 1200, 2400, 4800, 9600, 14400, 19200
can now use 28.8 K, 38.4 K, 57.6 K, 115.2 K
old teletypes = 110 baud (2 stop bits)
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hold line at logic HI
drop line to logic LO for start bit with duration (1/baud) seconds
transmit data bits at fixed rate with lsb first and msb last
transmit parity bit if needed
hold line at logic HI for stop bit(s)
space
+12V
start
b0
b1
b2
b3
b4
b5
b6
b7
stop
mark
-12V
RS-232 ASCII cap K= hex 4B= 0100 1011
+12V
space
start
1
1
0
1
0
0
1
0
stop
-12V
mark
TTL level ASCII cap K = hex 4B = 0100 1011
+5V
mark
start
1
1
0
1
0
0
1
0
stop
0V
space
usually use prearranged baud rate between devices
can have auto baud recognition
be careful of data over-run if UART does not have a buffer or CPU cannot keep up
may need to flush UART buffer to get most recent information
hex 4B = cap K
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50 feet maximum
only one receiver per transmitter
does not explicitly provide power to DCE (some “port powered” devices parasite from RTS)
requires TTL/CMOS logic to RS-232 level drivers - MAX232 chip
http://www.beyondlogic.org/serial/serial1.htm#40
no standard packet protocol
legacy COM port on PC
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EIA RS-422
similar to RS-232
each signal uses a differential voltage between two wires rather than single ended voltages
relative to GND
Tx is two wire twisted pair, Rx is two wire twisted pair
±6 V
multi-drop with up to 10 receivers per transmitter
one master, 10 slaves
not all slaves can talk back to master unless they have tri-state outputs
better noise immunity
higher speed up to 100K baud
longer distance up to 4000 feet
typically used to boost RS-232 over longer lines
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RS-485
similar to RS-422 but only one twisted pair
true multi-point bus
up to 32 drivers and 32 receivers on one twisted pair of wires up to 4000 feet
requires tri-state Tx drivers
requires device addresses
requires bus arbitration – usually software master-slave
device defaults to receiver mode
listens for end of current byte being sent on twisted pair
can sense bus collision by current draw
recommend bus terminating resistors Rt = 120
requires TTL/CMOS logic to differential drivers - MAX485 chip
1
RO
Receiver Output
if VA > VB+200mV then RO=HI if enabled
if VB > VA+200mV then RO=LO if enabled
Receiver Output Enable if /RE=LO then RO is enable
if /RE=HI then RO=hiZ
Driver Output Enable
if DE=HI then driver outputs are enabled
if DE=LO then driver outputs are hiZ
Driver Input
if DI=LO then VB > VA if enabled
if DI=HI then VA > VB if enabled
2
/RE
3
DE
4
DI
5
6
7
8
GND
A
Noninverting I/O
B
Inverting I/O
VCC Positive supply voltage
4.75 V < VCC < 5.25 V
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USB (Universal Serial Bus)
two wire differential multipoint bus
four pins – twisted pair data D+ and D-, +5V, GND
USB 1.1 up to 12 Mbps
USB 2.0 up to 480 Mbps with 5 m cable
USB 3.0 up to 4.8 Gbps
CMOS voltage levels in full speed (FS) and low speed (LS) modes
reduced voltage levels in high speed (HS) mode - low = 0V to 10mV, high = 360mV to 440mV
uses non-return to zero inverted (NRZI) logic
logic 0 transitions the voltage state (low to high, or high to low)
logic 1 does not transition state
up to 127 devices each with unique address
master device arbitrates traffic flow on the bus
significant protocol at packet level
three types of packets - handshake, setup, data
six styles of connectors for USB 1.1/2.0 – A, B, miniA, miniB, microAB, microB
maximum unit load of 150mA per device on +5 power line
maximum of 5 unit loads from bus master
USB to serial driver = FTDI FT232
provides TTL level TX, RX, RTS, CTS
requires USB drivers on PC that act like COM serial port
http://www.usb.org/home
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CAN (Controller Area Network)
two wire differential multipoint bus
requires CAN controller (similar to UART) and CAN transceivers (similar to MAX232)
many microprocessor families now provide CAN support
up to 1 Mbps at 40 m
nominally uses 0 to 5V
no standard connectors – often use D9 or RJ45
can provide power to slave devices
requires bus terminating resistors Rt = 120
significant protocol requirements at packet layer
includes collision arbitration
numerous SAE and ISO standards
msb first
identifier = 11b address of destination
control = 4b number of data bytes per packet (up to 8)
data = 8b per byte
CRC = 15b cyclic redundancy check
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OBD-II
IEEE 1394 Firewire
multi-point bus
up to 63 devices
1394b = 786 Mbps (now up to 3.2 Gbps)
can supply power to peripheral devices
can use direct memory access (DMA)
used primarily for video cameras
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SPI (Serial Peripheral Interface)
four wire interface (plus GND)
master device provides clock line
TTL or CMOS voltage levels and speeds (up to 70 Mbps)
SCK – serial clock (from master, shared by all chips)
MOSI – master output, slave input (shared by all chips)
MISO – master input, slave output (shared by all chips, slaves must have tri-state outputs)
CS – chip select (separate line to each slave from master)
typically data 8 bits with lsb first
can be longer and/or msb first based on slave chip
SPI send and receive subroutines in many programming languages
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I2C
two wire interface (plus GND)
SCL – serial clock (bi-directional but typically provided by master)
SDA – serial data (bi-directional)
typically only master drives the clock
each chip has a pre-assigned unique address up to seven bits long
uses open-drain output drivers and pull-up resistors
TTL or CMOS voltage levels and speeds (up to 1 Mbps)
master issues a special start sequence and then sends the address of a specific chip
typically 8 data bits with msb first (depends on slave chip)
data is presented on SDA and then SCL is pulsed
lower throughput than SPI but fewer wires
does not require multiple CS lines from master like SPI
I2C send and receive subroutines in many programming languages
http://www.robot-electronics.co.uk/htm/using_the_i2c_bus.htm
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