A LOW NOISE AND LOW POWER LNA FOR UWB SYSTEM
APPLICATION
Abstract
This paper presents the design of a 3.1-10.6GHz ultra wide band (UWB) low noise amplifier
(LNA) using resistive feedback gain enhancing technique for Ultra Wide band receiver. It is
an inductor less, low power, low noise LNA. Here the gain of the amplifier is increased and
the noise is reduced. The main advantage of this technique is very less power consumption
which is major requirement. It is having a power gain of 10.8 dB, a noise figure of 2.4 dB at
4.8 GHz and an IIP3 of -2.8dBm. The power consumed by the circuit is 8.9 mW. The
simulated results demonstrate that the LNA shows the largest bandwidth, the lowest power
consumption and lowest noise figure among the inductorless wideband LNAs.
Index terms:- LNA, ultra wide band (UWB), noise cancelling, inductorless, resistive
feedback
I. Introduction
UWB system is a technology which is capable of transmit datas over a wide range of
frequency bands from 3.1-10.6 GHz with very low power and high data rates. In recent years
UWB technology is so popular because this technology offers solution to the radio frequency
(RF) spectrum to coexist with other radio systems with zero interference. UWB technology is
well suited for short range and high speed wireless applications like cognitive radio, ground
penetrating radars, imaging etc. The UWB low noise amplifier (LNA) should possess certain
characteristics like good input and output return loss, flat gain over the entire bandwidth, low
noise figure for good sensitivity, low power consumption and a small chip area .
Traditionally, UWB LNA was developed to overcome the enormous bandwidth. The
distributed amplifier [2] provides wide bandwidth characteristics, good linearity and good
input and output impedance matching. On the other hand, it consumes a large DC current to
operate and occupies a larger chip area. The passive filter was also adopted for designing the
UWB LNA [3], which provides a wide input matching characteristic but it requires some
passive components like an inductor, which requires a large chip size. As a result the power
consumption is increased. Then the resistive shunt feedback technology [4] is introduced.
Here due to the absence of inductors size and power consumption is reduced. As a
consequence it degrades the noise performance because of the feedback resistor. Then the
noise cancelling technique [5] is introduced. In this case the noise is very low also good
impedance matching is done, but a trade off exists between gain and noise figure.
To overcome this problem noise cancelling gain enhanced technique is introduced.
Here the gain of the LNA is increased and the increase in gain can be used to relax the trade
off between voltage gain and noise figure.
Section II describes gain enhanced noise cancelling techniques. The circuit analysis
and design consideration for the proposed LNA is addressed. Section III shows the
experimental results, and Section IV gives the conclusions of this work.
II. CIRCUIT DESCRIPTION
A. Gain Enhanced Noise Cancelling Technique
The main idea is to produce the noises with opposite phase in different paths, and at the
output the noises will be cancelled by adding the signals. The noise cancelling circuit shown
in fig.1 consists of a transistor M1 ,a feedback resistor R F , and a voltage amplifier A1 having
amplification factor −AX which gives output with 180 degree phase difference with the input.
Another amplifier A2 of gain Ay is introduced at the output of M1. There is a noise current
In,M1 flowing from the drain to source of M1. The effect of the noise current is reduced by the
help of this technique without affecting the input impedance. So simultaneously noise
cancelling and impedance matching is done.
RF
RS
Y
A2
Ay(Vy+Vn,y)
X
Vx
M1
In
Vout+Vn,out
Vin
A1
-Ax(Vx+Vn,x)
Fig.1. LNA using gain enhanced noise cancelling technique
Due to the noise current In,M1 some noise voltage is produced at x and y. After amplification through
the amplifiers the two noise voltages are added and finally the output voltage due to noise becomes
Vn,out = Ay Vn,y − Ax Vn,x
= In,M1 ((R S + R F )Ay − R S Ax )
(1)
The output noise voltage is cancelled, when Vn,out = 0
Hence the noise cancelling condition becomes
AX = AY (1 +
Ax
Ay
RF
)
RS
R
= (1 + RF )
(2)
S
Now the overall gain becomes
AV =
Vout
VX
= AY (1 − g m1 R F ) − AX
When noise is cancelled the gain becomes
(3)
AV = −AY R F (g m1 +
1
)
RS
(4)
Here the gain is proportional to AY and R F . But large R F accounts for thermal noise and it
degrades the bandwidth. So by choosing a large gain amplifier AY the required overall gain
can be achieved with small size of M1 and R F which is the major advantage of this technique.
B. Circuit Analysis of the LNA
Vdd
RG
RD2
RD5
VD2
M4
M3
RFD2
Vo
RFD1
VD1
RS
M1
Cin
VG
M2
M5
Vin
Fig.2. Circuit diagram of the gain enhanced LNA
Fig.2 shows the proposed LNA. It consists of a noise cancelling gain enhancing stage and
an output buffer. R S is a 50Ω source impedance, which is connected to the LNA through a
large capacitor . R FD1 is a shunt feedback resistor and is used for wideband matching ,
sensing the signal and noise of input transistor M1 . The amplifier A1 is implemented by the
help of transistor M2 . It is a common source amplifier which will work as a inverter. The
combination of M3 and M4 constructs the amplifier A2 . Here two transistors are used to
design the amplifier A2 because by using two same transistors of small size in series the
overall gain will be the double of the gain of each transistors M3 and M4 , but the transistor
M3 will be operated by the help of the current flowing through the transistor M4 . As a result
by taking two transistors the total power consumed by the amplifier will be reduced
compared to the power consumed when it is implemented by one transistor. Here the two
transistors are connected in common gate connection as in AY no phase change is there. If
common source connection will be done then phase change will occur and another inverting
stage is needed to make it in phase which will cost for another transistor, more chip area,
more power consumption. Here M1 is connected to the source of M3 . So it will not draw any
current from the supply, it will be activated by the help of the current flowing through the
transistor M3 . Hence in this circuit the power consumption is reduced in a great manner as
three transistors are operating by the power consumed by a single transistor. R G and R D2 are
the transistors used for biasing purpose.
For output impedance matching there should be a circuit which will provide a gain of one
and will do the impedance matching. For that a source follower can be taken but it is not so
useful for low voltage application. So a resistive shunt feedback output stage is used in the
circuit which is constructed by using M5 , R FD2 and R D5 .
The input impedance is the parallel connection of the input resistance and input
capacitance of the circuit. At low frequency the input impedance is set to 50Ω. But at high
frequency the impedance will not be fixed as the impedance due to the capacitance will be
reduced. In order to make the effect of the capacitance zero we have to take smaller value of
capacitance, that means smaller M1 and M2 will be taken. If M1 will be small then
amplification will be less, but here amplification will not be reduced as the current of
transistor M3 and M4 is flowing through M1.
The equivalent small signal analysis of the overall circuit is represented here.
G1=G2
RFD1
gm3Vgs3
D1=S3
r03
r01
VG
gm4Vgs4
D2=D4
r04
gm2VG
gm1VG
r02
RFD2
D5
RD5
RD2
Vo
gm5VD2
r05
S1=S2=S5
Fig.3. Small signal representation of the LNA
The amplification factor of the two amplifiers A1 and A2 are expressed as
Ax =
VD2
VG
= g m2 R 2
(5)
1
VD4
Ay = V
D1
R2 RD2 ‖r02 ‖gm2 ‖(gm3 r03 +gm4 r04 )R1
≈R ≈
1
‖r
gm1 01
1
(6)
where R1 be the impedance at the drain of the transistor M1 and R 2 be the impedance at
the drain of the transistor M2 .
R1 = g
1
m1
‖r01
R 2 = R D2 ‖r02 ‖ g
(7)
1
m2
‖(g m3 r03 + g m4 r04 )R1
(8)
According to (2), the condition for noise cancellation is
g m2 (g
1
m1
‖r01 ) = 1 +
RFD1
(9)
RS
According to (4), the overall gain during noise cancellation becomes
ANC = −R FD1
1
‖(gm3 r03 +gm4 r04 )R1
gm2
1
‖r
gm1 01
RD2 ‖r02 ‖
1
(g m1 + R )
(10)
S
From equation (9), it is known that transistor M2 is of small size as g M2,A is proportional to
R FD1 and during noise cancellation process R FD1 is already taken as a small resistance. So the
conclusion is after the noise cancellation stage, the noise is mainly contributed by M3 and M4
and the noise factor becomes
R
γ
F= 1+RS
1
α gM3 RCG
CG
γ
+ αg
1
(11)
M4 RS
g
Where α = g M , g do is the channel conductance for VDS = 0 and γ is the noise parameter.
do
Now the buffer which is a resistive shunt feedback circuit at the output is having a gain of
V
RD2 (1−gM5 RFD2 )
AV = V o =
(12)
Rth +RD2
D2
R
R OUT = 1+g D2R
(13)
M5 D2
R OUT is set to be 50Ω. The buffer circuit provides good impedance matching and increases
the overall gain. The circuit parameters are given in the table 1.
Parameter name
Values
Parameter name
Values
RG
100Ω
W
( )1
L
120
. 18
R D2
250 Ω
W
( )2
L
160
. 18
R D5
100 Ω
W
( )3
L
30
. 18
R FD1
150 Ω
W
( )4
L
30
. 18
R FD2
500 Ω
W
( )5
L
60
. 18
Table.1.design parameters
The performance of an UWB LNA is defined in terms of FOM as defined in [6] is adopted.
FOM = 20 . log10 (
IIP3[mW] х Gain[lin] х BW[GHz]
)
Pdc [mW] х (NF[Lin]−1)
Where Pdc is the power consumption.
III. EXPERIMENTAL RESULTS
The LNA is simulated using 180-nm CMOS process technology. To avoid parasitic
inductances of bond wires, the dc probes are used. Here S parameters, IIP3 and NF are
simulated using CADENCE 6.1.5 Design Tool. The schematic and test bench diagram of the
proposed LNA are shown in the figure 4 and figure 5 respectively.
The simulated S21 is shown in Fig.6, where the maximum value of S21 is 11.2 dB at a
frequency range of 4 GHz to 7 GHz. Fig.7 shows that the simulated S11 is -10.5dB within a
frequency range of 6-8GHz.The simulated value of S22 is shown in Fig.8. Here the value of
S22 is -12 dB to -11dB within the frequency range of 5 GHz to 7 GHz, which is maximum
and at 3 GHz and the minimum value of S22 is -12.8dB. Fig.9 demonstrates that the
simulated NF is 2.4 dB at 4.4 GHz. Two tone testing is done with 2.5GHz spacing for thirdorder inter-modulation distortion, which is demonstrated on Fig.10 in which the third-order
output power is below -12dBm at an input power of -5dBm and an IIP3 of -2.8dBm. Fig.11
shows the conversion gain of 10.8dB at 10.5GHz.
Fig. 4 Schematic of the proposed LNA
Fig.5 Equivalent test bench schematic of the
proposed LNA using cadence tool.
Fig.6.Simulated S21 of the LNA
Fig.7.Simulated S11 of the LNA
Fig.8.Simulated S22 of the LNA
Fig.9.Simulated NF of the LNA
Fig.10.Simulated IIP3 of the LNA
Fig.11.Simulated conversion gain of the LNA
Table II shows the performance summary of this work and compares with previous published
wideband LNAs.
TABLE II
PERFORMANCE SUMMARY AND COMPARISON
Ref.
CMOS
process
Frequency
(GHz)
NF
(dB)
10
Conversion
Gain (dB)
(Power)
10.5
Inductor
Power
(mW)
FOM
(dB)
2.7-3.3
IIP3
(dB
m)
-3.5
7
65nm
no
13.7
2.05
8
180nm
1.6
7.7
1.9-2.2
0
no
35
-13
9
180nm
1.05-3.05
10.9
2.57
-0.7
no
12.6
-4.6
10
90nm
1.6-25
10.7
2.92
4
yes
21.6
20.8
11
90nm
22.1
10.7
4.3
-2.67
yes
8.4
9.2
This
Work
180nm
3.1-10.6
10.8
2.4
-2.8
no
8.9
14.5
IV. CONCLUSION
The design of a 3.1-10.6GHz ultra wide band (UWB) low noise amplifier (LNA) using
resistive feedback gain enhancing technique for Ultra Wide band receiver is illustrated here.
It is an inductor less, low power, low noise LNA. It is having a power gain of 10.8 dB, a
noise figure of 2.4 dB at 4.8 GHz and an IIP3 of -2.8dBm. The power consumed by the
circuit is 8.9 mW. In addition to the enhancement of gain, the proposed LNA achieves wide
bandwidth with small power consumption and lowest noise figure. The resistive feedback
gain enhancing technique improves the FOM compared with previous wideband LNAs;
hence it is suitable for wideband and multi-standard applications.
REFERENCES
[1]
S. Roy, J. R. Foerster, V. S. Somayazulu, D. G. Leeper,“Ultrawideband Radio
Design: The Promise of High-Speed, Short-Range Wireless Connectivity”,
Proceedings of the IEEE, vol. 92, no. 2, pp. 295-311, february 2004.
[2]
K. Moez, M. I. Elmasry, “A Low-Noise CMOS Distributed Amplifier for
UltraWide-Band Applications”, IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 2, FEBRUARY 2008.
[3]
Mei-Fen Chang-Ching Wu, Wen-Shen Chou, Wuen, Kuei-Ann Wen, “A low power
CMOS low noise amplifier for ultra-wideband wireless applications”, IEEE Int.
Symp. Circuits Syst. 5 (2005) 5063–5066.
[4]
S. Arshad, F. Zafar, R. Ramzan, Q. Wahab,” Wideband and multiband CMOS LNAs:
State-of-the-art and future prospects”, Microelectronics Journal,2013.
[5]
Yueh-Hua Yu, Yong-Sian Yang, Yi-Jan Emery Chen,” A Compact Wideband CMOS
Low Noise Amplifier With Gain Flatness Enhancement”, IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010.
[6]
M. Okushima, J. Borremans, D. Linten, G. Groeseneken, “A DC-to-22 GHz 8.4 mW
compact dual-feedback wideband LNA,” in Proc. IEEE Radio Frequency Integrated
Circuits Symp., pp. 295–298, Jun. 2009.
[7]
Ke-Hou Chen, Shen-Iuan Liu, “ InductorlessWideband CMOS Low-Noise Amplifiers
Using Noise-Canceling Technique ” IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS—I: regular papers, vol. 59, no. 2, pp. 305-314 february 2012.
[8]
F. Bruccoleri,E. A. M. Klumperink, and B. Nauta, “Wide-band CMOS low noise
amplifier exploiting thermal noise canceling,” IEEE J. Solid- State Circuits, vol. 39,
no. 2, pp. 275–281, Feb. 2004.
[9]
J. Kim, S. Hoyos, and J. Silva-Martinez, “Wideband common-gate CMOS LNA
employing dual negative feedback with simultaneous noise, gain, and bandwidth
optimization,” IEEE Trans. Micorw. Theory. Tech., vol. 58, no. 9, pp. 2340–2351,
Sep. 2010.
[10]
H.-K. Chen, Y.-S. Lin, and S.-S. Lu, “Analysis and design of a 1.6–28-GHz compact
wideband LNA in 90-nm CMOS using a pi-match input network,” IEEE Trans.
Micorw. Theory. Tech., vol. 58, no. 8, pp. 2092–2104, Aug. 2010.
[11]
M. Okushima, J. Borremans, D. Linten, and G. Groeseneken, “A DC-to-22 GHz 8.4
mW compact dual-feedback wideband LNA,” in Proc. IEEE Radio Frequency
Integrated Circuits Symp., pp. 295–298, Jun. 2009.