Stratix II GX-based Bit-Error Rate Tester for Versatile Link Project
Annie Xiang, Andy Liu, Datao Gong and Jingbo Ye
Physics, Southern Methodist University, Dallas, TX , USA
{cxiang, liu, dtgong, yejb}@smu.edu, http://www.physics.smu.edu/web/
Summary
Using FPGA-based Bit Error Rate Tester (BERT), we can measure the performance of a wide range of
digital communication systems. In particular, we can use it to evaluate versatile link at component,
subsystem and network level. Compared with traditional standalone BERT equipment, FPGA-based
BERT is much cheaper. It is also more feasible to set up for different DUTs in irradiation tests. Expedient
customization is another major advantage of FPGA implementation. We propose here a knowledge
sharing database that consists of several IP components. This note outlines potential features to be
accommodated in the knowledge-base and discusses a reference test case.
Introduction
Many of the versatile link working group members have hands-on experience with Altera’s Stratix II GX
EP2SGX90 signal integrity development board. This kit includes the hardware and software sufficient to
develop a BERT capable of verifying and characterizing high-speed serial interfaces. Although the
architecture and functionality discussed are general to all FPGA-based BERT, the following design and
reference are based on this specific device. There are, however, alternative platforms with worthy
advantages, such as Xilinx ‘s Virtix IV and beyond, that are worth future exploration.
The FPGA BERT generates and verifies serial data passed through a point-to-point data link. Its
embedded transceiver contains supporting logic and full-duplex channels to drive various interfaces. PC
user interface through USB enables feature settings and data analysis settings. A block diagram of a
typical serial link BER test is shown in figure. For various purposes, the component such as LD, PD, the
subsystem, such as SFP+ module and ASIC blocks, such as serializer/deserializer, encoder/decoder etc.
can be verified.
Figure 1. Block diagram of an FPGA-based BER test setup
A BER test can simply investigate data bit stream to verify the physical layer robustness. It can also
incorporate coding schemes, link controls and other advanced functions to extend the study of SEE
mitigation.
We conceive three levels of BERT implementations based on this embedded FPGA
architecture. At the basic level, only simple PRBS BER is tested on non-coded data transmission. At the
second level, 8B/10B encoded data with link status monitoring is implemented. Functions such as
comma insertion and detection are also required. At the third level, 64B/66B encoding for higher
throughput, forward error detection and correction schemes are implemented and their effects on the
link signal transmission integrity are to be examined.
Stratix II GX Transceiver and Development Kit
The Stratix II GX FPGA dedicates the right side banks to embedded transceiver circuitry to transmit and
receive high-speed serial data streams. Each transceiver provides both PCS (physical coding sublayer)
and PMA (physical media attachment sublayer) implementations in support of a number of protocols
and operation modes with build-in blocks and featured IPs. The PCS portion of the transceiver consists
of word aligner, byte ordering, 8b/10b encoder et. al. blocks. The PMA portion of the transceiver
consists of the serializer/deserializer, clock/data recovering blocks as well as the high-speed differential
buffer with pre-emphasis, equalization and other programmable features. Figure 2. shows the function
blocks of a Stratix II GX transceiver.
Figure 2. Function blocks of a Stratix II GX transceiver
The Stratix II GX device family supports up to 5 transceiver blocks and each transceiver block contains 4
transceiver channels. The transceiver channels can be configured to operate in basic mode from
600Mbps to 3.125Gbps in signle-width mode and from 1Gbps to 6.375Gbps in double width mode.
There are a number of supported protocols, such as PCIe, Gigabit Ethernet, XAUI and Serial RapidIO, etc..
Each transceiver block consists of two transmitter PLLs shared among the four transmitters. Therefore
there are two reference input clock selectable. Each of the four receivers has its own individual PLL and
clock recovery unit (CRU). The CRU can be set to lock-to-reference mode, lock-to-data mode or
automatic mode, where the CRU switches from reference to data when the prescribed threshold is
reached.
Transmitter and receiver phase compensation FIFO buffer are used at the transceiver and FPGA
boundary and cannot be bypassed. They compensate for skews between transceiver clock domain and
FPGA clock domain.
If the FPGA interface cannot match up with the throughput of the transceiver with sufficient timing
margin, the byte serializer is used in the transmitter. It takes wider words from FPGA and converts them
into smaller words for use in the transceiver. Deserializer is used on the receiver correspondently. And
each receiver has an optional byte ordering block available for some functional mode to restore the
expected word ordering after the byte deserializer.
Many protocols use 8b/10b encoding, which ensures sufficient data transitions and DC-balanced stream.
8b/10b encoder and decoder are part of the transceiver PCS blocks and can be by-passed. They conform
to the IEEE 802.3 standard.
Word aligner offers the functions of pattern detection, link control and status signaling, as well as run
length violation, disparity check and bit-slip etc in some modes. It detects word patterns, aligns word
boundaries, and signals synchronization according to protocol specific or custom defined state machine.
The Stratix II GX employs high-speed IO buffers at rates up to 6.375Gbps. These buffers are of 1.2V and
1.5V PCML standard and contain pre-emphasis, programmable on-chip termination, programmable
voltage output differential and equalization.
There are separate reset ports provided to control the PCS portion and PMA portion of the transmitter
and receiver. Combined with FPGA logic, we can implement customized reset sequence
The ALT2GXB megafunction provides a step-by-step menu selection to configure the transceiver
statically.
A simplified controller module ALT2GXB_RECONFIG is also offered to configure the
transceiver dynamically. The supported configurable include data rates, protocols and analog settings of
the buffers.
The current Stratix II GX EP2SGX90 signal integrity development board employs one EP2SGX90E device,
which contains 3 transceiver blocks and supports up to 12 transceiver channels. On the evaluation board
6 full duplex channels are setup and connected to SMAs.
Channel 0 transmits through GXB_TX1 differential output and GXB_RX1 differential output, which are
located in bank 13, wired in micro strip to optimize signal integrity; channel 1 to channel 4 are
connected to GXB_TRX4 to GXB_TRX7 in bank 14; channel 5 is connected to GXB_TRX8 in bank 15, also
wired in micro strip but with 40’ FR4 add-on.
Transceivers in bank 13 and 15, i.e. channel 0 and channel 5, take input reference clocks from on board
156.25MHz crystal or SMA input. Transceivers in bank 14, i.e. channel 0 and channel 5, take input
reference clocks from on board 156.25MHz crystal or a set of PCIe clocks of 25MHz, 100MHz, 125MHz
and 200MHz.
Pattern Generator and Error Checker
While we instantiate the transceivers through provided megafunctions, we should create custom data
generator and checker for the BER test. The BIST (build-in self test) block is good for verification but not
suitable for BER test.
Usually, pseudo-random binary sequence (PRBS) is implemented in polynomial shifter fashion as a basic
test pattern. For example, a Fibonacci LFSR instantiation of X7+x6+1 for 2^7-1 PRBS or x23+x18+1 for
2^23-1 PRBS or x31+x28+1 for 2^31-1 PRBS generation and verification should be adequate to comply
with link stress as specified by Ethernet or Fiber channel standards. When the link is first up, the error
checker uses the incoming data as seed to generated expected output pattern, until pattern match is
declared. The checker then switches to internal seed. Therefore, when the link is stable, incoming
erroneous bit cannot disturb the output generation of error checker. Link up is declared when errorfree incoming data for seven consecutive clock. It is deserted when it sees bit error for seven
consecutive clocks.
Error injection to simulate single bit error should also be provided. When error injection control is
asserted, bit 0 on the output is flipped to inflict a single bit error. Error counts and time stamp, and/or
error bits are to be logged in asynchronous FIFO for user access. Error statistics can be performed on the
PC side.
On the second level of BERT implementation, when the link transmits 8B/10B encoded data, transmitter
and receiver state machines should be created. For example, the error checker works with Idle detect
and word alignment block to delimit the incoming data stream and when consecutive valid or invalid
codes are received, declares link up or link down. Error injection block that invokes single bit error,
multi-error but within valid link up status, frame errors that cause link down flag to be raised are created.
On the third level of BERT implementation, pattern generator, error checker work in similar fashion with
added PCS blocks.
User Interface
The Altera development kit supports communication with a PC through USB port via FTDI interface, in
FIFO mode, whose Labview drivers are readily accessible. We only need to develop a handshake
protocol to transfer settings, controls and data. An example GUI panel is shown in Figure 3.
The evaluation board also provides non-GUI type of user access, there are 8 LEDs, two 7-segment
displays, two DIP switches, one of which is used for clock setting, and 6 push buttons at the users service.
Figure 3. Labview application front panel
Reference Design
SMU modified the Altera example design to implement a basic BERT. The VHDL /verilog program is
extended and a Labview VI coded to accommodate USB interface with the PC.
Channel 0 is used and the other channels are powered down. The input clock is the 156.25MHz on
board OSC (which requires S8-6 in open, S8-1 to 5 in close and S9 in the OSC position.), and the serial
data rate is 5Gbps. Data patterns supported are PRBS23, PRBS7 and high frequency pattern (1010). Data
interface is 40 bits wide in FPGA fabric.
Currently the Labview only functions displaying the Error statistics. Dynamic setting are not configurable
during run-time through Labview. But on board manual interface operation are still valid. Please refer to
the development kit user guide A-2 to A-6 for instruction.
Future Work
Level 2 and level 3 BERT
64/66b encoder and scrambler
Bath tub scan
Currently Xilinx provide build-in 64/66 and sample point shift which are worth exploring.
Reference
1. http://www.altera.com/literature/hb/stx2gx/stxiigx_sii5v2_01.pdf
2. http://www.xilinx.com/support/documentation/application_notes/xapp713.pdf
3. http://www2.tek.com/cmsreplive/tirep/3262/2007.11.14.09.39.22_3262_EN.pdf
4. http://www.home.agilent.com/agilent/faqDetail.jspx?cc=US&lc=eng&ckey=1481106&nid=536902258.0.00&id=1481106
5. http://www.ansoft.com/si/pdf/SERDES_FPGA_system_simulation_using_the_Xilinx_design_kit_
FINAL.pdf
6. http://www.bertscope.com/Literature/White_Papers/Pre_Emph_Altera.pdf
7. http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/FPGATDC_abs09.pdf
8. IEEE standard 802-3ae-2005
9. INCITS T11 FC-PI-4