ME 4447/6405
November 6th, 2012
Ellen Qiulei Huang
Juan Orphee
Austin Farmer

• Introduction
-- What is PWM?
• Analog vs. Digital Actuation
• Consideration on PWM frequency
• Implementation on the HCS12
--Register Setup
• Examples of PWM configuration using assembly and C
-- Applications of PWM
2

• Introduction
-- What is PWM?
• Analog vs. Digital Actuation
• Consideration on PWM frequency
• Implementation on the HCS12
-- Register Setup
• Examples of PWM configuration using assembly and C
-- Applications of PWM
3

Ellen Qiulei Huang
• Pulse Width Modulation (PWM) is a technique for delivering partial power to a load via digital means.
• The on-off behavior changes the average power of signal.
• Output signal alternates between on and off within specified period.
• http://www.youtube.com/watch?v=Lf7JJAAZ xEU
4

Ellen Qiulei Huang
A percentage measurement of how long the signal stays on.
On Off
V
H
Duty Cycle (D)
V
L
Period (T)
5

Ellen Qiulei Huang
• Duty Cycle:
Duty Cycle

On Time

100 %
Period
• Average signal : V avg

D

V
H


1

D


V
L
(Usually, V
L is taken as zero volts for simplicity.)
On Off
V
H
V
L
Duty
Cycle (D)
Period (T)
6

Ellen Qiulei Huang
• The average value of a PWM signal increases linearly with the duty cycle
7

Ellen Qiulei Huang
• Lead edge is fixed, the trailing edge is modulated.
On Off On Off
V hi
V hi
V lo
Duty
Cycle
~60% V lo
Duty
Cycle
~30%
Period Period
8

Ellen Qiulei Huang
• Trailing edge is fixed, lead edge is modulated.
V hi
Off
V lo
On
Duty
Cycle
~60%
Period
Off
V hi
V lo
Duty
Cycle
~30%
On
Period
9

Ellen Qiulei Huang
• Center of signal is fixed, both edges are modulated
V hi
Off On Off
Duty
Cycle
~30%
V lo
Period
V hi
Off
V lo
On
Duty
Cycle
~60%
Period
Off
10

Ellen Qiulei Huang
• Analog PWM signals can be made by combining a saw- tooth waveform and a sinusoid
• PWM output is formed by the intersection of the saw-tooth wave and sinusoid.
• PWM toggles when sine equals saw-tooth.
11

Ellen Qiulei Huang
• Limit signals are offset from a reference
• When output signal reaches limits, PWM state changes
12

Ellen Qiulei Huang
• Quantizer converts the difference between output and limits.
• Quantizer can be realized with a comparator whose output is 1 or 0 if the input signal is positive or negative.
13

Ellen Qiulei Huang
• PWM signal generated by Delta method
• Error = Ref – PWM
• Error is integrated.
When integration signal reaches limit, PWM state changes.
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Ellen Qiulei Huang
15

Ellen Qiulei Huang
Input signal (PWM)
Ripple
Output signal (actuator response)
16

Ellen Qiulei Huang
• Resolution: Inversely proportional to the number of distinct duty cycles you can generate for a given period
• Transitions can only occur on a clock tick
• Frequency limited by your clock and desired resolution
• Example: 8 MHz clock, choose PWM to be 4 MHz
• Limited resolution: only 3 duty cycles to choose from
17

Ellen Qiulei Huang
Lower Limits
1. Must be at least 10 times higher than the control system frequency
2. Higher than 20kHz – audible frequency of sounds to avoid annoying sound disturbances.
3. If too low the motor is pulsed, not continuous, because the motor’s inductance can not maintain the current
4. Inverse of frequency should be much less than the motor/load time constant
5. Higher error from ripple voltages
1. If too high the inductance of the motor causes the current drawn to be unstable
2. MOSFET transistor generates heat during switching
3. Limited by resolution of controller
4. Eddy currents generated in electromagnetic coils which lead to adverse heating
5. Heat losses in electromagnetic materials is proportional to frequency squared
18

Ellen Qiulei Huang
•
•
•
•
•
Average value proportional to duty cycle, D
Low power used in transistors used to switch the signal
Fast switching possible due to MOSFETS and power transistors at speeds in excess of 100 kHz
Digital signal is resistant to noise
Less heat dissipated versus using resistors for intermediate voltage values
19

Ellen Qiulei Huang
• Cost
• Complexity of circuit
• Voltage spikes
• Susceptible to Electromagnetic Interference
20

• Introduction
-- What is PWM?
• Analog vs. Digital Actuation
• Consideration on PWM frequency
• Implementation on the HCS12
--Register Setup
• Examples of PWM configuration using assembly and C
-- Applications of PWM
21

Juan Orphee
Pulse Width Modulator: PWM8B6CV1
• Use Port P
• Six 8-bit channels or three 16-bit channels for greater resolution
• Each channel produces an independent PWM signal
• Two choices of clock sources per channel which provides for a wide range of frequencies

PWM Block Diagram
-Each channel needs setup of the following registrars:
1) Enable/disable
2) Signal Polarity
3) Clock A or SA, B or SB
4) Prescale A and B clocks
5) Center Alignment Enable
6) Control Register
7) Prescale SA and SB clocks
8) Counter
9) Period
10)Duty Cycle
Define PWM signal
11)Emergency Shutdown
V hi
Duty
Cycle
V lo
Period
Juan Orphee

PWM Register Memory Map Juan Orphee

1-PWM Enable Register (PWME)
Juan Orphee
• PWME in address: $00E0
• Set PWMEx to 1 to enable the channel
• Set PWMEx to 0 to disable the channel

2-PWM Polarity Register (PWMPOL)
Juan Orphee
• PWMPOL in address: $00E1
• Set PPOLx to 0, signal goes from low to high
• Set PPOLx to 1, signal goes from high to low
Signal Starts Here
Zero Line

3-PWM Clock Select Register (PWMCLK)
Juan Orphee
• PWMCLK in address: $00E2
• Set PCLK(5/4/1)  0 to use clock A
• Set PCLK(5/4/1)  1 to use clock SA
• Set PCLK(3/2)  0 to use clock B
• Set PCLK(3/2)  1 to use clock SB
Note: choice of Prescale will determine clock selection

Juan Orphee
4-PWM Prescale Clock Select Register (PWMPRCLK)
• Located at $00E3
• Used to prescale clocks A and B
Prescaler =
(2
N
Bus Clock Frequency
 
Desired PWD Frequency
N = bit resolution
-Similar for Clock B
Bus Clock HCS12 = 8 MHz
-If calculated prescaler > 128 then use clock SA
-How to convert time (e.g. in seconds) to cycles?
Time (sec) x Clock Frequency = Time (sec) x (Buss Clock/Prescaler)

Duty
Cycle
Period
Time per clock cycle (sec) = Prescaler x Time (sec) per bus clock cycle
125x10(-9) sec for HCS12
T (sec)
-Resolution = Maximum Clock Counts
-Example: An 8 bit counter can count 2^N-1 = 255 clock cycles
PWM Frequency =
1
=
1 tion)
PWM Frequency =
1
 
PWM Frequency =
Bus Clock Frequency
(Prescaler)×(Resolution)
Prescaler =
(2
N
Bus Cloc k Frequency
 
29

Juan Orphee
5-PWM Center Align Enable Register(PWMCAE)
• Located at $00E4
• Set CAEx to 0 for left align signal
• Set CAEx to 1 for center align signal
• Note:
– Can only be set when channel is disabled

Left vs. Center Aligned
Juan Orphee
Not To Scale
PWM Signal Starts

6-PWM Control Register (PWMCTL)
Juan Orphee
• PWMCTL : Located at $00E5
• Set CONxy to 0 to keep 6 PWM channels separate (8-bit)
• Set CONxy to 1 to concatenate PWM channels x and y together (16-bit).
• x becomes the high byte and y becomes the low byte
• Channel y determines the configuration
• Bits PSWAI and PFRZ set either wait or freeze mode
• Note
– Changes only occur when both channels are disabled

Juan Orphee
7-PWM Scale A Register (SA Clock) (PWMSCLA)
• Located at $00E8
• Programmable scaling of clock A to generate clock SA
• Note

PWM Scale B Register (PWMSCLB)
Juan Orphee
• Located at $00E9
• Programmable scaling of clock B to generate clock SB
• Note

Juan Orphee
8-PWM Channel Counter Register (PWMCNT)
• Located at $00EC through $00F1
• One per channel
• It tracks the cycle counts
• When channel is enabled up-count starts
• Note
– Writing to counter while a channel is enable can cause irregular PWM cycles

Juan Orphee
Counter: Left vs. Center Aligned
PWM Signal Starts
• In the left aligned mode, the PWM counts up until
(period-1) and resets to zero.
• In the center aligned mode, the PWM counts up until (period-1) and counts down to zero.
• Note: Period (PWMPER) is expressed in number of cycles

Juan Orphee
9-PWM Channel Period Register (PWMPER)
=$00F2
• Located at $00F2 through $00F7
• PWMPERx
• Store a hexadecimal value to limit maximum value of counter
• Note : Changes occur when one of following happen
– Current period ends
– Counter is written to
– Channel is disabled
What is my PWMPER?
PWMPER (cycles) = PWM Period(sec) x Clock Freq(cycles/sec)

Juan Orphee
10-PWM Channel Duty Register (PWMDTY)
• Located at $00F8 through $00FD
• Store a hexadecimal value to control when signal changes
• Changes occur when:
– Current period ends
– Counter written to
– Channel is disabled
• e.g for 60% duty cycle:
PWMDTY = 0.6xPWMPER (in cycles)

$00FE
11-PWM Shutdown Register (PWMSDN)
Juan Orphee

• Introduction
-- What is PWM?
• Analog vs. Digital Actuation
• Consideration on PWM frequency
• Implementation on the HCS12
- Register configuration
• Example of PWM configuration using Assembly and C Code
• Applications of PWM
40

Austin Farmer
• Use PWM Channel 0
• Positive polarity (signal goes from high to low)
• Left aligned output
• Frequency: 40 kHz
– Period = 1/Frequency = 1/40 kHz = 25 μs
• Choose clock source using resolution:
– Bus clock frequency: 125 ns  25 μs / 125 ns = 200 cycles
– 200 < 255, select clock A with prescaler = 1
• Duty Cycle = 50%
– (50% * 200 cycles) = 100 cycles
41

Austin Farmer
PWME
PWMPOL
EQU $00E0
EQU $00E1
PWMCLK EQU $00E2
PWMPRCLK EQU $00E3
PWMCAE EQU $00E4
PWMPER0 EQU $00F2
PWMDTY0 EQU $00F8
* 1-PWM Enable Register
* 2-PWM Polarity Register
* 3-PWM Clock Select Register
* 4-PWM Prescale Clk Select Reg.
* 5-PWM Center Align Enable Reg.
* 9-PWM Channel 0 Period Register
* 10-PWM Channel 0 Duty Register
ORG $1000
LDAA #$01
STAA PWMPOL
LDAA #$00
STAA
STAA
PWMCAE
PWMCLK
*Positive polarity (starts high)
*Left aligned output
*Use Clock A
STAA PWMPRCLK *Clock A prescaler = 1
LDAA #$C8
*Period =(25μs/125ns)= 200 = $C8 STAA PWMPER0
LDAA #$64
STAA PWMDTY0
LDAA #$01
STAA PWME
...
*Duty cycle=(200*50%)= 100 = $64
*Enable PWM Channel 0

Austin Farmer
#include <hidef.h> /* common defines and macros */
#include <mc9s12c32.h> /* derivative information */
#pragma LINK_INFO DERIVATIVE “mc9s12c32”
// Set up chip in expanded mode
MISC = 0x03;
PEAR = 0x0C;
MODE = 0xE2;
//Set up PWM Registrer
PWMCLK = 0; // Sets source clock to clock A
PWMPOL = 1;
PWMCTL = 0;
// Positive Polarity (signal goes from high to low)
// Makes all channels 8-bit
PWMCAE = 0; // Signals are left aligned
PWMPER0 = 200; // Sets the period of the signal to 200 clock cycles
PWMDTY0 = 100; // Makes the duty cycle 100 clock cycles (50% of 200)
PWMPRCLK = 0; // Sets the prescaler to 1
PMWE = 1;
….
// Enables and starts Channel 0 of PWM
43

Austin Farmer
• In the past, motors were controlled at intermediate speeds by using variable resistors to lower delivered power
(inefficient)
– Example: Foot pedal on sewing machines is a variable resistor connected in series to control speed
• PWM provides a more compact way of applying adjustable power to devices
44

Austin Farmer
•
•
•
•
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Austin Farmer
• PWM is used in efficient voltage regulators
• With appropriate duty cycle, the output will approximate voltage at the desired level
• Switching noise can be filtered
46

Austin Farmer
• Commonly used to control the speed of a DC motor
• Continuous application of PWM cycle results in average voltage being applied to motor
• Output speed of motor is proportional to input voltage
• http://www.youtube.com/watch?v=Lf7JJAAZx
EU
• Used in Lab 3
47

Austin Farmer
• Pulses of various lengths will be sent at regular intervals
(the carrier frequency of the modulation)
• The widths of the pulses correspond to specific data values encoded at one end and decoded at the other
• Leading edge of the data used as clock because small offset is included
• More resistant to noise effects than binary data alone
48

Austin Farmer
• In audio circuits, PWM can produce an effect similar to a chorus
• Used in new class of efficient audio amplifiers
• PWM dimming provides superior color quality in LED video display (millions of colors)
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