Iterative Integer Division
Techniques
Shantanu Dutt
UIC
Division – Basics
• Radix r division is essentially a trial-and-error process, in which the
next quotient bit is chosen from 0, …, r-1
• SHR-Divisor Method: Start subtraction of V
from left most position of D, considering as many
digits of D as there are in the V (ignoring leading
0’s). After subtraction, consider the next lower
digit of D (i.e., in the “partial remainder”), and
align D*(current Q digit) so that LS digits align,
and subtract from the PR from that digit to its MS
non-0 digit. This is almost equivalent to a SHR V
for next subtraction every iteration.
088 = Q
V=4
353 = D
-0
353
- 32
033
- 32
001 = R
• Binary division is much simpler, since the next quotient bit is either a 0
or 1 depending on whether the partial remainder is less than or greater
than/equal to the divisor, respectively
• Integer division: Given 2 integers D the dividend and V the divisor, we
want to obtain an integer quotient Q and an integer remainder R, s.t.
D = V.Q + R, R < V
• Integer–FP division: Given 2 integers D the dividend and V the divisor, we
want to obtain a floating-point (FP) or real quotient s.t.
D ~ V.Q
Division – SHL-Partial-Remainder Method
• Instead of shifting the divisor right by 1 bit, the partial remainder can
be shifted left by one bit (in non-binary case, if the current Q bit is
non-zero)
088 = Q
V=4
353 = D
-0
353
- 32
SHL:
033
330
- 32
0111 = Q
V = 100
SHL:
SHL:
01 = R
SHL:
011101 = D
- 000
011101
011101
- 100
01101
01101
- 100
0101
0101
- 100
001 = R
• If D is n bits and V is k bits (ignoring
leading 0’s), perform n-k+1 iterations of the
SHL & subtract process
•
•
•
•
Division – Handling V with leading 0’s
Some higher order bits of an n-bit V are 0’s
One of the main requisites of correct division by repeated subtraction is that the portion of D (in
general the partial remainder) from which V is being subtracted be < 2.V, since the Q bit can only be 0
or 1
Note that for 6-bit division (n=6), V is stored as a 6-bit # (000100) in the computer. The type of manual
adjustment done in the above example of converting 6-bit subtractions into 4-bit ones (in general, nbit subtractions into k-bit ones, k < n, k is the most significant 1’s position in V) is impractical in
digital hardware (though a complex circuit may be designable to do variable-bit division)
Method 1:
– Shift V to the left by n-k-1 bits (until its MSB=1), and perform the div. for n-k steps (equivalently
D is considered a n+n-k-1 = 2n-k-1 bit #)
– Divide remainder R’ of this process by 2n-k-1 (SHR by n-k-1 bits) to get final remainder R
0111 = Q
V = 100000
SHL:
SHL:
SHL:
011101000 = D
- 000000
011101000
011101000
- 100000
01101000
01101000
- 100000
0101000
0101000
- 100000
001000 = R’
•
•
Division – Handling V with leading 0’s
Method 2: Augment D to the left by n-1 0’s, making D a (2n-1)-bit #, while V remains
an n-bit #. Perform the division for n iterations
Note that this ensures that at least in iteration 1:
–
The MS n bits of D < 2V. It can be proved that this will be true at the beginning
of every iteration, i.e., after subtraction and SHL of the previous iteration
000111 = Q
V = 000100
SHL:
00000011101 = D
- 000000
00000011101
00000011101
- 000000
0000011101
SHL: 0000011101
- 000000
000011101
SHL: 000011101
- 000100
00001101
SHL: 00001101
- 000100
SHL: 00000101
0000101
- 000100
000001 = R
• This is the type of division algorithm
used in a computer/digital-hardware
16
16
16
16
16
and
also n-bit
n’th
n-bit
SHL
2’s Complement Division