文化大學電機系2011年先進電機電子科技研討會
設計於深次微米CMOS製程之功率感知高速類比數位轉換積體電路
(Power-Aware High-Speed ADC in Deep Submicron CMOS)
台大電機系 陳信樹副教授
National Taiwan University
Department of Electrical Engineering
Outline
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Motivation
High-speed ADC IC design example
Digitally-assisted algorithm and architecture
Circuit implementation
Experimental results
Summary
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NTUEE ; Mixed-Signal IC Lab
High-Speed ADC Applications

Ref [1]
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Power-Aware High-Speed ADC Trends
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Power / Energy
 Higher resolution requires more energy to achieve.
Speed / Bandwidth
 Resolution and speed are trade-offs.
Bottleneck
 SAR architecture saves power and chip area, but speed is limited
by its conversion algorithm.
 Pipelined architecture achieves high speed by concurrent
operations, but OPAs consume considerable power.
Digitally assisted ADCs
 Digitally assisted algorithm alleviates analog circuit requirement;
therefore, it takes advantages of advanced processes to trade
little digital power to gain the benefits from analog part.
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High-Speed ADC Energy vs. SNDR
1.E+07
1.E+06
P/fs [pJ]
1.E+05
1.E+04
1.E+03
1.E+02
ISSCC 2010
VLSI 2010
ISSCC 1997-2009
VLSI 1997-2009
FOM=100fJ/conv-step
FOM=10fJ/conv-step
1.E+01
1.E+00
1.E-01
10
20
30
40
50
60
70
80
90
100
110
120
SNDR [dB]
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

Energy is proportional to resolution (SNDR).
FOM (Power / (Sample rate * 2ENOB)) is an indicator to compare different ADC designs.
State-of-the-art ADC designs approach 10fJ/c.s. Current world record is 4fJ/c.s.
Ref [2]
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NTUEE ; Mixed-Signal IC Lab
High-Speed ADC Bandwidth vs. SNDR
1.E+11
ISSCC 2010
VLSI 2010
ISSCC 1997-2009
VLSI 1997-2009
Jitter=1psrms
Jitter=0.1psrms
1.E+10
BW [Hz]
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
10
20
30
40
50
60
70
80
90
100 110 120
SNDR [dB]



Bandwidth is inverse proportional to resolution (SNDR).
State-of-the-art high-speed high-resolution ADCs are limited by clock jitter around
0.1psrms.
Ref [2]
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Experiment 1 - Low-Power High-Speed Two-Step ADC
Shared Resister Ladder
Clock Generator
MDAC1
Vin
3b
Flash
CADC


15
Encoder
and
Digital
Correction
Logic
7
MDAC2

4b
Flash
FADC1
4b
Flash
FADC2
6b
Technology
Resolution
Active area
Supply voltage
Sample rate
SFDR ([email protected])
SNR ([email protected])
SNDR ([email protected])
Power
FoM
0.13μm
6-bit
0.16mm2
1.2V
1-GS/s
40.7dB
33.8dB
33.7dB
49mW
1.24pJ/c.s.
15
Rearrange the timing of two-channel MDACs and apply a
self-timing technique to alleviate comparator comparison
time and charge injection disturbance
Slightly increases CADC accuracy to ease OPA signal
swing design
Ref [3]
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Experiment 2 - Low-Power High-Speed Sub-range SAR ADC
Vinp
Vinn
Vrp
Vrn
Sub Range
Capacitor Array
6b
Fine
Clock
Capacitor
array
output
6b
6b
Coarse
Analog
Circuit
Sample
Gain
Control
6b Registers + overlapping logic
State Control
Technology
Resolution
Active area
Supply voltage
Sample rate
SFDR ([email protected])
SNR ([email protected])
SNDR ([email protected])
Power
FoM
0.13μm
12-bit
0.096mm2
1.2V
10MS/s
69.8dB
61.2dB
59.7dB
3mW
0.38pJ/c.s.
Digital Error Correction Circuit
12b
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Relieve MSB accuracy requirement by the sub-range
concept with overlapping
Reduce total input capacitance by using the double-unitsized coupling-capacitor
Ref [4]
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Experiment 3 - Low-Power High-Speed SAR ADC
Technology
Resolution
Chip area
Supply voltage
Sample rate
SFDR ([email protected])
SNDR ([email protected])
Power
FoM


90nm
10-bit
1.029mm2
1.0V
40MS/s
61.9dB
54.1dB
1.34mW
81.1fJ/c.s.
Attain high conversion speed by adopting non-constant-radix
switching method
Compared to conventional non-binary designs, its DAC
implementation is simpler.
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Experiment 4 - Low-Power High-Speed Pipelined ADC
1
VREF
2
Calibration Sequence Controller
7b SA
Registers
VIN
ClockBoost
Input
Switch
7b SA
Registers
7b SA
Registers
7
7
7
2.5b Stage
with
Calibration
Capacitor
2.5b Stage
with
Calibration
Capacitor
2.5b Stage
with
Calibration
Capacitor
3
Calibration
Comparator
2.5b Stage
3
3
2b SubADC
2
3
Digital Error Correction
Dout
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Technology
Resolution
Active area
Supply voltage
Sample rate
SFDR ([email protected])
SNDR ([email protected])
Power
FoM
90nm
10-bit
0.21mm2
1.2V
320MS/s
66.7dB
51.2dB
42mW
0.44pJ/c.s.
10
Achieve high speed with a low-gain OPA by using digitallyassisted architecture, thus the OPAs have excellent power
efficiency
A simple gain-error self calibration method without external
precise references requires only 168 calibration clock cycles.
Ref [5]
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Digitally-Assisted High-Speed ADC Example (Experiment 4)
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Digitally assisted architecture is future trend to achieve excellent
power efficiency.
10b, several hundreds MS/s Pipeline ADCs are widely used in
wireless and cloud computing systems but suffer from OPA design
in deep submicron CMOS processes.
 Decreased OPA DC gain
 Smaller signal swing
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Pipeline ADC Accuracy
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OPA gain
 Less Ro of MOSFET in advanced technologies
 Reduced gain from each stage of OPA
 More gain stages introduce poles and decrease bandwidth.
 For 10b accuracy, the 1st stage MDAC requires 66dB OPA DC gain.

Capacitor mismatch
 Raw matching can attain 10b accuracy, not an issue!
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Closed-Loop Gain Error

A
1 
1
ACL 
  
 ,
1  A   1  1/  A  
 For finite A, closed-loop gain ACL is smaller than ideal gain, 1/.
 Gain error can be compensated by adjusting .
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MDAC Gain Error
Sub-ADC
Cs
Cs
Cf
Vos
8
Cp
Cs
+Vout
A
-Vout
8 comp.
+Vref -Vref
Vout
8
V
8C  C f  C p


8Cs

 Vin   Di ref  s
Vos  , Di  1, C f  2Cs
8Cs  C f  C p 
8
8Cs
i 1

Cf 
A
 Due to finite A, closed-loop gain is less than ideal value of 4.
  adjustment is proposed to correct MDAC gain error.
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Proposed MDAC with a Calibration Capacitor
Sub-ADC
Cs
Ccal
Cs
Cf
Vos
8
Cp
Cs
+Vout
A
-Vout
8 comp.
+Vref -Vref
 A calibration capacitor, Ccal, is added as a positive feedback to adjust .
 Closed-loop gain can achieve 10b accuracy with low DC gain A of 30dB.
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Self-Calibrated Algorithm (1)
UnderCalibration
MDAC
Vin
Σ
Ideal
MDAC
Σ
AV
1
Vref
8
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Calibration
Comparator
Ideal
MDAC
Vout
Σ
To SAR
Controller
4
4
3
 Vref
8
3
 Vref
8
1
Vref
2
Self-calibrated procedure starts with the last stage MDAC.
After MDAC is calibrated, it is treated as “ideal” MDAC.
Ideal MDACs subtract 3Vref/8 and then multiply 4.
Under-Calibration MDAC samples Vref/8 and then multiplies 4.
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Self-Calibrated Algorithm (2) – Gain Error
Vout ,under _ calibration  (
Vref
8
)  (4   AV )
 AV : gain error
3Vref 
Vref  AV  Vref
 Vref
Vout ,1stage _" ideal "  (
)  (4   AV )  (
)  4 

8 
2
2
 8
Vref  AV  Vref  4
 Vref  AV  Vref  3Vref 
Vout ,2 stage _"ideal "  

)  4 

(
2
8 
2
2

 2
Vout ," N " stage _"ideal " 
Vref
2

 AV  Vref  4 N 1
2
N : number of MDAC stages
 Output is Vref/2 when no gain error
 Using successive approximation method with iterations, the closed-loop
gain reaches 4 with 10b accuracy.
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Proposed ADC Architecture
1
VREF
2
Calibration Sequence Controller
7b SA
Registers
VIN
ClockBoost
Input
Switch
7b SA
Registers
7b SA
Registers
7
7
7
2.5b Stage
with
Calibration
Capacitor
2.5b Stage
with
Calibration
Capacitor
2.5b Stage
with
Calibration
Capacitor
3
Calibration
Comparator
2.5b Stage
3
3
3
2b SubADC
2
Digital Error Correction
Dout
10
 On-chip foreground analog self-calibrated technique
 Gain errors of first three stages are calibrated
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Calibration Step
Opamp
input 2Cs
Cs
Cs
4Cs 2Cs Cs
8Cs 4Cs 2Cs Cs
2Cs
b6
b5
b4
b3
b2
b1
b0
Opamp
output
 128 calibration steps
 Each step affects 0.14 % of MDAC gain (~4) with OPA gain of 40dB
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Calibration Range
120
Output Error= +1 LSB
110
Output Error= -1 LSB
Calibration Step
100
90
80
70
60
50
40
30
20
10
0
30
35
40
45
50
55
60
65
Open-Loop Gain (dB)
 Ccal in this work can calibrate OPA with a minimum DC gain of 30dB
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OPA
VDD
Vcmfb1
Vcmfb2
CALb
VINP
VOP
VON
CALb
VINN
Vb1
Vb2
 Use small L to increase bandwidth without considering gain
 Calibration mode has more compensation capacitance
 Simulation results: DC gain 40dB, closed-loop BW 1.36GHz
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Chip Micrograph
 0.21mm2 active area in 90 nm low-power CMOS
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Measured DNL
Before calibration
After calibration
 Before calibration: +1.7 / -1.0 LSB
 After calibration: +0.7/-0.6 LSB
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Measured INL
Before calibration
After calibration
 Before calibration: +15.6/-15.2 LSB
 After calibration: +0.8/-0.9 LSB
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Measured Dynamic Performance
 At low Fin, SNDR ≈ 54.2dB, ENOB ≈ 8.7bit
 At Nyquist Fin, SNDR ≈ 51.2dB, ENOB ≈ 8.2bit
 ERBW ≈ 160MHz
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Measured FFT
 SNDR ≈ 52.8dB and SFDR ≈ 57.8dB when Fs = 320MHz and Fin =
128MHz
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Measured Performance Summary
JSSC09 [7]
Technology (nm)
90
Calibration Method
Foreground
Sample Rate (MS/s)
500
Resolution (bit)
10
DNL/INL (LSB)
0.4/1.0
Peak SNDR (dB)
55.8
SNDR (dB) at Fs/2
53
SFDR (dB)
Power (mW)
55
FoM (fJ/c.-s.)
301
Active Area (mm2)
0.49
Note
Calibration
circuit is offchip
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ISSCC07 [8]
130
Foreground
/Background
205
10
0.15/0.6
56
56
73.5
92.5
881
0.52
Input buffer
power is
included
This Work
90
Foreground
320
10
0.7/0.9
54.2
51.2
66.7
42
442
0.21
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Summary
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A simple self-calibrated algorithm is proposed to correct gain error
resulting from low gain OPA in deep submicron CMOS.
The self-calibrated process does not require a precise external
reference and can be done within only 168 clock cycles.
Smallest active area of 0.21mm2 in 90nm CMOS including
calibration circuit
The prototype ADC achieves 320MS/s conversion rate, 8.7 ENOB
and only consumes 42mW. Nice power efficiency is obtained.
Power efficiency is the key to high-speed ADC IC designs.
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Reference
[1] http://www.analog.com/library/analogdialogue/archives/39-06/architecture.html
[2] B. Murmann, "ADC Performance Survey 1997-2010," [Online]. Available:
http://www.stanford.edu/~murmann/adcsurvey.html
[3] H. Chen et al., “A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-mm CMOS,” IEEE
J. Solid-State Circuits, vol. 44, no. 11, pp. 3051-3059, Nov. 2009.
[4] H. Chen et al., “A 3mW 12b 10MS/s Sub-Range SAR ADC” in IEEE Asian Solid-State
Circuits Conf. Dig. Tech. Papers, Taipei, Taiwan, pp. 153-156, Nov. 2009.
[5] H. Chen et al., “A 10b 320MS/s Self-Calibrated Pipeline ADC” in IEEE Asian SolidState Circuits Conf. Dig. Tech. Papers, Peking, China, pp. 173-176, Nov. 2010.
[6] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution
Comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.
[7] A. Verma and B. Razavi, ”A 10b 500MHz 55mW CMOS ADC,” IEEE J. Solid-State
Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009.
[8] B. Hernes et al.,”A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V
0.13mm CMOS,” ISSCC Dig. Tech. Papers, pp. 462-463, Feb. 2007.
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Power-Aware High-Speed ADC in Deep Submicron