Software-defined Radio using Xilinx
Anton S. Rodriguez, Michael C. Mensinger, Jr.
Advisors:
Dr. In Soo Ahn and Dr. Yufeng Lu
Department of Electrical and Computer Engineering
Bradley University, Peoria IL 61625
Outline
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Motivation
Project Goals
Equipment
QPSK Theory
Background
System Block Diagram
Requirements
Results
Conclusions
References
Motivation


A Software-defined Radio
(SDR) provides a versatile
wireless communication
solution for a wide range of
applications.
Applications:
• Cell phones
• Military radios
• GPS
• Wi-Fi

The SDR can be easily
modified to the operating
needs of individual
applications.

Lower costs
• No expensive equipment
• No need to replace
hardware
Project Overview

The objective of this project is
to design a communication
radio system on an FPGA
board.

QPSK modulation scheme is
used.
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The main focus is on the
carrier synchronization and
phase ambiguity correction
from the received data.

A Simulink model of the entire
system is designed and then
implemented on the
SignalWave Virtex-II FPGA
board .
Project Goals

Gain an in-depth
understanding about the
FPGA implementation of
carrier synchronization.

Achieve fast acquisition of
carrier synchronization.

Construct a working Simulink
model.
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Implement the Simulink
model on an FPGA board.
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Correct the phase ambiguity
present in the recovered data.
Equipment
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Virtex 4 FPGA
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Xilinx - ISE 9.2 Compiler

SignalWave Virtex-II
FPGA
QPSK Signal Representation
2 bits

s(t) = I(t)*cos(2πfot) – Q(t)*sin(2 πfot)
= A*cos(2πfot + θ(t))
θ(t)
I(t)
Q(t)
π/4
1
1
3π/4
-1
1
5π/4
-1
-1
7π/4
1
-1
Q
I
Background

Previous QPSK Project
Digital Data
(Transmitter)
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Wired
Channel
Digital Data
(Receiver)
Objectives:
• Make this system wireless
• Overcome the following communication problems:
 Multi-path effect
 Carrier synchronization
 Phase ambiguity
Multi-path Effect

Random process.
α1*x(t-τ1)

A number of different paths
may be traveled.
A

Constructive/destructive
interference.
α2*x(t-τ2)
α3*x(t-τ3)
B
Carrier Synchronization

Wireless communication introduces distortion due to channel
imperfections.

The carrier signals must be synchronized to decode data correctly
for both I & Q channels.
Phase Ambiguity

Typical problem in QPSK
systems.

Due to the nature of phaselocking characteristics, a static
phase error is introduced.
Q
Q
I
I
Transmitted and decoded in-phase data
Outline
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Motivation
Project Goals
Equipment
QPSK Theory
Background
System Block Diagram
Requirements
Results
Conclusions
References
System Block Diagram
(Simulink Model)
Channel
Baseband Signal Shaping
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Raised-cosine filtering
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Reduces inter-symbol interference (ISI)

Interpolator/Decimator
Interpolator
Decimator
System Block Diagram
(Simulink Model)
Channel
Phase-Locked Loop
(Carrier Recovery)
Corrected Signal
X(n)
I(n)
FIR
LPF
r(n)
cos(Өon+Ф)
+
-
FIR
LPF
Y(n)
-sin(Өon+Ф)
Q(n)
DDS
Loop Filter
Y(n)*I(n) - X(n)*Q(n)
Functional Requirements

System clock = 50 MHz

Carrier signal frequency = 12.5 MHz
• Data rate = 12.5 Mbps

The frequency offset tolerance is 1 kHz.
Results
(Carrier Synchronization)
QPSK signal
I & Q waveforms
Results
(Phase Ambiguity)
Transmitted Image
Received Image
Results
(Phase Ambiguity Correction)
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Differential coding
Channel
Results
(No Phase Ambiguity / Color)
Transmitted Image
Received Image
Results
(Preserved data / Color)
Conclusions
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QPSK wireless communication system is designed
•
•
•
•
•
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Simulink model is constructed
Carrier synchronization is achieved using digital PLL
Phase ambiguity is resolved using differential coding
Tested whole system with real data
Hardware implementation
Demonstrated the configurability of a software-defined radio
• Expandable to MPSK, MQAM and other modulation schemes
Future Work
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Symbol timing
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Error correcting capabilities
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Implement other modulation schemes
• 8PSK
• 16PSK
• and so on…
Acknowledgements

Dr. Yufeng Lu

Dr. In Soo Ahn

Senior Project Support from
• Department of Electrical and Computer Engineering
Bradley University, Peoria IL 61625
Questions?
References

Chris Dick, Fred Harris, and Michael Rice, FPGA Implementation of Carrier
Synchronization for QAM Receivers, Journal of VLSI Signal
Processing, Copyright © 2004 Kluwer Academic Publishers,
Netherlands.
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Stephens, Donald R. Phase-locked loops for wireless communications digital
and analog implementation. Boston: Kluwer Academic, 1998.
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Vinod Kumar Venkat Reddy Gari, “FPGA-based QPSK transceiver
design”, Technical Report, Department of Electrical and
Computer Engineering, Bradley University, November 2008.

Altera Corporation, "PLL & Clocking Glossary," Altera, 1995-2010.
[Online]. Available: http://www.altera.com. [Accessed: May 1, 2010].