NetFPGA10G
Michaela Blott, September 2010
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Xilinx Confidential – Internal
NetFPGA10G Team
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Michaela Blott
Adam Covington
Jonathan Ellithorpe
Paul Hartke
John Lockwood
Nick McKeown
Sachidanandan Sambandan
Kees Vissers
Tatsuya Yabe
James Zeng
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Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
Motivation/ Objective
 Leverage LATEST technology to create a networking
reference platform
 Enable researchers, students and customers to build
working prototypes of hardware-accelerated networking
systems
 Upgrade interface speeds and components to facilitate faster
and more complex prototypes
 Successor to the highly successful networking research
platform NetFPGA - used by over 500 universities worldwide
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Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
High-Level Specification
QDRII SRAM subsystem
1G or 10G Ethernet
subsystem
PCIe x8, Gen1
Xilinx Virtex5
1G or 10G Ethernet
subsystem
interface
XCV5TX240T-2
FG1759
1G or 10G Ethernet
subsystem
V2
1G or 10G Ethernet
subsystem
• PCIe adapter full size card, dual slot
with extra ATX power connector
RLDRAMII CIO DRAM subsystem
• Standalone operation supported
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Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
High-speed serial
expansion interface
Memory Interface SRAM Subsystem
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–
–
–
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QDRII, 300MHz, CY7C1515JV18-300BZXC
overall density 216Mb
organized in 3 independent 36bit interfaces
64.8Gbps raw access for read and 64.8Gbps for write @ 300MHz
sized to handle flow classification, routing table lookup, flow statistics,
and free and used lists
SRAM
adr, ctl
SRAM
din
36bit
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dout
adr, ctl
36bit
dout
SRAM
din
36bit
adr, ctl
36bit
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
dout
din
36bit
36bit
Memory Interface DRAM Subsystem
– RLDRAMII CIO, 250-300MHz, MT49H16M36HT-25:A
– overall density 2.3Gb (57msec storage of 40Gbps traffic)
– arranged as 2 independent 64bit interfaces (2 components per
interface)
– 76.8Gbps shared raw access for read and write @ 300MHz
– sized to handle packet buffering
RLDRAMII
CIO
adr, ctl
RLDRAMII
CIO
data
2*32=64bit
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adr, ctl
data
2*32=64bit
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
Network Interface Flavours
 PHY: four single-port PHYs (NetLogic AEL2005)
 10G interfaces or 1G interfaces via SFP+ cages
 Supported physical standards:
– 10G direct attach copper, and optical interfaces 10G LRM, 10G SR, 10G
LR
– 1000BaseT and 1000BaseX
FPGA
SFP+ cage
SFI
10G PHY
XAUI (4GTXs @3.125Gbps
SFP+ cage
SFI
10G PHY
XAUI (4GTXs @3.125Gbps
SFP+ cage
SFI
10G PHY
XAUI (4GTXs @3.125Gbps
10G PHY
XAUI (4GTXs @3.125Gbps
SFP+ cage
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SFI
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
Expansion Connector
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purpose:
– allow greater port density,
– support different physical interface flavours
– add daughter cards with
extra memory cards or NSEs/ KBPs
2 flavours:
– daughter card expansion
– board to board with expansion cable
connector:
– Two QTH Samtec connectors
– Designed for XAUI, PCIe, SATA, Infiniband,
HyperTransport, etc.
board to board cable:
– Twinax micro-ribbon cable
– Available in different lengths:
for example 0.5m (100 Gbps);1m (50 Gbps)
– recommended part number: HQDP-020-05.00-STL-SBR-2
distance vs speed:
FPGA
Samtec connector
10GTXs @6.25Gbps
10GTXs @6.25Gbps
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Samtec connector
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
NetFPGA1G – 10G comparison
In a nutshell...
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NetFPGA 1G
NetFPGA 10G
4 x 1Gbps Ethernet Ports
4 x 1Gbps or
4 x 10Gbps Ethernet Ports
4.5 MB ZBT SRAM
64 MB DDR2 SDRAM
27 MB QDRII-SRAM
288 MB RLDRAM-II
PCI
PCI Express x8
Virtex II-Pro 50
Virtex 5 TX240T
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
FPGA Designs
 Stress-test design
 prove the board is functional under maximum load
(temperature, power, noise)
 Basic & full infrastructure designs
 provides basic RTL infrastructure to all users in form of
well-defined and abstracted interfaces
 Planned reference designs
 PCIe-ICAP design (allows configuration of the FPGA via
PCIe)
 Stanford reference router design
 HLS platform
 and others...
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Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
More information ...
 Alpha Program
 Pricing is still being negotiated – heavily subsidized for academics as Micron,
Cypress, NetLogic Microsystems and Xilinx are donating the parts
 Board was built in collaboration with Hitech Global, who will also distribute the
board: (for academic and commercial use)
Visit HiTechGlobal’s website
– http://www.hitechglobal.com/Boards/PCIExpress_SFP+.htm
 Status: Release to Manufacture in the next weeks
 Visit NetFPGA website for the latest update
– http://www.netfpga.org
 If you haven’t already, sign up to netfpga-announce mailing list
– https://mailman.stanford.edu/mailman/listinfo/netfpga-announce
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Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
THANK YOU!
mblott@xilinx.com
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Xilinx Confidential – Internal
Demo
Stress-test Design
Host CPU
RLDRAM memory
test
QDR memory test
FPGA
PCIe test
SFP+ test
Filler
Config &
Flash test
Clock &
PWR test
UART
report
PCIe Application & Driver
Hyperterminal
Config & Flash test
CPLD
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NetFPGA10G board
Test computer
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx