Delay and Power Optimization
with TSV-aware 3D Floorplanning
M. A. Ahmed and M. Chrzanowska-Jeske
Portland State University, Oregon, USA
ISQED 2014
Outline
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Introduction
Electrical Characteristics of 3D Interconnect
3D-Interconnect Electrical Performance
TSV Aware 3D Floorplanning
Experimental Results
Conclusions
Introduction
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3D technology facilitates reduction in wirelength by
vertically stacking dies.
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TSVs are used to connect inter-die signals, and the
RC value of a single TSV depends on TSV
dimensions, technology and used materials.
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It is crucial to consider RC values of TSVs early in
the design phase to evaluate and optimize electrical
performance of 3D ICs.
Introduction
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This paper proposed a TSV-aware 3D floorplanning
tool that concurrently places TSV islands with circuit
blocks.
Electrical Characteristics of 3D
Interconnect
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TSV Capacitance
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CTW: coupling capacitance between a TSV and
wires surrounding the TSV
CTT: coupling capacitance between TSVs
Electrical Characteristics of 3D
Interconnect
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TSV Resistance
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The expression for TSV resistance is given by:
 is the resistivity of the material
lTSV is the height of TSV
ATSV is area of the TSV
Electrical Characteristics of 3D
Interconnect
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Wire Resistance and Capacitance
Electrical Characteristics of 3D
Interconnect
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Wire Resistance and Capacitance
3D-Interconnect Electrical
Performance
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Interconnects Delay
3D-Interconnect Electrical
Performance
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Interconnects Delay
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The difference between the interconnect delay in two cases will
be significant if TSV delay is large.
The floorplanners without TSV delay will treat these cases
similarly.
3D-Interconnect Electrical
Performance
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Interconnects Power Consumption
TSV Aware 3D Floorplanning
Experimental Results
Experimental Results
Experimental Results
Experimental Results
Experimental Results
Conclusions
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This paper presented and discussed delay and
power results of a novel TSV-aware 3D
floorplanning flow with TSV islands.